acpi_pci_machdep.c revision 1.10 1 /* $NetBSD: acpi_pci_machdep.c,v 1.10 2019/10/14 00:16:29 jmcneill Exp $ */
2
3 /*-
4 * Copyright (c) 2018 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jared McNeill <jmcneill (at) invisible.ca>.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #include <sys/cdefs.h>
33 __KERNEL_RCSID(0, "$NetBSD: acpi_pci_machdep.c,v 1.10 2019/10/14 00:16:29 jmcneill Exp $");
34
35 #include <sys/param.h>
36 #include <sys/bus.h>
37 #include <sys/device.h>
38 #include <sys/intr.h>
39 #include <sys/systm.h>
40 #include <sys/kernel.h>
41 #include <sys/extent.h>
42 #include <sys/queue.h>
43 #include <sys/mutex.h>
44 #include <sys/kmem.h>
45
46 #include <machine/cpu.h>
47
48 #include <arm/cpufunc.h>
49
50 #include <dev/pci/pcireg.h>
51 #include <dev/pci/pcivar.h>
52 #include <dev/pci/pciconf.h>
53
54 #include <dev/acpi/acpivar.h>
55 #include <dev/acpi/acpi_mcfg.h>
56 #include <dev/acpi/acpi_pci.h>
57
58 #include <arm/acpi/acpi_iort.h>
59 #include <arm/acpi/acpi_pci_machdep.h>
60
61 #include <arm/pci/pci_msi_machdep.h>
62
63 static int
64 acpi_pci_amazon_graviton_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t *data)
65 {
66 struct acpi_pci_context *ap = pc->pc_conf_v;
67 bus_size_t off;
68 int b, d, f;
69
70 pci_decompose_tag(pc, tag, &b, &d, &f);
71
72 if (ap->ap_bus == b) {
73 if (d > 0) {
74 *data = -1;
75 return EINVAL;
76 }
77 off = f * PCI_EXTCONF_SIZE + reg;
78 *data = bus_space_read_4(ap->ap_bst, ap->ap_conf_bsh, off);
79 return 0;
80 }
81
82 return acpimcfg_conf_read(pc, tag, reg, data);
83 }
84
85 static int
86 acpi_pci_amazon_graviton_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)
87 {
88 struct acpi_pci_context *ap = pc->pc_conf_v;
89 bus_size_t off;
90 int b, d, f;
91
92 pci_decompose_tag(pc, tag, &b, &d, &f);
93
94 if (ap->ap_bus == b) {
95 if (d > 0) {
96 return EINVAL;
97 }
98 off = f * PCI_EXTCONF_SIZE + reg;
99 bus_space_write_4(ap->ap_bst, ap->ap_conf_bsh, off, data);
100 return 0;
101 }
102
103 return acpimcfg_conf_write(pc, tag, reg, data);
104 }
105
106 static ACPI_STATUS
107 acpi_pci_amazon_graviton_map(ACPI_HANDLE handle, UINT32 level, void *ctx, void **retval)
108 {
109 struct acpi_pci_context *ap = ctx;
110 struct acpi_resources res;
111 struct acpi_mem *mem;
112 ACPI_STATUS rv;
113 int error;
114
115 rv = acpi_resource_parse(ap->ap_dev, handle, "_CRS", &res, &acpi_resource_parse_ops_quiet);
116 if (ACPI_FAILURE(rv))
117 return rv;
118
119 mem = acpi_res_mem(&res, 0);
120 if (mem == NULL) {
121 acpi_resource_cleanup(&res);
122 return AE_NOT_FOUND;
123 }
124
125 error = bus_space_map(ap->ap_bst, mem->ar_base, mem->ar_length, 0, &ap->ap_conf_bsh);
126 if (error != 0)
127 return AE_NO_MEMORY;
128
129 return AE_CTRL_TERMINATE;
130 }
131
132 static void
133 acpi_pci_amazon_graviton_init(struct pcibus_attach_args *pba)
134 {
135 struct acpi_pci_context *ap = pba->pba_pc->pc_conf_v;
136 ACPI_STATUS rv;
137
138 rv = AcpiGetDevices(__UNCONST("AMZN0001"), acpi_pci_amazon_graviton_map, ap, NULL);
139 if (ACPI_FAILURE(rv))
140 return;
141
142 ap->ap_conf_read = acpi_pci_amazon_graviton_conf_read;
143 ap->ap_conf_write = acpi_pci_amazon_graviton_conf_write;
144 }
145
146 static const struct acpi_pci_quirk {
147 const char q_oemid[ACPI_OEM_ID_SIZE+1];
148 const char q_oemtableid[ACPI_OEM_TABLE_ID_SIZE+1];
149 uint32_t q_oemrevision;
150 void (*q_init)(struct pcibus_attach_args *);
151 } acpi_pci_quirks[] = {
152 { "AMAZON", "GRAVITON", 0, acpi_pci_amazon_graviton_init },
153 };
154
155 static const struct acpi_pci_quirk *
156 acpi_pci_find_quirk(void)
157 {
158 ACPI_STATUS rv;
159 ACPI_TABLE_MCFG *mcfg;
160 u_int n;
161
162 rv = AcpiGetTable(ACPI_SIG_MCFG, 0, (ACPI_TABLE_HEADER **)&mcfg);
163 if (ACPI_FAILURE(rv))
164 return NULL;
165
166 for (n = 0; n < __arraycount(acpi_pci_quirks); n++) {
167 const struct acpi_pci_quirk *q = &acpi_pci_quirks[n];
168 if (memcmp(q->q_oemid, mcfg->Header.OemId, ACPI_OEM_ID_SIZE) == 0 &&
169 memcmp(q->q_oemtableid, mcfg->Header.OemTableId, ACPI_OEM_TABLE_ID_SIZE) == 0 &&
170 q->q_oemrevision == mcfg->Header.OemRevision)
171 return q;
172 }
173
174 return NULL;
175 }
176
177 struct acpi_pci_prt {
178 u_int prt_segment;
179 u_int prt_bus;
180 ACPI_HANDLE prt_handle;
181 TAILQ_ENTRY(acpi_pci_prt) prt_list;
182 };
183
184 static TAILQ_HEAD(, acpi_pci_prt) acpi_pci_irq_routes =
185 TAILQ_HEAD_INITIALIZER(acpi_pci_irq_routes);
186
187 static void acpi_pci_md_attach_hook(device_t, device_t,
188 struct pcibus_attach_args *);
189 static int acpi_pci_md_bus_maxdevs(void *, int);
190 static pcitag_t acpi_pci_md_make_tag(void *, int, int, int);
191 static void acpi_pci_md_decompose_tag(void *, pcitag_t, int *, int *, int *);
192 static u_int acpi_pci_md_get_segment(void *);
193 static uint32_t acpi_pci_md_get_devid(void *, uint32_t);
194 static pcireg_t acpi_pci_md_conf_read(void *, pcitag_t, int);
195 static void acpi_pci_md_conf_write(void *, pcitag_t, int, pcireg_t);
196 static int acpi_pci_md_conf_hook(void *, int, int, int, pcireg_t);
197 static void acpi_pci_md_conf_interrupt(void *, int, int, int, int, int *);
198
199 static int acpi_pci_md_intr_map(const struct pci_attach_args *,
200 pci_intr_handle_t *);
201 static const char *acpi_pci_md_intr_string(void *, pci_intr_handle_t,
202 char *, size_t);
203 static const struct evcnt *acpi_pci_md_intr_evcnt(void *, pci_intr_handle_t);
204 static int acpi_pci_md_intr_setattr(void *, pci_intr_handle_t *, int,
205 uint64_t);
206 static void * acpi_pci_md_intr_establish(void *, pci_intr_handle_t,
207 int, int (*)(void *), void *,
208 const char *);
209 static void acpi_pci_md_intr_disestablish(void *, void *);
210
211 struct arm32_pci_chipset arm_acpi_pci_chipset = {
212 .pc_attach_hook = acpi_pci_md_attach_hook,
213 .pc_bus_maxdevs = acpi_pci_md_bus_maxdevs,
214 .pc_make_tag = acpi_pci_md_make_tag,
215 .pc_decompose_tag = acpi_pci_md_decompose_tag,
216 .pc_get_segment = acpi_pci_md_get_segment,
217 .pc_get_devid = acpi_pci_md_get_devid,
218 .pc_conf_read = acpi_pci_md_conf_read,
219 .pc_conf_write = acpi_pci_md_conf_write,
220 .pc_conf_hook = acpi_pci_md_conf_hook,
221 .pc_conf_interrupt = acpi_pci_md_conf_interrupt,
222
223 .pc_intr_map = acpi_pci_md_intr_map,
224 .pc_intr_string = acpi_pci_md_intr_string,
225 .pc_intr_evcnt = acpi_pci_md_intr_evcnt,
226 .pc_intr_setattr = acpi_pci_md_intr_setattr,
227 .pc_intr_establish = acpi_pci_md_intr_establish,
228 .pc_intr_disestablish = acpi_pci_md_intr_disestablish,
229 };
230
231 static ACPI_STATUS
232 acpi_pci_md_pci_link(ACPI_HANDLE handle, int bus)
233 {
234 ACPI_PCI_ROUTING_TABLE *prt;
235 ACPI_HANDLE linksrc;
236 ACPI_BUFFER buf;
237 ACPI_STATUS rv;
238 void *linkdev;
239
240 rv = acpi_get(handle, &buf, AcpiGetIrqRoutingTable);
241 if (ACPI_FAILURE(rv))
242 return rv;
243
244 for (char *p = buf.Pointer; ; p += prt->Length) {
245 prt = (ACPI_PCI_ROUTING_TABLE *)p;
246 if (prt->Length == 0)
247 break;
248
249 const u_int dev = ACPI_HIWORD(prt->Address);
250 if (prt->Source[0] != 0) {
251 aprint_debug("ACPI: %s dev %u INT%c on lnkdev %s\n",
252 acpi_name(handle), dev, 'A' + (prt->Pin & 3), prt->Source);
253 rv = AcpiGetHandle(ACPI_ROOT_OBJECT, prt->Source, &linksrc);
254 if (ACPI_FAILURE(rv)) {
255 aprint_debug("ACPI: AcpiGetHandle failed for '%s': %s\n",
256 prt->Source, AcpiFormatException(rv));
257 continue;
258 }
259
260 linkdev = acpi_pci_link_devbyhandle(linksrc);
261 acpi_pci_link_add_reference(linkdev, 0, bus, dev, prt->Pin & 3);
262 } else {
263 aprint_debug("ACPI: %s dev %u INT%c on globint %d\n",
264 acpi_name(handle), dev, 'A' + (prt->Pin & 3), prt->SourceIndex);
265 }
266 }
267
268 return AE_OK;
269 }
270
271 static void
272 acpi_pci_md_attach_hook(device_t parent, device_t self,
273 struct pcibus_attach_args *pba)
274 {
275 struct acpi_pci_context *ap = pba->pba_pc->pc_conf_v;
276 struct acpi_pci_prt *prt, *prtp;
277 const struct acpi_pci_quirk *q;
278 struct acpi_devnode *ad;
279 ACPI_HANDLE handle;
280 int seg, bus, dev, func;
281
282 seg = ap->ap_seg;
283 handle = NULL;
284
285 if (pba->pba_bridgetag) {
286 /*
287 * Find the PCI address of our parent bridge and look for the
288 * corresponding ACPI device node. If there is no node for this
289 * bus, use the parent bridge routing information.
290 */
291 acpi_pci_md_decompose_tag(NULL, *pba->pba_bridgetag, &bus, &dev, &func);
292 ad = acpi_pcidev_find(seg, bus, dev, func);
293 if (ad != NULL) {
294 handle = ad->ad_handle;
295 } else {
296 /* No routes defined for this bus, copy from parent */
297 TAILQ_FOREACH(prtp, &acpi_pci_irq_routes, prt_list)
298 if (prtp->prt_bus == bus) {
299 handle = prtp->prt_handle;
300 break;
301 }
302 }
303 } else {
304 /*
305 * Lookup the ACPI device node for the root bus.
306 */
307 ad = acpi_pciroot_find(seg, 0);
308 if (ad != NULL)
309 handle = ad->ad_handle;
310 }
311
312 if (handle != NULL) {
313 prt = kmem_alloc(sizeof(*prt), KM_SLEEP);
314 prt->prt_bus = pba->pba_bus;
315 prt->prt_segment = ap->ap_seg;
316 prt->prt_handle = handle;
317 TAILQ_INSERT_TAIL(&acpi_pci_irq_routes, prt, prt_list);
318 }
319
320 q = acpi_pci_find_quirk();
321 if (q != NULL)
322 q->q_init(pba);
323
324 acpimcfg_map_bus(self, pba->pba_pc, pba->pba_bus);
325
326 if (ad != NULL) {
327 /*
328 * This is a new ACPI managed bus. Add PCI link references.
329 */
330 acpi_pci_md_pci_link(ad->ad_handle, pba->pba_bus);
331 }
332 }
333
334 static int
335 acpi_pci_md_bus_maxdevs(void *v, int busno)
336 {
337 return 32;
338 }
339
340 static pcitag_t
341 acpi_pci_md_make_tag(void *v, int b, int d, int f)
342 {
343 return (b << 16) | (d << 11) | (f << 8);
344 }
345
346 static void
347 acpi_pci_md_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp)
348 {
349 if (bp)
350 *bp = (tag >> 16) & 0xff;
351 if (dp)
352 *dp = (tag >> 11) & 0x1f;
353 if (fp)
354 *fp = (tag >> 8) & 0x7;
355 }
356
357 static u_int
358 acpi_pci_md_get_segment(void *v)
359 {
360 struct acpi_pci_context * const ap = v;
361
362 return ap->ap_seg;
363 }
364
365 static uint32_t
366 acpi_pci_md_get_devid(void *v, uint32_t devid)
367 {
368 struct acpi_pci_context * const ap = v;
369
370 return acpi_iort_pci_root_map(ap->ap_seg, devid);
371 }
372
373 static pcireg_t
374 acpi_pci_md_conf_read(void *v, pcitag_t tag, int offset)
375 {
376 struct acpi_pci_context * const ap = v;
377 pcireg_t val;
378
379 if (offset < 0 || offset >= PCI_EXTCONF_SIZE)
380 return (pcireg_t) -1;
381
382 if (ap->ap_conf_read != NULL)
383 ap->ap_conf_read(&ap->ap_pc, tag, offset, &val);
384 else
385 acpimcfg_conf_read(&ap->ap_pc, tag, offset, &val);
386
387 return val;
388 }
389
390 static void
391 acpi_pci_md_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val)
392 {
393 struct acpi_pci_context * const ap = v;
394
395 if (offset < 0 || offset >= PCI_EXTCONF_SIZE)
396 return;
397
398 if (ap->ap_conf_write != NULL)
399 ap->ap_conf_write(&ap->ap_pc, tag, offset, val);
400 else
401 acpimcfg_conf_write(&ap->ap_pc, tag, offset, val);
402 }
403
404 static int
405 acpi_pci_md_conf_hook(void *v, int b, int d, int f, pcireg_t id)
406 {
407 return PCI_CONF_DEFAULT;
408 }
409
410 static void
411 acpi_pci_md_conf_interrupt(void *v, int bus, int dev, int ipin, int sqiz, int *ilinep)
412 {
413 }
414
415 static struct acpi_pci_prt *
416 acpi_pci_md_intr_find_prt(pci_chipset_tag_t pc, u_int bus)
417 {
418 struct acpi_pci_prt *prt, *prtp;
419 u_int segment;
420
421 segment = pci_get_segment(pc);
422
423 prt = NULL;
424 TAILQ_FOREACH(prtp, &acpi_pci_irq_routes, prt_list)
425 if (prtp->prt_segment == segment && prtp->prt_bus == bus) {
426 prt = prtp;
427 break;
428 }
429
430 return prt;
431 }
432
433 static int
434 acpi_pci_md_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ih)
435 {
436 struct acpi_pci_prt *prt;
437 ACPI_PCI_ROUTING_TABLE *tab;
438 int line, pol, trig, error;
439 ACPI_HANDLE linksrc;
440 ACPI_BUFFER buf;
441 void *linkdev;
442
443 if (pa->pa_intrpin == PCI_INTERRUPT_PIN_NONE)
444 return EINVAL;
445
446 prt = acpi_pci_md_intr_find_prt(pa->pa_pc, pa->pa_bus);
447 if (prt == NULL)
448 return ENXIO;
449
450 if (ACPI_FAILURE(acpi_get(prt->prt_handle, &buf, AcpiGetIrqRoutingTable)))
451 return EIO;
452
453 error = ENOENT;
454 for (char *p = buf.Pointer; ; p += tab->Length) {
455 tab = (ACPI_PCI_ROUTING_TABLE *)p;
456 if (tab->Length == 0)
457 break;
458
459 if (pa->pa_device == ACPI_HIWORD(tab->Address) &&
460 (pa->pa_intrpin - 1) == (tab->Pin & 3)) {
461 if (tab->Source[0] != 0) {
462 if (ACPI_FAILURE(AcpiGetHandle(ACPI_ROOT_OBJECT, tab->Source, &linksrc)))
463 goto done;
464 linkdev = acpi_pci_link_devbyhandle(linksrc);
465 *ih = acpi_pci_link_route_interrupt(linkdev, tab->SourceIndex,
466 &line, &pol, &trig);
467 error = 0;
468 goto done;
469 } else {
470 *ih = tab->SourceIndex;
471 error = 0;
472 goto done;
473 }
474 }
475 }
476
477 done:
478 ACPI_FREE(buf.Pointer);
479 return error;
480 }
481
482 static const char *
483 acpi_pci_md_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len)
484 {
485 const int irq = __SHIFTOUT(ih, ARM_PCI_INTR_IRQ);
486 const int vec = __SHIFTOUT(ih, ARM_PCI_INTR_MSI_VEC);
487
488 if (ih & ARM_PCI_INTR_MSIX)
489 snprintf(buf, len, "irq %d (MSI-X vec %d)", irq, vec);
490 else if (ih & ARM_PCI_INTR_MSI)
491 snprintf(buf, len, "irq %d (MSI vec %d)", irq, vec);
492 else
493 snprintf(buf, len, "irq %d", irq);
494
495 return buf;
496 }
497
498 static const struct evcnt *
499 acpi_pci_md_intr_evcnt(void *v, pci_intr_handle_t ih)
500 {
501 return NULL;
502 }
503
504 static int
505 acpi_pci_md_intr_setattr(void *v, pci_intr_handle_t *ih, int attr, uint64_t data)
506 {
507 switch (attr) {
508 case PCI_INTR_MPSAFE:
509 if (data)
510 *ih |= ARM_PCI_INTR_MPSAFE;
511 else
512 *ih &= ~ARM_PCI_INTR_MPSAFE;
513 return 0;
514 default:
515 return ENODEV;
516 }
517 }
518
519 static void *
520 acpi_pci_md_intr_establish(void *v, pci_intr_handle_t ih, int ipl,
521 int (*callback)(void *), void *arg, const char *xname)
522 {
523 struct acpi_pci_context * const ap = v;
524
525 if ((ih & (ARM_PCI_INTR_MSI | ARM_PCI_INTR_MSIX)) != 0)
526 return arm_pci_msi_intr_establish(&ap->ap_pc, ih, ipl, callback, arg, xname);
527
528 const int irq = (int)__SHIFTOUT(ih, ARM_PCI_INTR_IRQ);
529 const int mpsafe = (ih & ARM_PCI_INTR_MPSAFE) ? IST_MPSAFE : 0;
530
531 return intr_establish_xname(irq, ipl, IST_LEVEL | mpsafe, callback, arg, xname);
532 }
533
534 static void
535 acpi_pci_md_intr_disestablish(void *v, void *vih)
536 {
537 intr_disestablish(vih);
538 }
539