acpipchb.c revision 1.12
1 /* $NetBSD: acpipchb.c,v 1.12 2019/10/15 00:23:44 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jared McNeill <jmcneill (at) invisible.ca>. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: acpipchb.c,v 1.12 2019/10/15 00:23:44 jmcneill Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/device.h> 38 #include <sys/intr.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/extent.h> 42 #include <sys/queue.h> 43 #include <sys/mutex.h> 44 #include <sys/kmem.h> 45 46 #include <machine/cpu.h> 47 48 #include <arm/cpufunc.h> 49 50 #include <dev/pci/pcireg.h> 51 #include <dev/pci/pcivar.h> 52 #include <dev/pci/pciconf.h> 53 54 #include <dev/acpi/acpivar.h> 55 #include <dev/acpi/acpi_pci.h> 56 #include <dev/acpi/acpi_mcfg.h> 57 58 #include <arm/acpi/acpi_pci_machdep.h> 59 60 #define PCIHOST_CACHELINE_SIZE arm_dcache_align 61 62 #define ACPIPCHB_MAX_RANGES 64 /* XXX arbitrary limit */ 63 64 struct acpipchb_bus_range { 65 bus_addr_t min; 66 bus_addr_t max; 67 bus_addr_t offset; 68 }; 69 70 struct acpipchb_bus_space { 71 struct bus_space bs; 72 73 struct acpipchb_bus_range range[ACPIPCHB_MAX_RANGES]; 74 int nrange; 75 76 int (*map)(void *, bus_addr_t, bus_size_t, 77 int, bus_space_handle_t *); 78 }; 79 80 struct acpipchb_softc { 81 device_t sc_dev; 82 83 bus_space_tag_t sc_memt; 84 85 struct arm32_bus_dma_tag sc_dmat; 86 struct acpi_pci_context sc_ap; 87 88 ACPI_HANDLE sc_handle; 89 ACPI_INTEGER sc_bus; 90 91 struct acpipchb_bus_space sc_pcimem_bst; 92 struct acpipchb_bus_space sc_pciio_bst; 93 }; 94 95 static int 96 acpipchb_amazon_graviton_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t *data) 97 { 98 struct acpi_pci_context *ap = pc->pc_conf_v; 99 int b, d, f; 100 101 pci_decompose_tag(pc, tag, &b, &d, &f); 102 103 if (ap->ap_bus == b) { 104 if (d > 0 || f > 0) { 105 *data = -1; 106 return EINVAL; 107 } 108 *data = bus_space_read_4(ap->ap_bst, ap->ap_conf_bsh, reg); 109 return 0; 110 } 111 112 return acpimcfg_conf_read(pc, tag, reg, data); 113 } 114 115 static int 116 acpipchb_amazon_graviton_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 117 { 118 struct acpi_pci_context *ap = pc->pc_conf_v; 119 int b, d, f; 120 121 pci_decompose_tag(pc, tag, &b, &d, &f); 122 123 if (ap->ap_bus == b) { 124 if (d > 0 || f > 0) { 125 return EINVAL; 126 } 127 bus_space_write_4(ap->ap_bst, ap->ap_conf_bsh, reg, data); 128 return 0; 129 } 130 131 return acpimcfg_conf_write(pc, tag, reg, data); 132 } 133 134 static int 135 acpipchb_amazon_graviton_bus_maxdevs(struct acpi_pci_context *ap, int busno) 136 { 137 if (busno == ap->ap_bus + 1) 138 return 1; 139 140 return 32; 141 } 142 143 static ACPI_STATUS 144 acpipchb_amazon_graviton_map(ACPI_HANDLE handle, UINT32 level, void *ctx, void **retval) 145 { 146 struct acpi_pci_context *ap = ctx; 147 struct acpi_resources res; 148 struct acpi_mem *mem; 149 ACPI_HANDLE parent; 150 ACPI_STATUS rv; 151 int error; 152 153 rv = AcpiGetParent(handle, &parent); 154 if (ACPI_FAILURE(rv)) 155 return rv; 156 if (ap->ap_handle != parent) 157 return AE_OK; 158 159 rv = acpi_resource_parse(ap->ap_dev, handle, "_CRS", &res, &acpi_resource_parse_ops_quiet); 160 if (ACPI_FAILURE(rv)) 161 return rv; 162 163 mem = acpi_res_mem(&res, 0); 164 if (mem == NULL) { 165 acpi_resource_cleanup(&res); 166 return AE_NOT_FOUND; 167 } 168 169 error = bus_space_map(ap->ap_bst, mem->ar_base, mem->ar_length, 0, &ap->ap_conf_bsh); 170 if (error != 0) 171 return AE_NO_MEMORY; 172 173 ap->ap_conf_read = acpipchb_amazon_graviton_conf_read; 174 ap->ap_conf_write = acpipchb_amazon_graviton_conf_write; 175 ap->ap_bus_maxdevs = acpipchb_amazon_graviton_bus_maxdevs; 176 177 return AE_CTRL_TERMINATE; 178 } 179 180 static void 181 acpipchb_amazon_graviton_init(struct acpi_pci_context *ap) 182 { 183 ACPI_STATUS rv; 184 185 rv = AcpiGetDevices(__UNCONST("AMZN0001"), acpipchb_amazon_graviton_map, ap, NULL); 186 if (ACPI_FAILURE(rv)) 187 return; 188 } 189 190 static const struct acpipchb_quirk { 191 const char q_oemid[ACPI_OEM_ID_SIZE+1]; 192 const char q_oemtableid[ACPI_OEM_TABLE_ID_SIZE+1]; 193 uint32_t q_oemrevision; 194 void (*q_init)(struct acpi_pci_context *); 195 } acpipchb_quirks[] = { 196 { "AMAZON", "GRAVITON", 0, acpipchb_amazon_graviton_init }, 197 }; 198 199 static const struct acpipchb_quirk * 200 acpipchb_find_quirk(void) 201 { 202 ACPI_STATUS rv; 203 ACPI_TABLE_MCFG *mcfg; 204 u_int n; 205 206 rv = AcpiGetTable(ACPI_SIG_MCFG, 0, (ACPI_TABLE_HEADER **)&mcfg); 207 if (ACPI_FAILURE(rv)) 208 return NULL; 209 210 for (n = 0; n < __arraycount(acpipchb_quirks); n++) { 211 const struct acpipchb_quirk *q = &acpipchb_quirks[n]; 212 if (memcmp(q->q_oemid, mcfg->Header.OemId, ACPI_OEM_ID_SIZE) == 0 && 213 memcmp(q->q_oemtableid, mcfg->Header.OemTableId, ACPI_OEM_TABLE_ID_SIZE) == 0 && 214 q->q_oemrevision == mcfg->Header.OemRevision) 215 return q; 216 } 217 218 return NULL; 219 } 220 221 static int acpipchb_match(device_t, cfdata_t, void *); 222 static void acpipchb_attach(device_t, device_t, void *); 223 224 static void acpipchb_setup_ranges(struct acpipchb_softc *, struct pcibus_attach_args *); 225 226 CFATTACH_DECL_NEW(acpipchb, sizeof(struct acpipchb_softc), 227 acpipchb_match, acpipchb_attach, NULL, NULL); 228 229 static const char * const compatible[] = { 230 "PNP0A08", 231 NULL 232 }; 233 234 static int 235 acpipchb_match(device_t parent, cfdata_t cf, void *aux) 236 { 237 struct acpi_attach_args *aa = aux; 238 239 if (aa->aa_node->ad_type != ACPI_TYPE_DEVICE) 240 return 0; 241 242 return acpi_match_hid(aa->aa_node->ad_devinfo, compatible); 243 } 244 245 static void 246 acpipchb_attach(device_t parent, device_t self, void *aux) 247 { 248 struct acpipchb_softc * const sc = device_private(self); 249 struct acpi_attach_args *aa = aux; 250 struct pcibus_attach_args pba; 251 const struct acpipchb_quirk *q; 252 ACPI_INTEGER cca, seg; 253 254 sc->sc_dev = self; 255 sc->sc_memt = aa->aa_memt; 256 sc->sc_handle = aa->aa_node->ad_handle; 257 258 if (ACPI_FAILURE(acpi_eval_integer(sc->sc_handle, "_BBN", &sc->sc_bus))) 259 sc->sc_bus = 0; 260 261 if (ACPI_FAILURE(acpi_eval_integer(sc->sc_handle, "_SEG", &seg))) 262 seg = 0; 263 264 if (ACPI_FAILURE(acpi_eval_integer(sc->sc_handle, "_CCA", &cca))) 265 cca = 1; 266 267 aprint_naive("\n"); 268 aprint_normal(": PCI Express Host Bridge\n"); 269 270 sc->sc_dmat = *aa->aa_dmat; 271 if (cca == 0) 272 sc->sc_dmat._nranges = 0; 273 274 sc->sc_ap.ap_dev = self; 275 sc->sc_ap.ap_pc = *aa->aa_pc; 276 sc->sc_ap.ap_pc.pc_conf_v = &sc->sc_ap; 277 sc->sc_ap.ap_seg = seg; 278 sc->sc_ap.ap_handle = sc->sc_handle; 279 sc->sc_ap.ap_bus = sc->sc_bus; 280 sc->sc_ap.ap_bst = sc->sc_memt; 281 282 q = acpipchb_find_quirk(); 283 if (q != NULL) 284 q->q_init(&sc->sc_ap); 285 286 if (acpi_pci_ignore_boot_config(sc->sc_handle)) { 287 if (acpimcfg_configure_bus(self, &sc->sc_ap.ap_pc, sc->sc_handle, sc->sc_bus, PCIHOST_CACHELINE_SIZE) != 0) 288 aprint_error_dev(self, "failed to configure bus\n"); 289 } 290 291 memset(&pba, 0, sizeof(pba)); 292 pba.pba_flags = aa->aa_pciflags & ~(PCI_FLAGS_MEM_OKAY | PCI_FLAGS_IO_OKAY); 293 pba.pba_memt = 0; 294 pba.pba_iot = 0; 295 pba.pba_dmat = &sc->sc_dmat; 296 #ifdef _PCI_HAVE_DMA64 297 pba.pba_dmat64 = &sc->sc_dmat; 298 #endif 299 pba.pba_pc = &sc->sc_ap.ap_pc; 300 pba.pba_bus = sc->sc_bus; 301 302 acpipchb_setup_ranges(sc, &pba); 303 304 config_found_ia(self, "pcibus", &pba, pcibusprint); 305 } 306 307 struct acpipchb_setup_ranges_args { 308 struct acpipchb_softc *sc; 309 struct pcibus_attach_args *pba; 310 }; 311 312 static int 313 acpipchb_bus_space_map(void *t, bus_addr_t bpa, bus_size_t size, int flag, 314 bus_space_handle_t *bshp) 315 { 316 struct acpipchb_bus_space * const abs = t; 317 int i; 318 319 if (size == 0) 320 return ERANGE; 321 322 for (i = 0; i < abs->nrange; i++) { 323 struct acpipchb_bus_range * const range = &abs->range[i]; 324 if (bpa >= range->min && bpa + size - 1 <= range->max) 325 return abs->map(t, bpa + range->offset, size, flag, bshp); 326 } 327 328 return ERANGE; 329 } 330 331 static ACPI_STATUS 332 acpipchb_setup_ranges_cb(ACPI_RESOURCE *res, void *ctx) 333 { 334 struct acpipchb_setup_ranges_args * const args = ctx; 335 struct acpipchb_softc * const sc = args->sc; 336 struct pcibus_attach_args *pba = args->pba; 337 struct acpipchb_bus_space *abs; 338 struct acpipchb_bus_range *range; 339 const char *range_type; 340 u_int pci_flags; 341 342 if (res->Type != ACPI_RESOURCE_TYPE_ADDRESS32 && 343 res->Type != ACPI_RESOURCE_TYPE_ADDRESS64) 344 return AE_OK; 345 346 switch (res->Data.Address.ResourceType) { 347 case ACPI_IO_RANGE: 348 abs = &sc->sc_pciio_bst; 349 range_type = "I/O"; 350 pci_flags = PCI_FLAGS_IO_OKAY; 351 break; 352 case ACPI_MEMORY_RANGE: 353 abs = &sc->sc_pcimem_bst; 354 range_type = "MEM"; 355 pci_flags = PCI_FLAGS_MEM_OKAY; 356 break; 357 default: 358 return AE_OK; 359 } 360 361 if (abs->nrange == ACPIPCHB_MAX_RANGES) { 362 aprint_error_dev(sc->sc_dev, 363 "maximum number of ranges reached, increase ACPIPCHB_MAX_RANGES\n"); 364 return AE_LIMIT; 365 } 366 367 range = &abs->range[abs->nrange]; 368 switch (res->Type) { 369 case ACPI_RESOURCE_TYPE_ADDRESS32: 370 range->min = res->Data.Address32.Address.Minimum; 371 range->max = res->Data.Address32.Address.Maximum; 372 range->offset = res->Data.Address32.Address.TranslationOffset; 373 break; 374 case ACPI_RESOURCE_TYPE_ADDRESS64: 375 range->min = res->Data.Address64.Address.Minimum; 376 range->max = res->Data.Address64.Address.Maximum; 377 range->offset = res->Data.Address64.Address.TranslationOffset; 378 break; 379 default: 380 return AE_OK; 381 } 382 abs->nrange++; 383 384 aprint_debug_dev(sc->sc_dev, "PCI %s [%#lx-%#lx] -> %#lx\n", range_type, range->min, range->max, range->offset); 385 386 if ((pba->pba_flags & pci_flags) == 0) { 387 abs->bs = *sc->sc_memt; 388 abs->bs.bs_cookie = abs; 389 abs->map = abs->bs.bs_map; 390 abs->bs.bs_map = acpipchb_bus_space_map; 391 if ((pci_flags & PCI_FLAGS_IO_OKAY) != 0) 392 pba->pba_iot = &abs->bs; 393 else if ((pci_flags & PCI_FLAGS_MEM_OKAY) != 0) 394 pba->pba_memt = &abs->bs; 395 pba->pba_flags |= pci_flags; 396 } 397 398 return AE_OK; 399 } 400 401 static void 402 acpipchb_setup_ranges(struct acpipchb_softc *sc, struct pcibus_attach_args *pba) 403 { 404 struct acpipchb_setup_ranges_args args; 405 406 args.sc = sc; 407 args.pba = pba; 408 409 AcpiWalkResources(sc->sc_handle, "_CRS", acpipchb_setup_ranges_cb, &args); 410 } 411
Indexes created Fri Sep 26 08:10:20 GMT 2025