acpipchb.c revision 1.27
1 /* $NetBSD: acpipchb.c,v 1.27 2021/08/07 21:27:53 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jared McNeill <jmcneill (at) invisible.ca>. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: acpipchb.c,v 1.27 2021/08/07 21:27:53 jmcneill Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/device.h> 38 #include <sys/intr.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/queue.h> 42 #include <sys/mutex.h> 43 #include <sys/kmem.h> 44 #include <sys/cpu.h> 45 46 #include <arm/cpufunc.h> 47 48 #include <dev/pci/pcireg.h> 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pciconf.h> 51 52 #include <dev/acpi/acpivar.h> 53 #include <dev/acpi/acpi_pci.h> 54 #include <dev/acpi/acpi_mcfg.h> 55 56 #include <arm/acpi/acpi_pci_machdep.h> 57 58 #define PCIHOST_CACHELINE_SIZE arm_dcache_align 59 60 #define ACPIPCHB_MAX_RANGES 64 /* XXX arbitrary limit */ 61 62 struct acpipchb_bus_range { 63 bus_addr_t min; 64 bus_addr_t max; 65 bus_addr_t offset; 66 }; 67 68 struct acpipchb_bus_space { 69 struct bus_space bs; 70 71 struct acpipchb_bus_range range[ACPIPCHB_MAX_RANGES]; 72 int nrange; 73 74 int (*map)(void *, bus_addr_t, bus_size_t, 75 int, bus_space_handle_t *); 76 77 int flags; 78 }; 79 80 struct acpipchb_softc { 81 device_t sc_dev; 82 83 bus_space_tag_t sc_memt; 84 85 ACPI_HANDLE sc_handle; 86 ACPI_INTEGER sc_bus; 87 88 struct acpipchb_bus_space sc_pcimem_bst; 89 struct acpipchb_bus_space sc_pciio_bst; 90 }; 91 92 static int acpipchb_match(device_t, cfdata_t, void *); 93 static void acpipchb_attach(device_t, device_t, void *); 94 95 static void acpipchb_configure_bus(struct acpipchb_softc *, struct pcibus_attach_args *); 96 static void acpipchb_setup_ranges(struct acpipchb_softc *, 97 struct pcibus_attach_args *); 98 static void acpipchb_setup_quirks(struct acpipchb_softc *, 99 struct pcibus_attach_args *); 100 101 CFATTACH_DECL_NEW(acpipchb, sizeof(struct acpipchb_softc), 102 acpipchb_match, acpipchb_attach, NULL, NULL); 103 104 static const char * const compatible[] = { 105 "PNP0A08", 106 NULL 107 }; 108 109 static int 110 acpipchb_match(device_t parent, cfdata_t cf, void *aux) 111 { 112 struct acpi_attach_args *aa = aux; 113 114 if (aa->aa_node->ad_type != ACPI_TYPE_DEVICE) 115 return 0; 116 117 return acpi_match_hid(aa->aa_node->ad_devinfo, compatible); 118 } 119 120 static void 121 acpipchb_attach(device_t parent, device_t self, void *aux) 122 { 123 struct acpipchb_softc * const sc = device_private(self); 124 struct acpi_attach_args *aa = aux; 125 struct pcibus_attach_args pba; 126 ACPI_INTEGER seg; 127 ACPI_STATUS rv; 128 uint16_t bus_start; 129 130 sc->sc_dev = self; 131 sc->sc_memt = aa->aa_memt; 132 sc->sc_handle = aa->aa_node->ad_handle; 133 134 /* 135 * First try to derive the base bus number from _CRS. If that fails, 136 * try _BBN. If that fails too, assume bus 0. 137 */ 138 if (ACPI_SUCCESS(acpi_pcidev_pciroot_bus(sc->sc_handle, &bus_start))) { 139 sc->sc_bus = bus_start; 140 } else { 141 rv = acpi_eval_integer(sc->sc_handle, "_BBN", &sc->sc_bus); 142 if (ACPI_FAILURE(rv)) { 143 sc->sc_bus = 0; 144 } 145 } 146 147 if (ACPI_FAILURE(acpi_eval_integer(sc->sc_handle, "_SEG", &seg))) { 148 seg = 0; 149 } 150 151 aprint_naive("\n"); 152 aprint_normal(": PCI Express Host Bridge\n"); 153 154 acpi_claim_childdevs(self, aa->aa_node); 155 156 memset(&pba, 0, sizeof(pba)); 157 pba.pba_flags = aa->aa_pciflags & 158 ~(PCI_FLAGS_MEM_OKAY | PCI_FLAGS_IO_OKAY); 159 pba.pba_memt = 0; 160 pba.pba_iot = 0; 161 pba.pba_dmat = aa->aa_dmat; 162 #ifdef _PCI_HAVE_DMA64 163 pba.pba_dmat64 = aa->aa_dmat64; 164 #endif 165 pba.pba_pc = aa->aa_pc; 166 pba.pba_bus = sc->sc_bus; 167 168 acpipchb_setup_ranges(sc, &pba); 169 acpipchb_setup_quirks(sc, &pba); 170 171 acpipchb_configure_bus(sc, &pba); 172 173 config_found(self, &pba, pcibusprint, 174 CFARGS(.devhandle = device_handle(self))); 175 } 176 177 static void 178 acpipchb_configure_bus(struct acpipchb_softc *sc, struct pcibus_attach_args *pba) 179 { 180 struct arm32_pci_chipset *md_pc = 181 (struct arm32_pci_chipset *)pba->pba_pc; 182 struct acpi_pci_context *ap = md_pc->pc_conf_v; 183 struct pciconf_resources *pcires; 184 ACPI_STATUS rv; 185 int error; 186 187 if (!acpi_pci_ignore_boot_config(sc->sc_handle)) { 188 return; 189 } 190 191 if ((ap->ap_flags & ACPI_PCI_FLAG_NO_MCFG) != 0) { 192 pcires = pciconf_resource_init(); 193 rv = AcpiWalkResources(sc->sc_handle, "_CRS", 194 acpimcfg_configure_bus_cb, pcires); 195 if (ACPI_FAILURE(rv)) { 196 error = ENXIO; 197 } else { 198 error = pci_configure_bus(pba->pba_pc, pcires, ap->ap_bus, 199 PCIHOST_CACHELINE_SIZE); 200 } 201 pciconf_resource_fini(pcires); 202 } else { 203 error = acpimcfg_configure_bus(sc->sc_dev, pba->pba_pc, sc->sc_handle, 204 sc->sc_bus, PCIHOST_CACHELINE_SIZE); 205 } 206 207 if (error != 0) { 208 aprint_error_dev(sc->sc_dev, "failed to configure bus, error %d\n", 209 error); 210 } 211 } 212 213 struct acpipchb_setup_ranges_args { 214 struct acpipchb_softc *sc; 215 struct pcibus_attach_args *pba; 216 }; 217 218 static int 219 acpipchb_bus_space_map(void *t, bus_addr_t bpa, bus_size_t size, int flag, 220 bus_space_handle_t *bshp) 221 { 222 struct acpipchb_bus_space * const abs = t; 223 int i; 224 225 if (size == 0) 226 return ERANGE; 227 228 if ((abs->flags & PCI_FLAGS_IO_OKAY) != 0) { 229 /* Force strongly ordered mapping for all I/O space */ 230 flag = _ARM_BUS_SPACE_MAP_STRONGLY_ORDERED; 231 } 232 233 for (i = 0; i < abs->nrange; i++) { 234 struct acpipchb_bus_range * const range = &abs->range[i]; 235 if (bpa >= range->min && bpa + size - 1 <= range->max) { 236 return abs->map(t, bpa + range->offset, size, 237 flag, bshp); 238 } 239 } 240 241 return ERANGE; 242 } 243 244 static ACPI_STATUS 245 acpipchb_setup_ranges_cb(ACPI_RESOURCE *res, void *ctx) 246 { 247 struct acpipchb_setup_ranges_args * const args = ctx; 248 struct acpipchb_softc * const sc = args->sc; 249 struct pcibus_attach_args *pba = args->pba; 250 struct acpipchb_bus_space *abs; 251 struct acpipchb_bus_range *range; 252 const char *range_type; 253 u_int pci_flags; 254 255 if (res->Type != ACPI_RESOURCE_TYPE_ADDRESS32 && 256 res->Type != ACPI_RESOURCE_TYPE_ADDRESS64) { 257 return AE_OK; 258 } 259 260 switch (res->Data.Address.ResourceType) { 261 case ACPI_IO_RANGE: 262 abs = &sc->sc_pciio_bst; 263 range_type = "I/O"; 264 pci_flags = PCI_FLAGS_IO_OKAY; 265 break; 266 case ACPI_MEMORY_RANGE: 267 abs = &sc->sc_pcimem_bst; 268 range_type = "MEM"; 269 pci_flags = PCI_FLAGS_MEM_OKAY; 270 break; 271 default: 272 return AE_OK; 273 } 274 275 if (abs->nrange == ACPIPCHB_MAX_RANGES) { 276 aprint_error_dev(sc->sc_dev, 277 "maximum number of ranges reached (ACPIPCHB_MAX_RANGES)\n"); 278 return AE_LIMIT; 279 } 280 281 range = &abs->range[abs->nrange]; 282 switch (res->Type) { 283 case ACPI_RESOURCE_TYPE_ADDRESS32: 284 range->min = res->Data.Address32.Address.Minimum; 285 range->max = res->Data.Address32.Address.Maximum; 286 range->offset = res->Data.Address32.Address.TranslationOffset; 287 break; 288 case ACPI_RESOURCE_TYPE_ADDRESS64: 289 range->min = res->Data.Address64.Address.Minimum; 290 range->max = res->Data.Address64.Address.Maximum; 291 range->offset = res->Data.Address64.Address.TranslationOffset; 292 break; 293 default: 294 return AE_OK; 295 } 296 abs->nrange++; 297 298 aprint_debug_dev(sc->sc_dev, "PCI %s [%#lx-%#lx] -> %#lx\n", 299 range_type, range->min, range->max, range->offset); 300 301 if ((pba->pba_flags & pci_flags) == 0) { 302 abs->bs = *sc->sc_memt; 303 abs->bs.bs_cookie = abs; 304 abs->map = abs->bs.bs_map; 305 abs->flags = pci_flags; 306 abs->bs.bs_map = acpipchb_bus_space_map; 307 if ((pci_flags & PCI_FLAGS_IO_OKAY) != 0) { 308 pba->pba_iot = &abs->bs; 309 } else if ((pci_flags & PCI_FLAGS_MEM_OKAY) != 0) { 310 pba->pba_memt = &abs->bs; 311 } 312 pba->pba_flags |= pci_flags; 313 } 314 315 return AE_OK; 316 } 317 318 static void 319 acpipchb_setup_ranges(struct acpipchb_softc *sc, struct pcibus_attach_args *pba) 320 { 321 struct acpipchb_setup_ranges_args args; 322 323 args.sc = sc; 324 args.pba = pba; 325 326 AcpiWalkResources(sc->sc_handle, "_CRS", acpipchb_setup_ranges_cb, 327 &args); 328 } 329 330 static void 331 acpipchb_setup_quirks(struct acpipchb_softc *sc, struct pcibus_attach_args *pba) 332 { 333 struct arm32_pci_chipset *md_pc = 334 (struct arm32_pci_chipset *)pba->pba_pc; 335 struct acpi_pci_context *ap = md_pc->pc_conf_v; 336 337 pba->pba_flags &= ~ap->ap_pciflags_clear; 338 } 339
Indexes created Mon Sep 22 10:09:38 GMT 2025