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acpipchb.c revision 1.29 
      1 /* $NetBSD: acpipchb.c,v 1.29 2022/08/13 16:44:11 jmcneill Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2018 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Jared McNeill <jmcneill (at) invisible.ca>.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  * POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 #include <sys/cdefs.h>
     33 __KERNEL_RCSID(0, "$NetBSD: acpipchb.c,v 1.29 2022/08/13 16:44:11 jmcneill Exp $");
     34 
     35 #include <sys/param.h>
     36 #include <sys/bus.h>
     37 #include <sys/device.h>
     38 #include <sys/intr.h>
     39 #include <sys/systm.h>
     40 #include <sys/kernel.h>
     41 #include <sys/queue.h>
     42 #include <sys/mutex.h>
     43 #include <sys/kmem.h>
     44 #include <sys/cpu.h>
     45 
     46 #include <arm/cpufunc.h>
     47 #include <arm/bootconfig.h>
     48 
     49 #include <dev/pci/pcireg.h>
     50 #include <dev/pci/pcivar.h>
     51 #include <dev/pci/pciconf.h>
     52 
     53 #include <dev/acpi/acpivar.h>
     54 #include <dev/acpi/acpi_pci.h>
     55 #include <dev/acpi/acpi_mcfg.h>
     56 
     57 #include <arm/acpi/acpi_pci_machdep.h>
     58 
     59 #define	PCIHOST_CACHELINE_SIZE		arm_dcache_align
     60 
     61 #define	ACPIPCHB_MAX_RANGES	64	/* XXX arbitrary limit */
     62 
     63 struct acpipchb_bus_range {
     64 	bus_addr_t		min;
     65 	bus_addr_t		max;
     66 	bus_addr_t		offset;
     67 };
     68 
     69 struct acpipchb_bus_space {
     70 	struct bus_space	bs;
     71 
     72 	struct acpipchb_bus_range range[ACPIPCHB_MAX_RANGES];
     73 	int			nrange;
     74 
     75 	int			(*map)(void *, bus_addr_t, bus_size_t,
     76 				       int, bus_space_handle_t *);
     77 
     78 	int			flags;
     79 };
     80 
     81 struct acpipchb_softc {
     82 	device_t		sc_dev;
     83 
     84 	bus_space_tag_t		sc_memt;
     85 
     86 	ACPI_HANDLE		sc_handle;
     87 	ACPI_INTEGER		sc_bus;
     88 
     89 	struct acpipchb_bus_space sc_pcimem_bst;
     90 	struct acpipchb_bus_space sc_pciio_bst;
     91 };
     92 
     93 static int	acpipchb_match(device_t, cfdata_t, void *);
     94 static void	acpipchb_attach(device_t, device_t, void *);
     95 
     96 static void	acpipchb_configure_bus(struct acpipchb_softc *, struct pcibus_attach_args *);
     97 static void	acpipchb_setup_ranges(struct acpipchb_softc *,
     98 				      struct pcibus_attach_args *);
     99 static void	acpipchb_setup_quirks(struct acpipchb_softc *,
    100 				      struct pcibus_attach_args *);
    101 
    102 CFATTACH_DECL_NEW(acpipchb, sizeof(struct acpipchb_softc),
    103 	acpipchb_match, acpipchb_attach, NULL, NULL);
    104 
    105 static const char * const compatible[] = {
    106 	"PNP0A08",
    107 	NULL
    108 };
    109 
    110 static int
    111 acpipchb_match(device_t parent, cfdata_t cf, void *aux)
    112 {
    113 	struct acpi_attach_args *aa = aux;
    114 
    115 	if (aa->aa_node->ad_type != ACPI_TYPE_DEVICE)
    116 		return 0;
    117 
    118 	return acpi_match_hid(aa->aa_node->ad_devinfo, compatible);
    119 }
    120 
    121 static void
    122 acpipchb_attach(device_t parent, device_t self, void *aux)
    123 {
    124 	struct acpipchb_softc * const sc = device_private(self);
    125 	struct acpi_attach_args *aa = aux;
    126 	struct pcibus_attach_args pba;
    127 	ACPI_INTEGER seg, nomsi;
    128 	ACPI_STATUS rv;
    129 	uint16_t bus_start;
    130 
    131 	sc->sc_dev = self;
    132 	sc->sc_memt = aa->aa_memt;
    133 	sc->sc_handle = aa->aa_node->ad_handle;
    134 
    135 	/*
    136 	 * First try to derive the base bus number from _CRS. If that fails,
    137 	 * try _BBN. If that fails too, assume bus 0.
    138 	 */
    139 	if (ACPI_SUCCESS(acpi_pcidev_pciroot_bus(sc->sc_handle, &bus_start))) {
    140 		sc->sc_bus = bus_start;
    141 	} else {
    142 		rv = acpi_eval_integer(sc->sc_handle, "_BBN", &sc->sc_bus);
    143 		if (ACPI_FAILURE(rv)) {
    144 			sc->sc_bus = 0;
    145 		}
    146 	}
    147 
    148 	if (ACPI_FAILURE(acpi_eval_integer(sc->sc_handle, "_SEG", &seg))) {
    149 		seg = 0;
    150 	}
    151 
    152 	if (ACPI_FAILURE(acpi_dsd_integer(sc->sc_handle, "linux,pcie-nomsi",
    153 	    &nomsi))) {
    154 		nomsi = 0;
    155 	}
    156 
    157 	aprint_naive("\n");
    158 	aprint_normal(": PCI Express Host Bridge\n");
    159 
    160 	acpi_claim_childdevs(self, aa->aa_node);
    161 
    162 	memset(&pba, 0, sizeof(pba));
    163 	pba.pba_flags = aa->aa_pciflags &
    164 			~(PCI_FLAGS_MEM_OKAY | PCI_FLAGS_IO_OKAY);
    165 	if (nomsi) {
    166 		pba.pba_flags &= ~(PCI_FLAGS_MSI_OKAY | PCI_FLAGS_MSIX_OKAY);
    167 	}
    168 	pba.pba_memt = 0;
    169 	pba.pba_iot = 0;
    170 	pba.pba_dmat = aa->aa_dmat;
    171 #ifdef _PCI_HAVE_DMA64
    172 	pba.pba_dmat64 = aa->aa_dmat64;
    173 #endif
    174 	pba.pba_pc = aa->aa_pc;
    175 	pba.pba_bus = sc->sc_bus;
    176 
    177 	acpipchb_setup_ranges(sc, &pba);
    178 	acpipchb_setup_quirks(sc, &pba);
    179 
    180 	acpipchb_configure_bus(sc, &pba);
    181 
    182 	config_found(self, &pba, pcibusprint,
    183 	    CFARGS(.devhandle = device_handle(self)));
    184 }
    185 
    186 static void
    187 acpipchb_configure_bus(struct acpipchb_softc *sc, struct pcibus_attach_args *pba)
    188 {
    189 	struct arm32_pci_chipset *md_pc =
    190 	    (struct arm32_pci_chipset *)pba->pba_pc;
    191 	struct acpi_pci_context *ap = md_pc->pc_conf_v;
    192 	struct pciconf_resources *pcires;
    193 	ACPI_STATUS rv;
    194 	int error, val;
    195 
    196 	if (!acpi_pci_ignore_boot_config(sc->sc_handle)) {
    197 		return;
    198 	}
    199 	if (get_bootconf_option(boot_args, "nopciconf",
    200 				BOOTOPT_TYPE_BOOLEAN, &val) && val) {
    201 		return;
    202 	}
    203 
    204 	if ((ap->ap_flags & ACPI_PCI_FLAG_NO_MCFG) != 0) {
    205 		pcires = pciconf_resource_init();
    206 		rv = AcpiWalkResources(sc->sc_handle, "_CRS",
    207 		    acpimcfg_configure_bus_cb, pcires);
    208 		if (ACPI_FAILURE(rv)) {
    209 			error = ENXIO;
    210 		} else {
    211 			error = pci_configure_bus(pba->pba_pc, pcires, ap->ap_bus,
    212 			    PCIHOST_CACHELINE_SIZE);
    213 		}
    214 		pciconf_resource_fini(pcires);
    215 	} else {
    216 		error = acpimcfg_configure_bus(sc->sc_dev, pba->pba_pc, sc->sc_handle,
    217 		    sc->sc_bus, PCIHOST_CACHELINE_SIZE);
    218 	}
    219 
    220 	if (error != 0) {
    221 		aprint_error_dev(sc->sc_dev, "failed to configure bus, error %d\n",
    222 		    error);
    223 	}
    224 }
    225 
    226 struct acpipchb_setup_ranges_args {
    227 	struct acpipchb_softc *sc;
    228 	struct pcibus_attach_args *pba;
    229 };
    230 
    231 static int
    232 acpipchb_bus_space_map(void *t, bus_addr_t bpa, bus_size_t size, int flag,
    233     bus_space_handle_t *bshp)
    234 {
    235 	struct acpipchb_bus_space * const abs = t;
    236 	int i;
    237 
    238 	if (size == 0)
    239 		return ERANGE;
    240 
    241 	if ((abs->flags & PCI_FLAGS_IO_OKAY) != 0) {
    242 		/* Force strongly ordered mapping for all I/O space */
    243 		flag = _ARM_BUS_SPACE_MAP_STRONGLY_ORDERED;
    244 	}
    245 
    246 	for (i = 0; i < abs->nrange; i++) {
    247 		struct acpipchb_bus_range * const range = &abs->range[i];
    248 		if (bpa >= range->min && bpa + size - 1 <= range->max) {
    249 			return abs->map(t, bpa + range->offset, size,
    250 					flag, bshp);
    251 		}
    252 	}
    253 
    254 	return ERANGE;
    255 }
    256 
    257 static ACPI_STATUS
    258 acpipchb_setup_ranges_cb(ACPI_RESOURCE *res, void *ctx)
    259 {
    260 	struct acpipchb_setup_ranges_args * const args = ctx;
    261 	struct acpipchb_softc * const sc = args->sc;
    262 	struct pcibus_attach_args *pba = args->pba;
    263 	struct acpipchb_bus_space *abs;
    264 	struct acpipchb_bus_range *range;
    265 	const char *range_type;
    266 	u_int pci_flags;
    267 
    268 	if (res->Type != ACPI_RESOURCE_TYPE_ADDRESS32 &&
    269 	    res->Type != ACPI_RESOURCE_TYPE_ADDRESS64) {
    270 		return AE_OK;
    271 	}
    272 
    273 	switch (res->Data.Address.ResourceType) {
    274 	case ACPI_IO_RANGE:
    275 		abs = &sc->sc_pciio_bst;
    276 		range_type = "I/O";
    277 		pci_flags = PCI_FLAGS_IO_OKAY;
    278 		break;
    279 	case ACPI_MEMORY_RANGE:
    280 		abs = &sc->sc_pcimem_bst;
    281 		range_type = "MEM";
    282 		pci_flags = PCI_FLAGS_MEM_OKAY;
    283 		break;
    284 	default:
    285 		return AE_OK;
    286 	}
    287 
    288 	if (abs->nrange == ACPIPCHB_MAX_RANGES) {
    289 		aprint_error_dev(sc->sc_dev,
    290 		    "maximum number of ranges reached (ACPIPCHB_MAX_RANGES)\n");
    291 		return AE_LIMIT;
    292 	}
    293 
    294 	range = &abs->range[abs->nrange];
    295 	switch (res->Type) {
    296 	case ACPI_RESOURCE_TYPE_ADDRESS32:
    297 		range->min = res->Data.Address32.Address.Minimum;
    298 		range->max = res->Data.Address32.Address.Maximum;
    299 		range->offset = res->Data.Address32.Address.TranslationOffset;
    300 		break;
    301 	case ACPI_RESOURCE_TYPE_ADDRESS64:
    302 		range->min = res->Data.Address64.Address.Minimum;
    303 		range->max = res->Data.Address64.Address.Maximum;
    304 		range->offset = res->Data.Address64.Address.TranslationOffset;
    305 		break;
    306 	default:
    307 		return AE_OK;
    308 	}
    309 	abs->nrange++;
    310 
    311 	aprint_debug_dev(sc->sc_dev, "PCI %s [%#lx-%#lx] -> %#lx\n",
    312 	    range_type, range->min, range->max, range->offset);
    313 
    314 	if ((pba->pba_flags & pci_flags) == 0) {
    315 		abs->bs = *sc->sc_memt;
    316 		abs->bs.bs_cookie = abs;
    317 		abs->map = abs->bs.bs_map;
    318 		abs->flags = pci_flags;
    319 		abs->bs.bs_map = acpipchb_bus_space_map;
    320 		if ((pci_flags & PCI_FLAGS_IO_OKAY) != 0) {
    321 			pba->pba_iot = &abs->bs;
    322 		} else if ((pci_flags & PCI_FLAGS_MEM_OKAY) != 0) {
    323 			pba->pba_memt = &abs->bs;
    324 		}
    325 		pba->pba_flags |= pci_flags;
    326 	}
    327 
    328 	return AE_OK;
    329 }
    330 
    331 static void
    332 acpipchb_setup_ranges(struct acpipchb_softc *sc, struct pcibus_attach_args *pba)
    333 {
    334 	struct acpipchb_setup_ranges_args args;
    335 
    336 	args.sc = sc;
    337 	args.pba = pba;
    338 
    339 	AcpiWalkResources(sc->sc_handle, "_CRS", acpipchb_setup_ranges_cb,
    340 	    &args);
    341 }
    342 
    343 static void
    344 acpipchb_setup_quirks(struct acpipchb_softc *sc, struct pcibus_attach_args *pba)
    345 {
    346 	struct arm32_pci_chipset *md_pc =
    347 	    (struct arm32_pci_chipset *)pba->pba_pc;
    348 	struct acpi_pci_context *ap = md_pc->pc_conf_v;
    349 
    350 	pba->pba_flags &= ~ap->ap_pciflags_clear;
    351 }
    352