acpipchb.c revision 1.30
1 /* $NetBSD: acpipchb.c,v 1.30 2022/08/13 20:08:36 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jared McNeill <jmcneill (at) invisible.ca>. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: acpipchb.c,v 1.30 2022/08/13 20:08:36 jmcneill Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/device.h> 38 #include <sys/intr.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/queue.h> 42 #include <sys/mutex.h> 43 #include <sys/kmem.h> 44 #include <sys/cpu.h> 45 46 #include <arm/cpufunc.h> 47 #include <arm/bootconfig.h> 48 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pciconf.h> 52 53 #include <dev/acpi/acpivar.h> 54 #include <dev/acpi/acpi_pci.h> 55 #include <dev/acpi/acpi_mcfg.h> 56 57 #include <arm/acpi/acpi_pci_machdep.h> 58 59 #define PCIHOST_CACHELINE_SIZE arm_dcache_align 60 61 #define ACPIPCHB_MAX_RANGES 64 /* XXX arbitrary limit */ 62 63 struct acpipchb_bus_range { 64 bus_addr_t min; 65 bus_addr_t max; 66 bus_addr_t offset; 67 }; 68 69 struct acpipchb_bus_space { 70 struct bus_space bs; 71 72 struct acpipchb_bus_range range[ACPIPCHB_MAX_RANGES]; 73 int nrange; 74 75 int (*map)(void *, bus_addr_t, bus_size_t, 76 int, bus_space_handle_t *); 77 78 int flags; 79 }; 80 81 struct acpipchb_softc { 82 device_t sc_dev; 83 84 bus_space_tag_t sc_memt; 85 86 ACPI_HANDLE sc_handle; 87 ACPI_INTEGER sc_bus; 88 89 struct acpipchb_bus_space sc_pcimem_bst; 90 struct acpipchb_bus_space sc_pciio_bst; 91 }; 92 93 static int acpipchb_match(device_t, cfdata_t, void *); 94 static void acpipchb_attach(device_t, device_t, void *); 95 96 static void acpipchb_configure_bus(struct acpipchb_softc *, struct pcibus_attach_args *); 97 static void acpipchb_setup_ranges(struct acpipchb_softc *, 98 struct pcibus_attach_args *); 99 static void acpipchb_setup_quirks(struct acpipchb_softc *, 100 struct pcibus_attach_args *); 101 102 CFATTACH_DECL_NEW(acpipchb, sizeof(struct acpipchb_softc), 103 acpipchb_match, acpipchb_attach, NULL, NULL); 104 105 static const char * const compatible[] = { 106 "PNP0A08", 107 NULL 108 }; 109 110 static int 111 acpipchb_match(device_t parent, cfdata_t cf, void *aux) 112 { 113 struct acpi_attach_args *aa = aux; 114 115 if (aa->aa_node->ad_type != ACPI_TYPE_DEVICE) 116 return 0; 117 118 return acpi_match_hid(aa->aa_node->ad_devinfo, compatible); 119 } 120 121 static void 122 acpipchb_attach(device_t parent, device_t self, void *aux) 123 { 124 struct acpipchb_softc * const sc = device_private(self); 125 struct acpi_attach_args *aa = aux; 126 struct pcibus_attach_args pba; 127 ACPI_INTEGER seg, nomsi; 128 ACPI_STATUS rv; 129 uint16_t bus_start; 130 int val; 131 132 sc->sc_dev = self; 133 sc->sc_memt = aa->aa_memt; 134 sc->sc_handle = aa->aa_node->ad_handle; 135 136 /* 137 * First try to derive the base bus number from _CRS. If that fails, 138 * try _BBN. If that fails too, assume bus 0. 139 */ 140 if (ACPI_SUCCESS(acpi_pcidev_pciroot_bus(sc->sc_handle, &bus_start))) { 141 sc->sc_bus = bus_start; 142 } else { 143 rv = acpi_eval_integer(sc->sc_handle, "_BBN", &sc->sc_bus); 144 if (ACPI_FAILURE(rv)) { 145 sc->sc_bus = 0; 146 } 147 } 148 149 if (ACPI_FAILURE(acpi_eval_integer(sc->sc_handle, "_SEG", &seg))) { 150 seg = 0; 151 } 152 153 if (ACPI_FAILURE(acpi_dsd_integer(sc->sc_handle, "linux,pcie-nomsi", 154 &nomsi))) { 155 nomsi = 0; 156 } 157 if (get_bootconf_option(boot_args, "nopcimsi", 158 BOOTOPT_TYPE_BOOLEAN, &val) && val) { 159 nomsi = 1; 160 } 161 162 aprint_naive("\n"); 163 aprint_normal(": PCI Express Host Bridge\n"); 164 165 acpi_claim_childdevs(self, aa->aa_node); 166 167 memset(&pba, 0, sizeof(pba)); 168 pba.pba_flags = aa->aa_pciflags & 169 ~(PCI_FLAGS_MEM_OKAY | PCI_FLAGS_IO_OKAY); 170 if (nomsi) { 171 pba.pba_flags &= ~(PCI_FLAGS_MSI_OKAY | PCI_FLAGS_MSIX_OKAY); 172 } 173 pba.pba_memt = 0; 174 pba.pba_iot = 0; 175 pba.pba_dmat = aa->aa_dmat; 176 #ifdef _PCI_HAVE_DMA64 177 pba.pba_dmat64 = aa->aa_dmat64; 178 #endif 179 pba.pba_pc = aa->aa_pc; 180 pba.pba_bus = sc->sc_bus; 181 182 acpipchb_setup_ranges(sc, &pba); 183 acpipchb_setup_quirks(sc, &pba); 184 185 acpipchb_configure_bus(sc, &pba); 186 187 config_found(self, &pba, pcibusprint, 188 CFARGS(.devhandle = device_handle(self))); 189 } 190 191 static void 192 acpipchb_configure_bus(struct acpipchb_softc *sc, struct pcibus_attach_args *pba) 193 { 194 struct arm32_pci_chipset *md_pc = 195 (struct arm32_pci_chipset *)pba->pba_pc; 196 struct acpi_pci_context *ap = md_pc->pc_conf_v; 197 struct pciconf_resources *pcires; 198 ACPI_STATUS rv; 199 int error, val; 200 201 if (!acpi_pci_ignore_boot_config(sc->sc_handle)) { 202 return; 203 } 204 if (get_bootconf_option(boot_args, "nopciconf", 205 BOOTOPT_TYPE_BOOLEAN, &val) && val) { 206 return; 207 } 208 209 if ((ap->ap_flags & ACPI_PCI_FLAG_NO_MCFG) != 0) { 210 pcires = pciconf_resource_init(); 211 rv = AcpiWalkResources(sc->sc_handle, "_CRS", 212 acpimcfg_configure_bus_cb, pcires); 213 if (ACPI_FAILURE(rv)) { 214 error = ENXIO; 215 } else { 216 error = pci_configure_bus(pba->pba_pc, pcires, ap->ap_bus, 217 PCIHOST_CACHELINE_SIZE); 218 } 219 pciconf_resource_fini(pcires); 220 } else { 221 error = acpimcfg_configure_bus(sc->sc_dev, pba->pba_pc, sc->sc_handle, 222 sc->sc_bus, PCIHOST_CACHELINE_SIZE); 223 } 224 225 if (error != 0) { 226 aprint_error_dev(sc->sc_dev, "failed to configure bus, error %d\n", 227 error); 228 } 229 } 230 231 struct acpipchb_setup_ranges_args { 232 struct acpipchb_softc *sc; 233 struct pcibus_attach_args *pba; 234 }; 235 236 static int 237 acpipchb_bus_space_map(void *t, bus_addr_t bpa, bus_size_t size, int flag, 238 bus_space_handle_t *bshp) 239 { 240 struct acpipchb_bus_space * const abs = t; 241 int i; 242 243 if (size == 0) 244 return ERANGE; 245 246 if ((abs->flags & PCI_FLAGS_IO_OKAY) != 0) { 247 /* Force strongly ordered mapping for all I/O space */ 248 flag = _ARM_BUS_SPACE_MAP_STRONGLY_ORDERED; 249 } 250 251 for (i = 0; i < abs->nrange; i++) { 252 struct acpipchb_bus_range * const range = &abs->range[i]; 253 if (bpa >= range->min && bpa + size - 1 <= range->max) { 254 return abs->map(t, bpa + range->offset, size, 255 flag, bshp); 256 } 257 } 258 259 return ERANGE; 260 } 261 262 static ACPI_STATUS 263 acpipchb_setup_ranges_cb(ACPI_RESOURCE *res, void *ctx) 264 { 265 struct acpipchb_setup_ranges_args * const args = ctx; 266 struct acpipchb_softc * const sc = args->sc; 267 struct pcibus_attach_args *pba = args->pba; 268 struct acpipchb_bus_space *abs; 269 struct acpipchb_bus_range *range; 270 const char *range_type; 271 u_int pci_flags; 272 273 if (res->Type != ACPI_RESOURCE_TYPE_ADDRESS32 && 274 res->Type != ACPI_RESOURCE_TYPE_ADDRESS64) { 275 return AE_OK; 276 } 277 278 switch (res->Data.Address.ResourceType) { 279 case ACPI_IO_RANGE: 280 abs = &sc->sc_pciio_bst; 281 range_type = "I/O"; 282 pci_flags = PCI_FLAGS_IO_OKAY; 283 break; 284 case ACPI_MEMORY_RANGE: 285 abs = &sc->sc_pcimem_bst; 286 range_type = "MEM"; 287 pci_flags = PCI_FLAGS_MEM_OKAY; 288 break; 289 default: 290 return AE_OK; 291 } 292 293 if (abs->nrange == ACPIPCHB_MAX_RANGES) { 294 aprint_error_dev(sc->sc_dev, 295 "maximum number of ranges reached (ACPIPCHB_MAX_RANGES)\n"); 296 return AE_LIMIT; 297 } 298 299 range = &abs->range[abs->nrange]; 300 switch (res->Type) { 301 case ACPI_RESOURCE_TYPE_ADDRESS32: 302 range->min = res->Data.Address32.Address.Minimum; 303 range->max = res->Data.Address32.Address.Maximum; 304 range->offset = res->Data.Address32.Address.TranslationOffset; 305 break; 306 case ACPI_RESOURCE_TYPE_ADDRESS64: 307 range->min = res->Data.Address64.Address.Minimum; 308 range->max = res->Data.Address64.Address.Maximum; 309 range->offset = res->Data.Address64.Address.TranslationOffset; 310 break; 311 default: 312 return AE_OK; 313 } 314 abs->nrange++; 315 316 aprint_debug_dev(sc->sc_dev, "PCI %s [%#lx-%#lx] -> %#lx\n", 317 range_type, range->min, range->max, range->offset); 318 319 if ((pba->pba_flags & pci_flags) == 0) { 320 abs->bs = *sc->sc_memt; 321 abs->bs.bs_cookie = abs; 322 abs->map = abs->bs.bs_map; 323 abs->flags = pci_flags; 324 abs->bs.bs_map = acpipchb_bus_space_map; 325 if ((pci_flags & PCI_FLAGS_IO_OKAY) != 0) { 326 pba->pba_iot = &abs->bs; 327 } else if ((pci_flags & PCI_FLAGS_MEM_OKAY) != 0) { 328 pba->pba_memt = &abs->bs; 329 } 330 pba->pba_flags |= pci_flags; 331 } 332 333 return AE_OK; 334 } 335 336 static void 337 acpipchb_setup_ranges(struct acpipchb_softc *sc, struct pcibus_attach_args *pba) 338 { 339 struct acpipchb_setup_ranges_args args; 340 341 args.sc = sc; 342 args.pba = pba; 343 344 AcpiWalkResources(sc->sc_handle, "_CRS", acpipchb_setup_ranges_cb, 345 &args); 346 } 347 348 static void 349 acpipchb_setup_quirks(struct acpipchb_softc *sc, struct pcibus_attach_args *pba) 350 { 351 struct arm32_pci_chipset *md_pc = 352 (struct arm32_pci_chipset *)pba->pba_pc; 353 struct acpi_pci_context *ap = md_pc->pc_conf_v; 354 355 pba->pba_flags &= ~ap->ap_pciflags_clear; 356 } 357
Indexes created Fri Sep 26 08:10:20 GMT 2025