acpipchb.c revision 1.5 1 /* $NetBSD: acpipchb.c,v 1.5 2018/11/16 15:41:27 jmcneill Exp $ */
2
3 /*-
4 * Copyright (c) 2018 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jared McNeill <jmcneill (at) invisible.ca>.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #include <sys/cdefs.h>
33 __KERNEL_RCSID(0, "$NetBSD: acpipchb.c,v 1.5 2018/11/16 15:41:27 jmcneill Exp $");
34
35 #include <sys/param.h>
36 #include <sys/bus.h>
37 #include <sys/device.h>
38 #include <sys/intr.h>
39 #include <sys/systm.h>
40 #include <sys/kernel.h>
41 #include <sys/extent.h>
42 #include <sys/queue.h>
43 #include <sys/mutex.h>
44 #include <sys/kmem.h>
45
46 #include <machine/cpu.h>
47
48 #include <arm/cpufunc.h>
49
50 #include <dev/pci/pcireg.h>
51 #include <dev/pci/pcivar.h>
52 #include <dev/pci/pciconf.h>
53
54 #include <dev/acpi/acpivar.h>
55 #include <dev/acpi/acpi_pci.h>
56 #include <dev/acpi/acpi_mcfg.h>
57
58 #include <arm/acpi/acpi_pci_machdep.h>
59
60 #define PCIHOST_CACHELINE_SIZE arm_dcache_align
61
62 struct acpipchb_softc {
63 device_t sc_dev;
64
65 struct arm32_bus_dma_tag sc_dmat;
66 struct acpi_pci_context sc_ap;
67
68 ACPI_HANDLE sc_handle;
69 ACPI_INTEGER sc_bus;
70 };
71
72 static struct arm32_dma_range ahcipchb_coherent_ranges[] = {
73 [0] = {
74 .dr_sysbase = 0,
75 .dr_busbase = 0,
76 .dr_len = UINTPTR_MAX,
77 .dr_flags = _BUS_DMAMAP_COHERENT,
78 }
79 };
80
81 static int acpipchb_match(device_t, cfdata_t, void *);
82 static void acpipchb_attach(device_t, device_t, void *);
83
84 CFATTACH_DECL_NEW(acpipchb, sizeof(struct acpipchb_softc),
85 acpipchb_match, acpipchb_attach, NULL, NULL);
86
87 static const char * const compatible[] = {
88 "PNP0A08",
89 NULL
90 };
91
92 static int
93 acpipchb_match(device_t parent, cfdata_t cf, void *aux)
94 {
95 struct acpi_attach_args *aa = aux;
96
97 if (aa->aa_node->ad_type != ACPI_TYPE_DEVICE)
98 return 0;
99
100 return acpi_match_hid(aa->aa_node->ad_devinfo, compatible);
101 }
102
103 static void
104 acpipchb_attach(device_t parent, device_t self, void *aux)
105 {
106 struct acpipchb_softc * const sc = device_private(self);
107 struct acpi_attach_args *aa = aux;
108 struct pcibus_attach_args pba;
109 ACPI_INTEGER cca, seg;
110
111 sc->sc_dev = self;
112 sc->sc_handle = aa->aa_node->ad_handle;
113
114 if (ACPI_FAILURE(acpi_eval_integer(sc->sc_handle, "_BBN", &sc->sc_bus)))
115 sc->sc_bus = 0;
116
117 if (ACPI_FAILURE(acpi_eval_integer(sc->sc_handle, "_SEG", &seg)))
118 seg = 0;
119
120 if (ACPI_FAILURE(acpi_eval_integer(sc->sc_handle, "_CCA", &cca)))
121 cca = 0;
122
123 aprint_naive("\n");
124 aprint_normal(": PCI Express Host Bridge\n");
125
126 sc->sc_dmat = *aa->aa_dmat;
127 if (cca) {
128 sc->sc_dmat._ranges = ahcipchb_coherent_ranges;
129 sc->sc_dmat._nranges = __arraycount(ahcipchb_coherent_ranges);
130 }
131
132 sc->sc_ap.ap_pc = *aa->aa_pc;
133 sc->sc_ap.ap_pc.pc_conf_v = &sc->sc_ap;
134 sc->sc_ap.ap_seg = seg;
135
136 if (acpi_pci_ignore_boot_config(sc->sc_handle)) {
137 if (acpimcfg_configure_bus(self, &sc->sc_ap.ap_pc, sc->sc_handle, sc->sc_bus, PCIHOST_CACHELINE_SIZE) != 0)
138 aprint_error_dev(self, "failed to configure bus\n");
139 }
140
141 memset(&pba, 0, sizeof(pba));
142 pba.pba_flags = aa->aa_pciflags;
143 pba.pba_iot = aa->aa_iot;
144 pba.pba_memt = aa->aa_memt;
145 pba.pba_dmat = &sc->sc_dmat;
146 #ifdef _PCI_HAVE_DMA64
147 pba.pba_dmat64 = &sc->sc_dmat;
148 #endif
149 pba.pba_pc = &sc->sc_ap.ap_pc;
150 pba.pba_bus = sc->sc_bus;
151
152 config_found_ia(self, "pcibus", &pba, pcibusprint);
153 }
154