acpipchb.c revision 1.6
1 /* $NetBSD: acpipchb.c,v 1.6 2018/11/18 20:22:20 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jared McNeill <jmcneill (at) invisible.ca>. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: acpipchb.c,v 1.6 2018/11/18 20:22:20 jmcneill Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/device.h> 38 #include <sys/intr.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/extent.h> 42 #include <sys/queue.h> 43 #include <sys/mutex.h> 44 #include <sys/kmem.h> 45 46 #include <machine/cpu.h> 47 48 #include <arm/cpufunc.h> 49 50 #include <dev/pci/pcireg.h> 51 #include <dev/pci/pcivar.h> 52 #include <dev/pci/pciconf.h> 53 54 #include <dev/acpi/acpivar.h> 55 #include <dev/acpi/acpi_pci.h> 56 #include <dev/acpi/acpi_mcfg.h> 57 58 #include <arm/acpi/acpi_pci_machdep.h> 59 60 #define PCIHOST_CACHELINE_SIZE arm_dcache_align 61 62 struct acpipchb_softc { 63 device_t sc_dev; 64 65 struct arm32_bus_dma_tag sc_dmat; 66 struct acpi_pci_context sc_ap; 67 68 ACPI_HANDLE sc_handle; 69 ACPI_INTEGER sc_bus; 70 71 struct bus_space sc_pciio_bst; 72 }; 73 74 static struct arm32_dma_range ahcipchb_coherent_ranges[] = { 75 [0] = { 76 .dr_sysbase = 0, 77 .dr_busbase = 0, 78 .dr_len = UINTPTR_MAX, 79 .dr_flags = _BUS_DMAMAP_COHERENT, 80 } 81 }; 82 83 static int acpipchb_match(device_t, cfdata_t, void *); 84 static void acpipchb_attach(device_t, device_t, void *); 85 86 static void acpipchb_setup_pciio(struct acpipchb_softc *, struct pcibus_attach_args *); 87 88 CFATTACH_DECL_NEW(acpipchb, sizeof(struct acpipchb_softc), 89 acpipchb_match, acpipchb_attach, NULL, NULL); 90 91 static const char * const compatible[] = { 92 "PNP0A08", 93 NULL 94 }; 95 96 static int 97 acpipchb_match(device_t parent, cfdata_t cf, void *aux) 98 { 99 struct acpi_attach_args *aa = aux; 100 101 if (aa->aa_node->ad_type != ACPI_TYPE_DEVICE) 102 return 0; 103 104 return acpi_match_hid(aa->aa_node->ad_devinfo, compatible); 105 } 106 107 static void 108 acpipchb_attach(device_t parent, device_t self, void *aux) 109 { 110 struct acpipchb_softc * const sc = device_private(self); 111 struct acpi_attach_args *aa = aux; 112 struct pcibus_attach_args pba; 113 ACPI_INTEGER cca, seg; 114 115 sc->sc_dev = self; 116 sc->sc_handle = aa->aa_node->ad_handle; 117 118 if (ACPI_FAILURE(acpi_eval_integer(sc->sc_handle, "_BBN", &sc->sc_bus))) 119 sc->sc_bus = 0; 120 121 if (ACPI_FAILURE(acpi_eval_integer(sc->sc_handle, "_SEG", &seg))) 122 seg = 0; 123 124 if (ACPI_FAILURE(acpi_eval_integer(sc->sc_handle, "_CCA", &cca))) 125 cca = 0; 126 127 aprint_naive("\n"); 128 aprint_normal(": PCI Express Host Bridge\n"); 129 130 sc->sc_dmat = *aa->aa_dmat; 131 if (cca) { 132 sc->sc_dmat._ranges = ahcipchb_coherent_ranges; 133 sc->sc_dmat._nranges = __arraycount(ahcipchb_coherent_ranges); 134 } 135 136 sc->sc_ap.ap_pc = *aa->aa_pc; 137 sc->sc_ap.ap_pc.pc_conf_v = &sc->sc_ap; 138 sc->sc_ap.ap_seg = seg; 139 140 if (acpi_pci_ignore_boot_config(sc->sc_handle)) { 141 if (acpimcfg_configure_bus(self, &sc->sc_ap.ap_pc, sc->sc_handle, sc->sc_bus, PCIHOST_CACHELINE_SIZE) != 0) 142 aprint_error_dev(self, "failed to configure bus\n"); 143 } 144 145 memset(&pba, 0, sizeof(pba)); 146 pba.pba_flags = aa->aa_pciflags; 147 pba.pba_iot = 0; 148 pba.pba_memt = aa->aa_memt; 149 pba.pba_dmat = &sc->sc_dmat; 150 #ifdef _PCI_HAVE_DMA64 151 pba.pba_dmat64 = &sc->sc_dmat; 152 #endif 153 pba.pba_pc = &sc->sc_ap.ap_pc; 154 pba.pba_bus = sc->sc_bus; 155 156 acpipchb_setup_pciio(sc, &pba); 157 158 config_found_ia(self, "pcibus", &pba, pcibusprint); 159 } 160 161 struct acpipchb_setup_pciio_args { 162 struct acpipchb_softc *sc; 163 struct pcibus_attach_args *pba; 164 }; 165 166 static ACPI_STATUS 167 acpipchb_setup_pciio_cb(ACPI_RESOURCE *res, void *ctx) 168 { 169 struct acpipchb_setup_pciio_args * const args = ctx; 170 struct acpipchb_softc * const sc = args->sc; 171 struct pcibus_attach_args *pba = args->pba; 172 173 if (res->Type != ACPI_RESOURCE_TYPE_ADDRESS32 && 174 res->Type != ACPI_RESOURCE_TYPE_ADDRESS64) 175 return AE_OK; 176 177 if (res->Data.Address.ResourceType != ACPI_IO_RANGE) 178 return AE_OK; 179 180 sc->sc_pciio_bst = *pba->pba_memt; 181 sc->sc_pciio_bst.bs_cookie = &sc->sc_pciio_bst; 182 183 switch (res->Type) { 184 case ACPI_RESOURCE_TYPE_ADDRESS32: 185 sc->sc_pciio_bst.bs_base = res->Data.Address32.Address.TranslationOffset; 186 sc->sc_pciio_bst.bs_stride = res->Data.Address32.Address.Granularity; 187 break; 188 case ACPI_RESOURCE_TYPE_ADDRESS64: 189 sc->sc_pciio_bst.bs_base = res->Data.Address64.Address.TranslationOffset; 190 sc->sc_pciio_bst.bs_stride = res->Data.Address64.Address.Granularity; 191 break; 192 } 193 194 aprint_debug_dev(sc->sc_dev, "PCI I/O base %#lx stride %d\n", sc->sc_pciio_bst.bs_base, sc->sc_pciio_bst.bs_stride); 195 196 pba->pba_iot = &sc->sc_pciio_bst; 197 pba->pba_flags |= PCI_FLAGS_IO_OKAY; 198 199 return AE_LIMIT; 200 } 201 202 static void 203 acpipchb_setup_pciio(struct acpipchb_softc *sc, struct pcibus_attach_args *pba) 204 { 205 struct acpipchb_setup_pciio_args args; 206 207 args.sc = sc; 208 args.pba = pba; 209 210 AcpiWalkResources(sc->sc_handle, "_CRS", acpipchb_setup_pciio_cb, &args); 211 } 212
Indexes created Tue Sep 23 14:10:03 GMT 2025