acpipchb.c revision 1.8
1 /* $NetBSD: acpipchb.c,v 1.8 2019/06/19 13:39:18 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jared McNeill <jmcneill (at) invisible.ca>. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: acpipchb.c,v 1.8 2019/06/19 13:39:18 jmcneill Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/device.h> 38 #include <sys/intr.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/extent.h> 42 #include <sys/queue.h> 43 #include <sys/mutex.h> 44 #include <sys/kmem.h> 45 46 #include <machine/cpu.h> 47 48 #include <arm/cpufunc.h> 49 50 #include <dev/pci/pcireg.h> 51 #include <dev/pci/pcivar.h> 52 #include <dev/pci/pciconf.h> 53 54 #include <dev/acpi/acpivar.h> 55 #include <dev/acpi/acpi_pci.h> 56 #include <dev/acpi/acpi_mcfg.h> 57 58 #include <arm/acpi/acpi_pci_machdep.h> 59 60 #define PCIHOST_CACHELINE_SIZE arm_dcache_align 61 62 struct acpipchb_bus_space { 63 struct bus_space bs; 64 65 bus_addr_t min; 66 bus_addr_t max; 67 bus_addr_t offset; 68 69 int (*map)(void *, bus_addr_t, bus_size_t, 70 int, bus_space_handle_t *); 71 }; 72 73 struct acpipchb_softc { 74 device_t sc_dev; 75 76 struct arm32_bus_dma_tag sc_dmat; 77 struct acpi_pci_context sc_ap; 78 79 ACPI_HANDLE sc_handle; 80 ACPI_INTEGER sc_bus; 81 82 struct acpipchb_bus_space sc_pciio_bst; 83 }; 84 85 static int acpipchb_match(device_t, cfdata_t, void *); 86 static void acpipchb_attach(device_t, device_t, void *); 87 88 static void acpipchb_setup_pciio(struct acpipchb_softc *, struct pcibus_attach_args *); 89 90 CFATTACH_DECL_NEW(acpipchb, sizeof(struct acpipchb_softc), 91 acpipchb_match, acpipchb_attach, NULL, NULL); 92 93 static const char * const compatible[] = { 94 "PNP0A08", 95 NULL 96 }; 97 98 static int 99 acpipchb_match(device_t parent, cfdata_t cf, void *aux) 100 { 101 struct acpi_attach_args *aa = aux; 102 103 if (aa->aa_node->ad_type != ACPI_TYPE_DEVICE) 104 return 0; 105 106 return acpi_match_hid(aa->aa_node->ad_devinfo, compatible); 107 } 108 109 static void 110 acpipchb_attach(device_t parent, device_t self, void *aux) 111 { 112 struct acpipchb_softc * const sc = device_private(self); 113 struct acpi_attach_args *aa = aux; 114 struct pcibus_attach_args pba; 115 ACPI_INTEGER cca, seg; 116 117 sc->sc_dev = self; 118 sc->sc_handle = aa->aa_node->ad_handle; 119 120 if (ACPI_FAILURE(acpi_eval_integer(sc->sc_handle, "_BBN", &sc->sc_bus))) 121 sc->sc_bus = 0; 122 123 if (ACPI_FAILURE(acpi_eval_integer(sc->sc_handle, "_SEG", &seg))) 124 seg = 0; 125 126 if (ACPI_FAILURE(acpi_eval_integer(sc->sc_handle, "_CCA", &cca))) 127 cca = 1; 128 129 aprint_naive("\n"); 130 aprint_normal(": PCI Express Host Bridge\n"); 131 132 sc->sc_dmat = *aa->aa_dmat; 133 if (cca == 0) 134 sc->sc_dmat._nranges = 0; 135 136 sc->sc_ap.ap_pc = *aa->aa_pc; 137 sc->sc_ap.ap_pc.pc_conf_v = &sc->sc_ap; 138 sc->sc_ap.ap_seg = seg; 139 140 if (acpi_pci_ignore_boot_config(sc->sc_handle)) { 141 if (acpimcfg_configure_bus(self, &sc->sc_ap.ap_pc, sc->sc_handle, sc->sc_bus, PCIHOST_CACHELINE_SIZE) != 0) 142 aprint_error_dev(self, "failed to configure bus\n"); 143 } 144 145 memset(&pba, 0, sizeof(pba)); 146 pba.pba_flags = aa->aa_pciflags; 147 pba.pba_iot = 0; 148 pba.pba_memt = aa->aa_memt; 149 pba.pba_dmat = &sc->sc_dmat; 150 #ifdef _PCI_HAVE_DMA64 151 pba.pba_dmat64 = &sc->sc_dmat; 152 #endif 153 pba.pba_pc = &sc->sc_ap.ap_pc; 154 pba.pba_bus = sc->sc_bus; 155 156 acpipchb_setup_pciio(sc, &pba); 157 158 config_found_ia(self, "pcibus", &pba, pcibusprint); 159 } 160 161 struct acpipchb_setup_pciio_args { 162 struct acpipchb_softc *sc; 163 struct pcibus_attach_args *pba; 164 }; 165 166 static int 167 acpipchb_bus_space_map(void *t, bus_addr_t bpa, bus_size_t size, int flag, 168 bus_space_handle_t *bshp) 169 { 170 struct acpipchb_bus_space * const abs = t; 171 172 if (bpa < abs->min || bpa + size >= abs->max) 173 return ERANGE; 174 175 return abs->map(t, bpa + abs->offset, size, flag, bshp); 176 } 177 178 static ACPI_STATUS 179 acpipchb_setup_pciio_cb(ACPI_RESOURCE *res, void *ctx) 180 { 181 struct acpipchb_setup_pciio_args * const args = ctx; 182 struct acpipchb_softc * const sc = args->sc; 183 struct acpipchb_bus_space * const abs = &sc->sc_pciio_bst; 184 struct pcibus_attach_args *pba = args->pba; 185 186 if (res->Type != ACPI_RESOURCE_TYPE_ADDRESS32 && 187 res->Type != ACPI_RESOURCE_TYPE_ADDRESS64) 188 return AE_OK; 189 190 if (res->Data.Address.ResourceType != ACPI_IO_RANGE) 191 return AE_OK; 192 193 abs->bs = *pba->pba_memt; 194 abs->bs.bs_cookie = abs; 195 abs->map = abs->bs.bs_map; 196 abs->bs.bs_map = acpipchb_bus_space_map; 197 198 switch (res->Type) { 199 case ACPI_RESOURCE_TYPE_ADDRESS32: 200 abs->min = res->Data.Address32.Address.Minimum; 201 abs->max = res->Data.Address32.Address.Maximum; 202 abs->offset = res->Data.Address32.Address.TranslationOffset; 203 break; 204 case ACPI_RESOURCE_TYPE_ADDRESS64: 205 abs->min = res->Data.Address64.Address.Minimum; 206 abs->max = res->Data.Address64.Address.Maximum; 207 abs->offset = res->Data.Address64.Address.TranslationOffset; 208 break; 209 } 210 211 aprint_debug_dev(sc->sc_dev, "PCI I/O [%#lx-%#lx] -> %#lx\n", abs->min, abs->max, abs->offset); 212 213 pba->pba_iot = &sc->sc_pciio_bst.bs; 214 pba->pba_flags |= PCI_FLAGS_IO_OKAY; 215 216 return AE_LIMIT; 217 } 218 219 static void 220 acpipchb_setup_pciio(struct acpipchb_softc *sc, struct pcibus_attach_args *pba) 221 { 222 struct acpipchb_setup_pciio_args args; 223 224 args.sc = sc; 225 args.pba = pba; 226 227 AcpiWalkResources(sc->sc_handle, "_CRS", acpipchb_setup_pciio_cb, &args); 228 } 229
Indexes created Tue Sep 23 02:09:52 GMT 2025