cpu_acpi.c revision 1.13 1 1.13 skrll /* $NetBSD: cpu_acpi.c,v 1.13 2021/11/25 09:36:20 skrll Exp $ */
2 1.1 jmcneill
3 1.1 jmcneill /*-
4 1.1 jmcneill * Copyright (c) 2018 The NetBSD Foundation, Inc.
5 1.1 jmcneill * All rights reserved.
6 1.1 jmcneill *
7 1.1 jmcneill * This code is derived from software contributed to The NetBSD Foundation
8 1.1 jmcneill * by Jared McNeill <jmcneill (at) invisible.ca>.
9 1.1 jmcneill *
10 1.1 jmcneill * Redistribution and use in source and binary forms, with or without
11 1.1 jmcneill * modification, are permitted provided that the following conditions
12 1.1 jmcneill * are met:
13 1.1 jmcneill * 1. Redistributions of source code must retain the above copyright
14 1.1 jmcneill * notice, this list of conditions and the following disclaimer.
15 1.1 jmcneill * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 jmcneill * notice, this list of conditions and the following disclaimer in the
17 1.1 jmcneill * documentation and/or other materials provided with the distribution.
18 1.1 jmcneill *
19 1.1 jmcneill * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 1.1 jmcneill * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 1.1 jmcneill * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 1.1 jmcneill * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 1.1 jmcneill * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 1.1 jmcneill * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 1.1 jmcneill * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 1.1 jmcneill * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 1.1 jmcneill * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 1.1 jmcneill * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 1.1 jmcneill * POSSIBILITY OF SUCH DAMAGE.
30 1.1 jmcneill */
31 1.1 jmcneill
32 1.5 jmcneill #include "tprof.h"
33 1.6 ryo #include "opt_multiprocessor.h"
34 1.5 jmcneill
35 1.1 jmcneill #include <sys/cdefs.h>
36 1.13 skrll __KERNEL_RCSID(0, "$NetBSD: cpu_acpi.c,v 1.13 2021/11/25 09:36:20 skrll Exp $");
37 1.1 jmcneill
38 1.1 jmcneill #include <sys/param.h>
39 1.1 jmcneill #include <sys/bus.h>
40 1.1 jmcneill #include <sys/cpu.h>
41 1.1 jmcneill #include <sys/device.h>
42 1.5 jmcneill #include <sys/interrupt.h>
43 1.5 jmcneill #include <sys/kcpuset.h>
44 1.7 jmcneill #include <sys/reboot.h>
45 1.1 jmcneill
46 1.1 jmcneill #include <dev/acpi/acpireg.h>
47 1.1 jmcneill #include <dev/acpi/acpivar.h>
48 1.1 jmcneill
49 1.1 jmcneill #include <arm/armreg.h>
50 1.1 jmcneill #include <arm/cpu.h>
51 1.1 jmcneill #include <arm/cpufunc.h>
52 1.8 skrll #include <arm/cpuvar.h>
53 1.1 jmcneill #include <arm/locore.h>
54 1.1 jmcneill
55 1.1 jmcneill #include <arm/arm/psci.h>
56 1.1 jmcneill
57 1.5 jmcneill #if NTPROF > 0
58 1.5 jmcneill #include <dev/tprof/tprof_armv8.h>
59 1.5 jmcneill #endif
60 1.5 jmcneill
61 1.1 jmcneill static int cpu_acpi_match(device_t, cfdata_t, void *);
62 1.1 jmcneill static void cpu_acpi_attach(device_t, device_t, void *);
63 1.1 jmcneill
64 1.5 jmcneill #if NTPROF > 0
65 1.5 jmcneill static void cpu_acpi_tprof_init(device_t);
66 1.5 jmcneill #endif
67 1.5 jmcneill
68 1.1 jmcneill CFATTACH_DECL_NEW(cpu_acpi, 0, cpu_acpi_match, cpu_acpi_attach, NULL, NULL);
69 1.1 jmcneill
70 1.6 ryo #ifdef MULTIPROCESSOR
71 1.1 jmcneill static register_t
72 1.1 jmcneill cpu_acpi_mpstart_pa(void)
73 1.1 jmcneill {
74 1.3 skrll
75 1.3 skrll return (register_t)KERN_VTOPHYS((vaddr_t)cpu_mpstart);
76 1.1 jmcneill }
77 1.6 ryo #endif /* MULTIPROCESSOR */
78 1.1 jmcneill
79 1.1 jmcneill static int
80 1.1 jmcneill cpu_acpi_match(device_t parent, cfdata_t cf, void *aux)
81 1.1 jmcneill {
82 1.1 jmcneill ACPI_SUBTABLE_HEADER *hdrp = aux;
83 1.2 jmcneill ACPI_MADT_GENERIC_INTERRUPT *gicc;
84 1.1 jmcneill
85 1.2 jmcneill if (hdrp->Type != ACPI_MADT_TYPE_GENERIC_INTERRUPT)
86 1.2 jmcneill return 0;
87 1.2 jmcneill
88 1.2 jmcneill gicc = (ACPI_MADT_GENERIC_INTERRUPT *)hdrp;
89 1.2 jmcneill
90 1.2 jmcneill return (gicc->Flags & ACPI_MADT_ENABLED) != 0;
91 1.1 jmcneill }
92 1.1 jmcneill
93 1.1 jmcneill static void
94 1.1 jmcneill cpu_acpi_attach(device_t parent, device_t self, void *aux)
95 1.1 jmcneill {
96 1.12 jmcneill prop_dictionary_t dict = device_properties(self);
97 1.1 jmcneill ACPI_MADT_GENERIC_INTERRUPT *gicc = aux;
98 1.1 jmcneill const uint64_t mpidr = gicc->ArmMpidr;
99 1.4 jmcneill const int unit = device_unit(self);
100 1.4 jmcneill struct cpu_info *ci = &cpu_info_store[unit];
101 1.1 jmcneill
102 1.6 ryo #ifdef MULTIPROCESSOR
103 1.7 jmcneill if (cpu_mpidr_aff_read() != mpidr && (boothowto & RB_MD1) == 0) {
104 1.1 jmcneill const u_int cpuindex = device_unit(self);
105 1.6 ryo int error;
106 1.1 jmcneill
107 1.1 jmcneill cpu_mpidr[cpuindex] = mpidr;
108 1.10 jmcneill cpu_dcache_wb_range((vaddr_t)&cpu_mpidr[cpuindex],
109 1.10 jmcneill sizeof(cpu_mpidr[cpuindex]));
110 1.1 jmcneill
111 1.1 jmcneill /* XXX support spin table */
112 1.1 jmcneill error = psci_cpu_on(mpidr, cpu_acpi_mpstart_pa(), 0);
113 1.1 jmcneill if (error != PSCI_SUCCESS) {
114 1.1 jmcneill aprint_error_dev(self, "failed to start CPU\n");
115 1.1 jmcneill return;
116 1.1 jmcneill }
117 1.1 jmcneill
118 1.9 skrll sev();
119 1.1 jmcneill
120 1.1 jmcneill for (u_int i = 0x10000000; i > 0; i--) {
121 1.7 jmcneill if (cpu_hatched_p(cpuindex))
122 1.7 jmcneill break;
123 1.1 jmcneill }
124 1.1 jmcneill }
125 1.6 ryo #endif /* MULTIPROCESSOR */
126 1.1 jmcneill
127 1.12 jmcneill /* Assume that less efficient processors are faster. */
128 1.12 jmcneill prop_dictionary_set_uint32(dict, "capacity_dmips_mhz",
129 1.12 jmcneill gicc->EfficiencyClass);
130 1.12 jmcneill
131 1.4 jmcneill /* Store the ACPI Processor UID in cpu_info */
132 1.4 jmcneill ci->ci_acpiid = gicc->Uid;
133 1.4 jmcneill
134 1.1 jmcneill /* Attach the CPU */
135 1.1 jmcneill cpu_attach(self, mpidr);
136 1.5 jmcneill
137 1.5 jmcneill #if NTPROF > 0
138 1.5 jmcneill if (cpu_mpidr_aff_read() == mpidr)
139 1.5 jmcneill config_interrupts(self, cpu_acpi_tprof_init);
140 1.5 jmcneill #endif
141 1.5 jmcneill }
142 1.5 jmcneill
143 1.5 jmcneill #if NTPROF > 0
144 1.5 jmcneill static struct cpu_info *
145 1.5 jmcneill cpu_acpi_find_processor(UINT32 uid)
146 1.5 jmcneill {
147 1.5 jmcneill CPU_INFO_ITERATOR cii;
148 1.5 jmcneill struct cpu_info *ci;
149 1.5 jmcneill
150 1.5 jmcneill for (CPU_INFO_FOREACH(cii, ci)) {
151 1.5 jmcneill if (ci->ci_acpiid == uid)
152 1.5 jmcneill return ci;
153 1.5 jmcneill }
154 1.5 jmcneill
155 1.5 jmcneill return NULL;
156 1.5 jmcneill }
157 1.5 jmcneill
158 1.5 jmcneill static ACPI_STATUS
159 1.5 jmcneill cpu_acpi_tprof_intr_establish(ACPI_SUBTABLE_HEADER *hdrp, void *aux)
160 1.5 jmcneill {
161 1.5 jmcneill device_t dev = aux;
162 1.5 jmcneill ACPI_MADT_GENERIC_INTERRUPT *gicc;
163 1.5 jmcneill struct cpu_info *ci;
164 1.5 jmcneill char xname[16];
165 1.5 jmcneill kcpuset_t *set;
166 1.5 jmcneill int error;
167 1.5 jmcneill void *ih;
168 1.5 jmcneill
169 1.5 jmcneill if (hdrp->Type != ACPI_MADT_TYPE_GENERIC_INTERRUPT)
170 1.5 jmcneill return AE_OK;
171 1.5 jmcneill
172 1.5 jmcneill gicc = (ACPI_MADT_GENERIC_INTERRUPT *)hdrp;
173 1.5 jmcneill if ((gicc->Flags & ACPI_MADT_ENABLED) == 0)
174 1.5 jmcneill return AE_OK;
175 1.5 jmcneill
176 1.11 jmcneill const bool cpu_primary_p = cpu_info_store[0].ci_cpuid == gicc->ArmMpidr;
177 1.5 jmcneill const bool intr_ppi_p = gicc->PerformanceInterrupt < 32;
178 1.10 jmcneill const int type = (gicc->Flags & ACPI_MADT_PERFORMANCE_IRQ_MODE) ?
179 1.10 jmcneill IST_EDGE : IST_LEVEL;
180 1.5 jmcneill
181 1.5 jmcneill if (intr_ppi_p && !cpu_primary_p)
182 1.5 jmcneill return AE_OK;
183 1.5 jmcneill
184 1.5 jmcneill ci = cpu_acpi_find_processor(gicc->Uid);
185 1.5 jmcneill if (ci == NULL) {
186 1.10 jmcneill aprint_error_dev(dev, "couldn't find processor %#x\n",
187 1.10 jmcneill gicc->Uid);
188 1.5 jmcneill return AE_OK;
189 1.5 jmcneill }
190 1.5 jmcneill
191 1.5 jmcneill if (intr_ppi_p) {
192 1.5 jmcneill strlcpy(xname, "pmu", sizeof(xname));
193 1.5 jmcneill } else {
194 1.5 jmcneill snprintf(xname, sizeof(xname), "pmu %s", cpu_name(ci));
195 1.5 jmcneill }
196 1.5 jmcneill
197 1.10 jmcneill ih = intr_establish_xname(gicc->PerformanceInterrupt, IPL_HIGH,
198 1.10 jmcneill type | IST_MPSAFE, armv8_pmu_intr, NULL, xname);
199 1.5 jmcneill if (ih == NULL) {
200 1.10 jmcneill aprint_error_dev(dev, "couldn't establish %s interrupt\n",
201 1.10 jmcneill xname);
202 1.5 jmcneill return AE_OK;
203 1.5 jmcneill }
204 1.5 jmcneill
205 1.5 jmcneill if (!intr_ppi_p) {
206 1.5 jmcneill kcpuset_create(&set, true);
207 1.5 jmcneill kcpuset_set(set, cpu_index(ci));
208 1.5 jmcneill error = interrupt_distribute(ih, set, NULL);
209 1.5 jmcneill kcpuset_destroy(set);
210 1.5 jmcneill
211 1.5 jmcneill if (error) {
212 1.10 jmcneill aprint_error_dev(dev,
213 1.10 jmcneill "failed to distribute %s interrupt: %d\n",
214 1.5 jmcneill xname, error);
215 1.5 jmcneill return AE_OK;
216 1.5 jmcneill }
217 1.5 jmcneill }
218 1.5 jmcneill
219 1.10 jmcneill aprint_normal("%s: PMU interrupting on irq %d\n", cpu_name(ci),
220 1.10 jmcneill gicc->PerformanceInterrupt);
221 1.5 jmcneill
222 1.5 jmcneill return AE_OK;
223 1.5 jmcneill }
224 1.5 jmcneill
225 1.5 jmcneill static void
226 1.5 jmcneill cpu_acpi_tprof_init(device_t self)
227 1.5 jmcneill {
228 1.13 skrll int err = armv8_pmu_init();
229 1.13 skrll if (err) {
230 1.13 skrll aprint_error_dev(self,
231 1.13 skrll "failed to initialize PMU event counter\n");
232 1.13 skrll return;
233 1.13 skrll }
234 1.5 jmcneill
235 1.5 jmcneill if (acpi_madt_map() != AE_OK) {
236 1.10 jmcneill aprint_error_dev(self,
237 1.10 jmcneill "failed to map MADT, performance counters not available\n");
238 1.5 jmcneill return;
239 1.5 jmcneill }
240 1.5 jmcneill acpi_madt_walk(cpu_acpi_tprof_intr_establish, self);
241 1.5 jmcneill acpi_madt_unmap();
242 1.1 jmcneill }
243 1.5 jmcneill #endif
244