| History log of /src/sys/arch/arm/acpi/cpu_acpi.c |
| Revision | | Date | Author | Comments |
| 1.18 |
| 30-Jan-2025 |
jmcneill | arm: acpi: Early return when a CPU is not configured
|
| 1.17 |
| 30-Dec-2024 |
jmcneill | arm64: Enable support for low power idle CPU states on ACPI platforms.
The ACPI CPU driver parses the _LPI package on each CPU and builds a
table of supported low power states. A custom cpu_idle() implementation
is registered that uses the time previously spent idle to select an
entry method for low power on the next idle entry.
A boot option, "nolpi", can be used to ignore _LPI and use the normal
WFI idle method.
This decreases the battery discharge rate on my Snapdragon X1E laptop from
~17W to ~10W when idle.
|
| 1.16 |
| 30-Jun-2024 |
jmcneill | aarch64: Add NUMA awareness for ACPI systems with SRAT tables.
On an Ampere Altra w/ hemisphere mode enabled:
[ 1.0000000] cpu0: package 16, core 0, smt 0, numa 0
[...]
[ 1.0000000] cpu32: package 22, core 0, smt 0, numa 1
[ 1.000004] SRAT: 2 NUMA nodes
[ 1.000004] SRAT: node 0 memory range 0 (0x88300000 - 0x88400000 flags 1)
[ 1.000004] SRAT: node 0 memory range 1 (0x90000000 - 0x100000000 flags 1)
[ 1.000004] SRAT: node 0 memory range 2 (0x80000000000 - 0x80080000000 flags 1)
[ 1.000004] SRAT: node 0 memory range 3 (0x80100000000 - 0x81000000000 flags 1)
[ 1.000004] SRAT: node 1 memory range 0 (0xc0000000000 - 0xc1000000000 flags 1)
|
| 1.15 |
| 09-May-2024 |
pho | branches: 1.15.2;
kern/58195: arm: Support drvctl -d and -r for cpufeaturebus
This is required for detaching and re-attaching the vmt(4) driver on aarch64.
|
| 1.14 |
| 16-May-2022 |
jmcneill | tprof: armv8: Only attach to known PMU types.
|
| 1.13 |
| 25-Nov-2021 |
skrll | Improve error handling.
Hypervisors can return a PMCR.N of 0.
|
| 1.12 |
| 24-Nov-2021 |
jmcneill | arm64: acpi: Set capacity_dmips_mhz for CPUs
The GICC structure describes a relative power efficiency for each
processor. Use this value as-is for the capacity_dmips_mhz value of a
cpu. This makes the assumption that "more efficient" means "slower".
|
| 1.11 |
| 17-Oct-2021 |
jmcneill | Fix primary CPU detection in cpu_acpi_tprof_intr_establish
|
| 1.10 |
| 23-Jan-2021 |
jmcneill | fit in 80 columns
|
| 1.9 |
| 03-Dec-2020 |
skrll | Provide and use a sev() macro for the sev instruction.
While here use the correct barrier to ensure completion of memory accesses
before a couple of the sev() calls.
|
| 1.8 |
| 15-Feb-2020 |
skrll | branches: 1.8.6;
Various updates and improvements to cpu start up on arm/aarch64
- start sharing more code around the AP startup messaging.
- call arm_cpu_topology_set early so that ci_core_id is available for
drivers, e.g. bcm2835_intr.c
- both arm and aarch64 now have
- a static cpu_info_store array
- the same arm_cpu_{hatched,mbox}
|
| 1.7 |
| 19-Oct-2019 |
jmcneill | branches: 1.7.2;
Increase aarch64 MAXCPUS to 256.
|
| 1.6 |
| 23-May-2019 |
ryo | branches: 1.6.2; 1.6.4;
fix build without options MULTIPROCESSOR
|
| 1.5 |
| 05-Dec-2018 |
jmcneill | Add CPU performance counter support
|
| 1.4 |
| 19-Oct-2018 |
jmcneill | branches: 1.4.2;
Store the ACPI Processor UID in struct cpu_info
|
| 1.3 |
| 18-Oct-2018 |
skrll | Provide generic start code that assumes the MMU is off and caches are
disabled as per the linux booting protocol for ARMv6 and ARMv7 boards.
u-boot image type should be changed to 'linux' for correct behaviour.
The new start code builds a minimal "bootstrap" L1PT with cached access
disabled and uses the same table for all processors. AP startup is
performed in less steps and more code is written in C.
The bootstrap tables and stack are placed into an (orphaned) section
"_init_memory" which is given to uvm when it is no longer used.
Various kernels have been converted to use this code and tested. Some
boards were provided by TNF. Thanks!
The GENERIC kernel now boots on boards using the TEGRA, SUNXI and EXYNOS
kernels. The GENERIC kernel will also work on RPI2 using u-boot.
Thanks to martin@ and aymeric@ for testing on parallella and nanosoc
respectively
|
| 1.2 |
| 16-Oct-2018 |
jmcneill | Only attach to usable processors
|
| 1.1 |
| 12-Oct-2018 |
jmcneill | Add ACPI platform glue and basic device drivers (CPU, GIC, Generic Timer,
SBSA UART).
|
| 1.4.2.3 |
| 26-Dec-2018 |
pgoyette | Sync with HEAD, resolve a few conflicts
|
| 1.4.2.2 |
| 20-Oct-2018 |
pgoyette | Sync with head
|
| 1.4.2.1 |
| 19-Oct-2018 |
pgoyette | file cpu_acpi.c was added on branch pgoyette-compat on 2018-10-20 06:58:24 +0000
|
| 1.6.4.1 |
| 23-Oct-2019 |
martin | Pull up following revision(s) (requested by jmcneill in ticket #359):
sys/arch/aarch64/aarch64/locore.S: revision 1.42
sys/arch/aarch64/aarch64/locore.S: revision 1.43
sys/arch/aarch64/aarch64/locore.S: revision 1.44
sys/arch/arm/fdt/cpu_fdt.c: revision 1.28
sys/arch/aarch64/include/cpu.h: revision 1.14
sys/arch/aarch64/include/param.h: revision 1.12
sys/arch/arm/arm32/cpu.c: revision 1.133
sys/arch/arm/arm32/cpu.c: revision 1.134
sys/arch/arm/include/cpu.h: revision 1.101
sys/arch/arm/acpi/cpu_acpi.c: revision 1.7
sys/arch/aarch64/aarch64/cpu.c: revision 1.23
sys/arch/aarch64/aarch64/cpu.c: revision 1.24
sys/arch/aarch64/aarch64/cpu.c: revision 1.25
Increase aarch64 MAXCPUS to 256.
-
Invalidate dcache before polling AP hatched status
-
Avoid overlap between BP and last AP stack. AP stacks are now in order of
increasing address order.
Spotted by and idea from mlelstv.
-
Use separate cacheline aligned arrays for mbox and hatched as before.
-
cpu_hatched_p only for MULTIPROCESSOR
|
| 1.6.2.4 |
| 13-Apr-2020 |
martin | Mostly merge changes from HEAD upto 20200411
|
| 1.6.2.3 |
| 08-Apr-2020 |
martin | Merge changes from current as of 20200406
|
| 1.6.2.2 |
| 10-Jun-2019 |
christos | Sync with HEAD
|
| 1.6.2.1 |
| 23-May-2019 |
christos | file cpu_acpi.c was added on branch phil-wifi on 2019-06-10 22:05:50 +0000
|
| 1.7.2.1 |
| 29-Feb-2020 |
ad | Sync with head.
|
| 1.8.6.2 |
| 03-Apr-2021 |
thorpej | Sync with HEAD.
|
| 1.8.6.1 |
| 14-Dec-2020 |
thorpej | Sync w/ HEAD.
|
| 1.15.2.1 |
| 01-Jul-2024 |
perseant | Sync with HEAD.
|
