1 1.45 ryo /* $NetBSD: arm32_boot.c,v 1.45 2022/12/22 06:58:08 ryo Exp $ */ 2 1.1 matt 3 1.1 matt /* 4 1.1 matt * Copyright (c) 2002, 2003, 2005 Genetec Corporation. All rights reserved. 5 1.1 matt * Written by Hiroyuki Bessho for Genetec Corporation. 6 1.1 matt * 7 1.1 matt * Redistribution and use in source and binary forms, with or without 8 1.1 matt * modification, are permitted provided that the following conditions 9 1.1 matt * are met: 10 1.1 matt * 1. Redistributions of source code must retain the above copyright 11 1.1 matt * notice, this list of conditions and the following disclaimer. 12 1.1 matt * 2. Redistributions in binary form must reproduce the above copyright 13 1.1 matt * notice, this list of conditions and the following disclaimer in the 14 1.1 matt * documentation and/or other materials provided with the distribution. 15 1.1 matt * 3. The name of Genetec Corporation may not be used to endorse or 16 1.1 matt * promote products derived from this software without specific prior 17 1.1 matt * written permission. 18 1.1 matt * 19 1.1 matt * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 20 1.1 matt * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 1.1 matt * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 1.1 matt * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 23 1.1 matt * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 1.1 matt * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 1.1 matt * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 1.1 matt * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 1.1 matt * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 1.1 matt * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 1.1 matt * POSSIBILITY OF SUCH DAMAGE. 30 1.1 matt * 31 1.1 matt * Copyright (c) 2001 Wasabi Systems, Inc. 32 1.1 matt * All rights reserved. 33 1.1 matt * 34 1.1 matt * Written by Jason R. Thorpe for Wasabi Systems, Inc. 35 1.1 matt * 36 1.1 matt * Redistribution and use in source and binary forms, with or without 37 1.1 matt * modification, are permitted provided that the following conditions 38 1.1 matt * are met: 39 1.1 matt * 1. Redistributions of source code must retain the above copyright 40 1.1 matt * notice, this list of conditions and the following disclaimer. 41 1.1 matt * 2. Redistributions in binary form must reproduce the above copyright 42 1.1 matt * notice, this list of conditions and the following disclaimer in the 43 1.1 matt * documentation and/or other materials provided with the distribution. 44 1.1 matt * 3. All advertising materials mentioning features or use of this software 45 1.1 matt * must display the following acknowledgement: 46 1.1 matt * This product includes software developed for the NetBSD Project by 47 1.1 matt * Wasabi Systems, Inc. 48 1.1 matt * 4. The name of Wasabi Systems, Inc. may not be used to endorse 49 1.1 matt * or promote products derived from this software without specific prior 50 1.1 matt * written permission. 51 1.1 matt * 52 1.1 matt * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 53 1.1 matt * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 54 1.1 matt * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 55 1.1 matt * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 56 1.1 matt * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 57 1.1 matt * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 58 1.1 matt * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 59 1.1 matt * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 60 1.1 matt * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 61 1.1 matt * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 62 1.1 matt * POSSIBILITY OF SUCH DAMAGE. 63 1.1 matt * 64 1.1 matt * Copyright (c) 1997,1998 Mark Brinicombe. 65 1.1 matt * Copyright (c) 1997,1998 Causality Limited. 66 1.1 matt * All rights reserved. 67 1.1 matt * 68 1.1 matt * Redistribution and use in source and binary forms, with or without 69 1.1 matt * modification, are permitted provided that the following conditions 70 1.1 matt * are met: 71 1.1 matt * 1. Redistributions of source code must retain the above copyright 72 1.1 matt * notice, this list of conditions and the following disclaimer. 73 1.1 matt * 2. Redistributions in binary form must reproduce the above copyright 74 1.1 matt * notice, this list of conditions and the following disclaimer in the 75 1.1 matt * documentation and/or other materials provided with the distribution. 76 1.1 matt * 3. All advertising materials mentioning features or use of this software 77 1.1 matt * must display the following acknowledgement: 78 1.1 matt * This product includes software developed by Mark Brinicombe 79 1.1 matt * for the NetBSD Project. 80 1.1 matt * 4. The name of the company nor the name of the author may be used to 81 1.1 matt * endorse or promote products derived from this software without specific 82 1.1 matt * prior written permission. 83 1.1 matt * 84 1.1 matt * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 85 1.1 matt * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 86 1.1 matt * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 87 1.1 matt * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 88 1.1 matt * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 89 1.1 matt * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 90 1.1 matt * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 91 1.1 matt * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 92 1.1 matt * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 93 1.1 matt * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 94 1.1 matt * SUCH DAMAGE. 95 1.1 matt * 96 1.1 matt * Copyright (c) 2007 Microsoft 97 1.1 matt * All rights reserved. 98 1.1 matt * 99 1.1 matt * Redistribution and use in source and binary forms, with or without 100 1.1 matt * modification, are permitted provided that the following conditions 101 1.1 matt * are met: 102 1.1 matt * 1. Redistributions of source code must retain the above copyright 103 1.1 matt * notice, this list of conditions and the following disclaimer. 104 1.1 matt * 2. Redistributions in binary form must reproduce the above copyright 105 1.1 matt * notice, this list of conditions and the following disclaimer in the 106 1.1 matt * documentation and/or other materials provided with the distribution. 107 1.1 matt * 3. All advertising materials mentioning features or use of this software 108 1.1 matt * must display the following acknowledgement: 109 1.1 matt * This product includes software developed by Microsoft 110 1.1 matt * 111 1.1 matt * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 112 1.1 matt * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 113 1.1 matt * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 114 1.1 matt * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTERS BE LIABLE FOR ANY DIRECT, 115 1.1 matt * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 116 1.1 matt * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 117 1.1 matt * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 118 1.1 matt * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 119 1.1 matt * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 120 1.1 matt * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 121 1.1 matt * SUCH DAMAGE. 122 1.1 matt */ 123 1.1 matt 124 1.1 matt #include <sys/cdefs.h> 125 1.45 ryo __KERNEL_RCSID(1, "$NetBSD: arm32_boot.c,v 1.45 2022/12/22 06:58:08 ryo Exp $"); 126 1.3 skrll 127 1.20 skrll #include "opt_arm_debug.h" 128 1.21 skrll #include "opt_cputypes.h" 129 1.3 skrll #include "opt_ddb.h" 130 1.3 skrll #include "opt_kgdb.h" 131 1.9 skrll #include "opt_multiprocessor.h" 132 1.1 matt 133 1.1 matt #include <sys/param.h> 134 1.38 skrll 135 1.39 skrll #include <sys/asan.h> 136 1.38 skrll #include <sys/atomic.h> 137 1.1 matt #include <sys/cpu.h> 138 1.38 skrll #include <sys/device.h> 139 1.1 matt #include <sys/intr.h> 140 1.38 skrll #include <sys/reboot.h> 141 1.1 matt 142 1.1 matt #include <uvm/uvm_extern.h> 143 1.1 matt 144 1.5 matt #include <arm/locore.h> 145 1.1 matt #include <arm/undefined.h> 146 1.1 matt #include <arm/arm32/machdep.h> 147 1.1 matt 148 1.1 matt #include <machine/db_machdep.h> 149 1.1 matt #include <ddb/db_extern.h> 150 1.1 matt 151 1.1 matt #include <machine/bootconfig.h> 152 1.1 matt 153 1.3 skrll #ifdef KGDB 154 1.3 skrll #include <sys/kgdb.h> 155 1.3 skrll #endif 156 1.3 skrll 157 1.20 skrll #ifdef VERBOSE_INIT_ARM 158 1.20 skrll #define VPRINTF(...) printf(__VA_ARGS__) 159 1.20 skrll #else 160 1.23 skrll #define VPRINTF(...) __nothing 161 1.20 skrll #endif 162 1.20 skrll 163 1.1 matt vaddr_t 164 1.1 matt initarm_common(vaddr_t kvm_base, vsize_t kvm_size, 165 1.1 matt const struct boot_physmem *bp, size_t nbp) 166 1.1 matt { 167 1.1 matt struct bootmem_info * const bmi = &bootmem_info; 168 1.1 matt 169 1.20 skrll VPRINTF("nfreeblocks = %u, free_pages = %d (%#x)\n", 170 1.1 matt bmi->bmi_nfreeblocks, bmi->bmi_freepages, 171 1.1 matt bmi->bmi_freepages); 172 1.1 matt 173 1.1 matt /* 174 1.1 matt * Moved from cpu_startup() as data_abort_handler() references 175 1.1 matt * this during uvm init. 176 1.1 matt */ 177 1.1 matt uvm_lwp_setuarea(&lwp0, kernelstack.pv_va); 178 1.1 matt 179 1.19 skrll struct lwp * const l = &lwp0; 180 1.19 skrll struct pcb * const pcb = lwp_getpcb(l); 181 1.19 skrll 182 1.19 skrll /* Zero out the PCB. */ 183 1.19 skrll memset(pcb, 0, sizeof(*pcb)); 184 1.19 skrll 185 1.19 skrll pcb->pcb_ksp = uvm_lwp_getuarea(l) + USPACE_SVC_STACK_TOP; 186 1.19 skrll pcb->pcb_ksp -= sizeof(struct trapframe); 187 1.19 skrll 188 1.19 skrll struct trapframe * tf = (struct trapframe *)pcb->pcb_ksp; 189 1.19 skrll 190 1.19 skrll /* Zero out the trapframe. */ 191 1.19 skrll memset(tf, 0, sizeof(*tf)); 192 1.19 skrll lwp_settrapframe(l, tf); 193 1.19 skrll 194 1.19 skrll tf->tf_spsr = PSR_USR32_MODE; 195 1.41 rin #ifdef _ARM_ARCH_BE8 196 1.41 rin tf->tf_spsr |= PSR_E_BIT; 197 1.19 skrll #endif 198 1.19 skrll 199 1.20 skrll VPRINTF("bootstrap done.\n"); 200 1.1 matt 201 1.20 skrll VPRINTF("vectors"); 202 1.1 matt arm32_vector_init(systempage.pv_va, ARM_VEC_ALL); 203 1.20 skrll VPRINTF(" %#"PRIxVADDR"\n", vector_page); 204 1.1 matt 205 1.1 matt /* 206 1.1 matt * Pages were allocated during the secondary bootstrap for the 207 1.1 matt * stacks for different CPU modes. 208 1.1 matt * We must now set the r13 registers in the different CPU modes to 209 1.1 matt * point to these stacks. 210 1.1 matt * Since the ARM stacks use STMFD etc. we must set r13 to the top end 211 1.1 matt * of the stack memory. 212 1.1 matt */ 213 1.20 skrll VPRINTF("init subsystems: stacks "); 214 1.1 matt set_stackptr(PSR_FIQ32_MODE, 215 1.1 matt fiqstack.pv_va + FIQ_STACK_SIZE * PAGE_SIZE); 216 1.1 matt set_stackptr(PSR_IRQ32_MODE, 217 1.1 matt irqstack.pv_va + IRQ_STACK_SIZE * PAGE_SIZE); 218 1.1 matt set_stackptr(PSR_ABT32_MODE, 219 1.1 matt abtstack.pv_va + ABT_STACK_SIZE * PAGE_SIZE); 220 1.1 matt set_stackptr(PSR_UND32_MODE, 221 1.1 matt undstack.pv_va + UND_STACK_SIZE * PAGE_SIZE); 222 1.1 matt 223 1.1 matt /* 224 1.1 matt * Well we should set a data abort handler. 225 1.1 matt * Once things get going this will change as we will need a proper 226 1.1 matt * handler. 227 1.1 matt * Until then we will use a handler that just panics but tells us 228 1.1 matt * why. 229 1.1 matt * Initialisation of the vectors will just panic on a data abort. 230 1.1 matt * This just fills in a slightly better one. 231 1.1 matt */ 232 1.20 skrll VPRINTF("vectors "); 233 1.1 matt data_abort_handler_address = (u_int)data_abort_handler; 234 1.1 matt prefetch_abort_handler_address = (u_int)prefetch_abort_handler; 235 1.1 matt undefined_handler_address = (u_int)undefinedinstruction_bounce; 236 1.1 matt 237 1.1 matt /* Initialise the undefined instruction handlers */ 238 1.20 skrll VPRINTF("undefined "); 239 1.1 matt undefined_init(); 240 1.1 matt 241 1.44 skrll #ifdef FPU_VFP 242 1.44 skrll /* vfp_detect uses an undefined handler */ 243 1.44 skrll VPRINTF("vfp "); 244 1.44 skrll vfp_detect(curcpu()); 245 1.44 skrll #endif 246 1.44 skrll 247 1.1 matt /* Load memory into UVM. */ 248 1.20 skrll VPRINTF("page "); 249 1.18 cherry uvm_md_init(); 250 1.1 matt 251 1.24 skrll VPRINTF("pmap_physload\n"); 252 1.2 matt KASSERT(bp != NULL || nbp == 0); 253 1.2 matt KASSERT(bp == NULL || nbp != 0); 254 1.1 matt 255 1.2 matt for (size_t i = 0; i < bmi->bmi_nfreeblocks; i++) { 256 1.2 matt pv_addr_t * const pv = &bmi->bmi_freeblocks[i]; 257 1.2 matt paddr_t start = atop(pv->pv_pa); 258 1.2 matt const paddr_t end = start + atop(pv->pv_size); 259 1.24 skrll int vm_freelist = VM_FREELIST_DEFAULT; 260 1.2 matt 261 1.24 skrll VPRINTF("block %2zu start %08lx end %08lx", i, 262 1.24 skrll pv->pv_pa, pv->pv_pa + pv->pv_size); 263 1.24 skrll 264 1.24 skrll if (!bp) { 265 1.24 skrll VPRINTF("... loading in freelist %d\n", vm_freelist); 266 1.24 skrll uvm_page_physload(start, end, start, end, VM_FREELIST_DEFAULT); 267 1.24 skrll continue; 268 1.24 skrll } 269 1.27 skrll VPRINTF("\n"); 270 1.43 skrll 271 1.43 skrll /* 272 1.43 skrll * This assumes the bp list is sorted in ascending 273 1.43 skrll * order. 274 1.43 skrll */ 275 1.24 skrll paddr_t segend = end; 276 1.43 skrll for (size_t j = 0; j < nbp && start < end; j++) { 277 1.24 skrll paddr_t bp_start = bp[j].bp_start; 278 1.24 skrll paddr_t bp_end = bp_start + bp[j].bp_pages; 279 1.24 skrll 280 1.27 skrll VPRINTF(" bp %2zu start %08lx end %08lx\n", 281 1.24 skrll j, ptoa(bp_start), ptoa(bp_end)); 282 1.43 skrll 283 1.24 skrll KASSERT(bp_start < bp_end); 284 1.43 skrll if (start >= bp_end || segend < bp_start) 285 1.24 skrll continue; 286 1.24 skrll 287 1.24 skrll if (start < bp_start) 288 1.24 skrll start = bp_start; 289 1.24 skrll 290 1.24 skrll if (start < bp_end) { 291 1.24 skrll if (segend > bp_end) { 292 1.24 skrll segend = bp_end; 293 1.2 matt } 294 1.24 skrll vm_freelist = bp[j].bp_freelist; 295 1.24 skrll 296 1.24 skrll VPRINTF(" start %08lx end %08lx" 297 1.27 skrll "... loading in freelist %d\n", ptoa(start), 298 1.25 skrll ptoa(segend), vm_freelist); 299 1.43 skrll 300 1.43 skrll uvm_page_physload(start, segend, start, segend, 301 1.43 skrll vm_freelist); 302 1.43 skrll 303 1.24 skrll start = segend; 304 1.24 skrll segend = end; 305 1.2 matt } 306 1.1 matt } 307 1.1 matt } 308 1.1 matt 309 1.40 skrll /* 310 1.40 skrll * Bootstrap pmap telling it where the managed kernel virtual memory 311 1.40 skrll * is. 312 1.40 skrll */ 313 1.20 skrll VPRINTF("pmap "); 314 1.1 matt pmap_bootstrap(kvm_base, kvm_base + kvm_size); 315 1.17 skrll 316 1.39 skrll kasan_init(); 317 1.39 skrll 318 1.1 matt #ifdef __HAVE_MEMORY_DISK__ 319 1.1 matt md_root_setconf(memory_disk, sizeof memory_disk); 320 1.1 matt #endif 321 1.1 matt 322 1.1 matt #ifdef BOOTHOWTO 323 1.1 matt boothowto |= BOOTHOWTO; 324 1.1 matt #endif 325 1.1 matt 326 1.1 matt #ifdef KGDB 327 1.1 matt if (boothowto & RB_KDB) { 328 1.1 matt kgdb_debug_init = 1; 329 1.1 matt kgdb_connect(1); 330 1.1 matt } 331 1.1 matt #endif 332 1.1 matt 333 1.1 matt #ifdef DDB 334 1.1 matt db_machine_init(); 335 1.1 matt ddb_init(0, NULL, NULL); 336 1.1 matt 337 1.1 matt if (boothowto & RB_KDB) 338 1.1 matt Debugger(); 339 1.1 matt #endif 340 1.1 matt 341 1.11 jmcneill #ifdef MULTIPROCESSOR 342 1.33 skrll /* 343 1.33 skrll * Ensure BP cache is flushed to memory so that APs start cache 344 1.33 skrll * coherency with correct view. 345 1.33 skrll */ 346 1.33 skrll cpu_dcache_wbinv_all(); 347 1.11 jmcneill #endif 348 1.11 jmcneill 349 1.20 skrll VPRINTF("done.\n"); 350 1.1 matt 351 1.1 matt /* We return the new stack pointer address */ 352 1.19 skrll return pcb->pcb_ksp; 353 1.1 matt } 354 1.1 matt 355 1.1 matt #ifdef MULTIPROCESSOR 356 1.1 matt /* 357 1.1 matt * When we are called, the MMU and caches are on and we are running on the stack 358 1.1 matt * of the idlelwp for this cpu. 359 1.1 matt */ 360 1.1 matt void 361 1.28 skrll cpu_hatch(struct cpu_info *ci, u_int cpuindex, void (*md_cpu_init)(struct cpu_info *)) 362 1.1 matt { 363 1.28 skrll KASSERT(cpu_index(ci) == cpuindex); 364 1.1 matt 365 1.1 matt /* 366 1.1 matt * Raise our IPL to the max 367 1.1 matt */ 368 1.1 matt splhigh(); 369 1.1 matt 370 1.28 skrll VPRINTF("%s(%s): ", __func__, cpu_name(ci)); 371 1.44 skrll /* mpidr/midr filled in by cpu_init_secondary_processor */ 372 1.29 jmcneill 373 1.1 matt /* 374 1.1 matt * Make sure we have the right vector page. 375 1.1 matt */ 376 1.20 skrll VPRINTF(" vectors"); 377 1.1 matt arm32_vector_init(systempage.pv_va, ARM_VEC_ALL); 378 1.1 matt 379 1.1 matt /* 380 1.7 matt * Initialize the stack for each mode (we are already running on the 381 1.7 matt * SVC32 stack of the idlelwp). 382 1.1 matt */ 383 1.20 skrll VPRINTF(" stacks"); 384 1.1 matt set_stackptr(PSR_FIQ32_MODE, 385 1.10 matt fiqstack.pv_va + (cpu_index(ci) + 1) * FIQ_STACK_SIZE * PAGE_SIZE); 386 1.1 matt set_stackptr(PSR_IRQ32_MODE, 387 1.10 matt irqstack.pv_va + (cpu_index(ci) + 1) * IRQ_STACK_SIZE * PAGE_SIZE); 388 1.1 matt set_stackptr(PSR_ABT32_MODE, 389 1.10 matt abtstack.pv_va + (cpu_index(ci) + 1) * ABT_STACK_SIZE * PAGE_SIZE); 390 1.1 matt set_stackptr(PSR_UND32_MODE, 391 1.10 matt undstack.pv_va + (cpu_index(ci) + 1) * UND_STACK_SIZE * PAGE_SIZE); 392 1.1 matt 393 1.6 matt ci->ci_lastlwp = NULL; 394 1.6 matt ci->ci_pmap_lastuser = NULL; 395 1.6 matt #ifdef ARM_MMU_EXTENDED 396 1.20 skrll VPRINTF(" tlb"); 397 1.1 matt /* 398 1.6 matt * Attach to the tlb. 399 1.1 matt */ 400 1.6 matt ci->ci_pmap_cur = pmap_kernel(); 401 1.6 matt ci->ci_pmap_asid_cur = KERNEL_PID; 402 1.1 matt #endif 403 1.6 matt 404 1.1 matt #ifdef CPU_CORTEX 405 1.1 matt if (CPU_ID_CORTEX_P(ci->ci_arm_cpuid)) { 406 1.1 matt /* 407 1.1 matt * Start and reset the PMC Cycle Counter. 408 1.17 skrll */ 409 1.1 matt armreg_pmcr_write(ARM11_PMCCTL_E|ARM11_PMCCTL_P|ARM11_PMCCTL_C); 410 1.45 ryo armreg_pmintenclr_write(PMINTEN_C | PMINTEN_P); 411 1.1 matt armreg_pmcntenset_write(CORTEX_CNTENS_C); 412 1.1 matt } 413 1.1 matt #endif 414 1.1 matt 415 1.24 skrll VPRINTF(" md(%p)", md_cpu_init); 416 1.24 skrll if (md_cpu_init != NULL) 417 1.24 skrll (*md_cpu_init)(ci); 418 1.24 skrll 419 1.20 skrll VPRINTF(" interrupts"); 420 1.1 matt /* 421 1.1 matt * Let the interrupts do what they need to on this CPU. 422 1.1 matt */ 423 1.1 matt intr_cpu_init(ci); 424 1.1 matt 425 1.24 skrll VPRINTF(" done!\n"); 426 1.37 skrll cpu_clr_mbox(cpuindex); 427 1.1 matt } 428 1.1 matt #endif /* MULTIPROCESSOR */ 429