| History log of /src/sys/arch/arm/arm32/arm32_boot.c |
| Revision | | Date | Author | Comments |
| 1.45 |
| 22-Dec-2022 |
ryo | Explicitly disable overflow interrupts before enabling the cycle counter.
|
| 1.44 |
| 31-Oct-2021 |
skrll | branches: 1.44.4;
Rework Arm (32bit and 64bit) AP startup so that cpu_hatch doesn't sleep.
The AP initialisation code in cpu_init_secondary_processor will read and
initialise the required system registers and state for the BP to attach
and report.
Rework the interrupt handler code for this new sequence. Thankfully,
this removes a bunch of code for bcm2836mp.
The VFP detection handler on <= armv7 relies on the global undefined
handler being in place until the BP attaches vfp. That is, after the
APs have been spun up.
gicv3_its.c has a serialisation issue which is protected against in
the gicv3_its_cpu_init, which is called from cpu_hatch, with a spin
lock. The serialisation issue needs addressing more completely.
Tested on RPI3, Apple M1, QEMU, and lx2k
Fixes PR port-arm/56264:
diagnostic assertion "l->l_stat == LSONPROC" failed on RPI3
|
| 1.43 |
| 03-Jun-2021 |
skrll | Mirror changes to passing pages to UVM into aarch64_machdep.c
Two fixes for loading free pages into UVM
- Only consider a boot_physmem (inner loop) range that has its end
(bp_end) after the bootconfig.dram (outer loop) range start (start).
This was harmless as a later condition correctly checks there is only
something to do if start < bp_end.
- Stop processing boot_physmem ranges if all the bootconfig.dram range has
been passed to UVM. This fixes a boot problem for simon@
Copy a comment over and do the VPRINTF before the uvm_page_physload in
the same way as aarch64_machdep.c as well.
|
| 1.42 |
| 01-Jun-2021 |
skrll | branches: 1.42.2;
G/C
|
| 1.41 |
| 01-Dec-2020 |
rin | branches: 1.41.4;
Switch earmv6{,hf}eb to BE8 in kernel side.
My strategy here is to define _ARM_ARCH_BE8 macro in arm/cdefs.h, if
__ARMEB__ && _ARM_ARCH_6.
Use this macro to determine whether system is compiled for and running on
BE8 mode or not.
Note that, for __ARMEB__, some conditions become compile-time constants
determined by _ARM_ARCH_BE8 macro, e.g., whether BE8 or BE32 are accepted
as a userland binary, or unaligned memory access is possible or not.
|
| 1.40 |
| 11-Sep-2020 |
skrll | branches: 1.40.2;
Wrap a long comment
|
| 1.39 |
| 10-Jul-2020 |
skrll | Add support for KASAN on ARMv[67]
Thanks to maxv for many pointers and reviews.
|
| 1.38 |
| 06-Jun-2020 |
skrll | KNF
|
| 1.37 |
| 15-Feb-2020 |
skrll | Various updates and improvements to cpu start up on arm/aarch64
- start sharing more code around the AP startup messaging.
- call arm_cpu_topology_set early so that ci_core_id is available for
drivers, e.g. bcm2835_intr.c
- both arm and aarch64 now have
- a static cpu_info_store array
- the same arm_cpu_{hatched,mbox}
|
| 1.36 |
| 08-Jan-2020 |
jmcneill | cpu_hatch is too late to report AP topology, do it at attach time instead
|
| 1.35 |
| 20-Dec-2019 |
ad | branches: 1.35.2;
Some more CPU topology stuff:
- Use cegger@'s ACPI SRAT parsing code to figure out NUMA node ID for each
CPU as it is attached.
- For scheduler experiments with SMT, flag CPUs with the lowest numbered SMT
IDs as "primaries", link back to the primaries from secondaries, and build
a circular list of CPUs in each package with identical SMT IDs.
- No need for package/core/smt/numa IDs to be anything other than a u_int.
|
| 1.34 |
| 02-Dec-2019 |
ad | Take the basic CPU topology information we already collect, and use it
to make circular lists of CPU siblings in the same core, and in the
same package. Nothing fancy, just enough to have a bit of fun in the
scheduler trying out different tactics.
|
| 1.33 |
| 16-Mar-2019 |
skrll | branches: 1.33.4;
Flush the BP cache just before starting APs so that cache coherency starts
with a correct view.
|
| 1.32 |
| 27-Jan-2019 |
pgoyette | Merge the [pgoyette-compat] branch
|
| 1.31 |
| 25-Jan-2019 |
skrll | Make sure ci_{smt,core,package}_id are all filled in appropriately.
Previously the BP was missed and __SHIFTOUT wasn't used.
|
| 1.30 |
| 03-Jan-2019 |
skrll | Simplify
|
| 1.29 |
| 03-Jan-2019 |
jmcneill | Read mpidr and cpuid from the secondary processor itself instead of the
boot processor. While here, add Cortex-A15 r4p0 to supported list.
|
| 1.28 |
| 03-Jan-2019 |
skrll | Start CPUs more like aarch64 by using a cpu_mpidr array (if populated)
to map MPIDRs to an index for each CPU.
Towards big.LITTLE support.
|
| 1.27 |
| 31-Oct-2018 |
skrll | Tidyup VERBOSE_INIT_ARM output
|
| 1.26 |
| 28-Oct-2018 |
skrll | Fix a commit
|
| 1.25 |
| 18-Oct-2018 |
skrll | Fix VPRINTF
|
| 1.24 |
| 18-Oct-2018 |
skrll | Provide generic start code that assumes the MMU is off and caches are
disabled as per the linux booting protocol for ARMv6 and ARMv7 boards.
u-boot image type should be changed to 'linux' for correct behaviour.
The new start code builds a minimal "bootstrap" L1PT with cached access
disabled and uses the same table for all processors. AP startup is
performed in less steps and more code is written in C.
The bootstrap tables and stack are placed into an (orphaned) section
"_init_memory" which is given to uvm when it is no longer used.
Various kernels have been converted to use this code and tested. Some
boards were provided by TNF. Thanks!
The GENERIC kernel now boots on boards using the TEGRA, SUNXI and EXYNOS
kernels. The GENERIC kernel will also work on RPI2 using u-boot.
Thanks to martin@ and aymeric@ for testing on parallella and nanosoc
respectively
|
| 1.23 |
| 14-Oct-2018 |
skrll | Use __nothing
|
| 1.22 |
| 16-Sep-2018 |
skrll | G/C
|
| 1.21 |
| 15-Aug-2018 |
skrll | Sprinkle #include "opt_cputypes.h"
|
| 1.20 |
| 31-Jul-2018 |
skrll | Define and use VPRINTF
|
| 1.19 |
| 02-Jul-2017 |
skrll | branches: 1.19.4; 1.19.6;
Consistency around the user trapframe for all LWPs and there's no need to
keep assigning it in kernel entry points.
|
| 1.18 |
| 22-Dec-2016 |
cherry | switch all ports to use uvm_init.c:uvm_md_init()
uvm_setpagesize() is now subsumed within this funciton.
|
| 1.17 |
| 08-Mar-2016 |
skrll | branches: 1.17.2;
#if 0 a KASSERT for now as it doesn't apply to Raspberry Pi 3
|
| 1.16 |
| 17-May-2015 |
matt | KASSERT in cpu_hatch that AUXCTL.SMP is set for Cortex CPUs.
|
| 1.15 |
| 04-May-2015 |
matt | Deal with 4GB overflow in arm32_kvminit.c
|
| 1.14 |
| 04-May-2015 |
matt | Fix 4GB wraparound math.
|
| 1.13 |
| 04-May-2015 |
matt | If not using LPAE, if memory ends at 4GB ignore the last page so physical_end
doesn't wrap to 0.
|
| 1.12 |
| 12-Jan-2015 |
jakllsch | use IPL_NONE for CPU attach message serialization mutex
|
| 1.11 |
| 13-Dec-2014 |
jmcneill | serialize printing of secondary cpu info
|
| 1.10 |
| 04-Nov-2014 |
matt | branches: 1.10.2;
Fix the stacks used by the other CPU to not overlap with the boot cpu's stacks.
|
| 1.9 |
| 29-Oct-2014 |
skrll | Sprinkle #include "opt_multiprocessor.h"
|
| 1.8 |
| 14-Sep-2014 |
ryo | add memory access barrier
|
| 1.7 |
| 28-Mar-2014 |
matt | branches: 1.7.4;
Various MP changes.
|
| 1.6 |
| 03-Mar-2014 |
matt | Further cpu_info inits in cpu_hatch
|
| 1.5 |
| 18-Aug-2013 |
matt | branches: 1.5.2;
Move parts of cpu.h that are not needed by MI code in <arm/locore.h>
Don't include <machine/cpu.h> or <machine/frame.h>, use <arm/locore.h>
Use <arm/asm.h> instead of <machine/arm.h>
|
| 1.4 |
| 12-Jun-2013 |
matt | branches: 1.4.2;
Add printfs around initializing the vector_page.
|
| 1.3 |
| 11-May-2013 |
skrll | Include opt_{ddb,kgdb} and fix KGDB build
|
| 1.2 |
| 17-Oct-2012 |
matt | branches: 1.2.2; 1.2.4;
Change the semantics of the boot_physmem array to select a freelist to use
with uvm_page_physload. Reduces duplication of work.
|
| 1.1 |
| 31-Aug-2012 |
matt | branches: 1.1.2;
Make cpu_reset, most of initarm and the kvm init code common.
Add MP hooks for cpu_need_resced
Add idlestck which is allocated in arm32_kvminit
|
| 1.1.2.4 |
| 03-Dec-2017 |
jdolecek | update from HEAD
|
| 1.1.2.3 |
| 20-Aug-2014 |
tls | Rebase to HEAD as of a few days ago.
|
| 1.1.2.2 |
| 23-Jun-2013 |
tls | resync from head
|
| 1.1.2.1 |
| 20-Nov-2012 |
tls | Resync to 2012-11-19 00:00:00 UTC
|
| 1.2.4.2 |
| 28-Nov-2012 |
matt | Merge improved arm support (especially Cortex) from HEAD
including OMAP and BCM53xx support.
|
| 1.2.4.1 |
| 17-Oct-2012 |
matt | file arm32_boot.c was added on branch matt-nb6-plus on 2012-11-28 22:40:16 +0000
|
| 1.2.2.3 |
| 22-May-2014 |
yamt | sync with head.
for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.
this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
|
| 1.2.2.2 |
| 30-Oct-2012 |
yamt | sync with head
|
| 1.2.2.1 |
| 17-Oct-2012 |
yamt | file arm32_boot.c was added on branch yamt-pagecache on 2012-10-30 17:18:56 +0000
|
| 1.4.2.2 |
| 18-May-2014 |
rmind | sync with head
|
| 1.4.2.1 |
| 28-Aug-2013 |
rmind | sync with head
|
| 1.5.2.3 |
| 24-Mar-2014 |
matt | Need to deal with proc0paddr.
|
| 1.5.2.2 |
| 15-Feb-2014 |
matt | Merge armv7 support from HEAD, specifically support for the BCM5301X
and BCM56340 evbarm kernels.
|
| 1.5.2.1 |
| 18-Aug-2013 |
matt | file arm32_boot.c was added on branch matt-nb5-mips64 on 2014-02-15 16:18:36 +0000
|
| 1.7.4.3 |
| 12-Jan-2015 |
snj | Pull up following revision(s) (requested by jmcneill in ticket #412):
sys/arch/arm/arm32/arm32_boot.c: revision 1.12
use IPL_NONE for CPU attach message serialization mutex
|
| 1.7.4.2 |
| 13-Dec-2014 |
martin | Pull up following revision(s) (requested by jmcneill in ticket #319):
sys/arch/arm/arm32/arm32_boot.c: revision 1.11
serialize printing of secondary cpu info
|
| 1.7.4.1 |
| 09-Nov-2014 |
martin | Pull up following revision(s) (requested by skrll in ticket #188):
sys/arch/arm/include/arm32/pmap.h: revision 1.136
sys/arch/arm/include/armreg.h: revision 1.100
sys/arch/arm/cortex/gic.c: revision 1.11
sys/arch/arm/arm32/db_interface.c: revision 1.54
sys/arch/arm/include/armreg.h: revision 1.101
sys/arch/arm/cortex/gic.c: revision 1.12
sys/arch/arm/arm32/arm32_machdep.c: revision 1.107
sys/arch/arm/arm/cpufunc_asm_armv7.S: revision 1.19
sys/arch/arm/cortex/a9_mpsubr.S: revision 1.20
sys/arch/evbarm/conf/BPI: revision 1.5
sys/arch/arm/cortex/a9_mpsubr.S: revision 1.21
sys/arch/arm/arm32/pmap.c: revision 1.306
sys/arch/arm/arm32/db_machdep.c: revision 1.22
sys/arch/arm/arm32/arm32_tlb.c: revision 1.3
sys/arch/arm/arm/undefined.c: revision 1.55
sys/arch/arm/cortex/a9_mpsubr.S: revision 1.22
sys/arch/arm/arm32/pmap.c: revision 1.307
sys/arch/arm/arm32/arm32_tlb.c: revision 1.4
sys/arch/arm/cortex/a9_mpsubr.S: revision 1.23
sys/arch/arm/arm32/arm32_tlb.c: revision 1.5
sys/arch/evbarm/conf/BPI: revision 1.8
sys/arch/arm/cortex/a9_mpsubr.S: revision 1.24
sys/arch/arm/arm32/arm32_tlb.c: revision 1.6
sys/arch/arm/arm32/arm32_tlb.c: revision 1.7
sys/arch/evbarm/conf/CUBIETRUCK: revision 1.5
sys/arch/arm/pic/pic.c: revision 1.23
sys/arch/arm/pic/pic.c: revision 1.24
sys/arch/arm/pic/picvar.h: revision 1.11
sys/arch/arm/arm/cpufunc_asm_armv7.S: revision 1.20
sys/arch/arm/mainbus/cpu_mainbus.c: revision 1.16
sys/arch/arm/arm32/pmap.c: revision 1.298
sys/arch/arm/arm/cpufunc_asm_arm11.S: revision 1.17
sys/arch/arm/arm/cpufunc_asm_pj4b.S: revision 1.5
sys/arch/arm/arm32/pmap.c: revision 1.310
sys/arch/arm/arm32/pmap.c: revision 1.311
sys/arch/arm/arm32/arm32_kvminit.c: revision 1.32
sys/arch/arm/cortex/a9_mpsubr.S: revision 1.19
sys/arch/arm/arm32/arm32_boot.c: revision 1.10
sys/arch/arm/arm/ast.c: revision 1.25
sys/arch/arm/include/armreg.h: revision 1.98
sys/uvm/pmap/pmap_tlb.c: revision 1.10
sys/arch/arm/arm32/arm32_boot.c: revision 1.8
sys/arch/arm/arm32/arm32_boot.c: revision 1.9
sys/arch/arm/arm/arm_machdep.c: revision 1.43
Various ARM MP fixes.
|
| 1.10.2.5 |
| 28-Aug-2017 |
skrll | Sync with HEAD
|
| 1.10.2.4 |
| 05-Feb-2017 |
skrll | Sync with HEAD
|
| 1.10.2.3 |
| 19-Mar-2016 |
skrll | Sync with HEAD
|
| 1.10.2.2 |
| 06-Jun-2015 |
skrll | Sync with HEAD
|
| 1.10.2.1 |
| 06-Apr-2015 |
skrll | Sync with HEAD
|
| 1.17.2.1 |
| 07-Jan-2017 |
pgoyette | Sync with HEAD. (Note that most of these changes are simply $NetBSD$
tag issues.)
|
| 1.19.6.2 |
| 08-Apr-2020 |
martin | Merge changes from current as of 20200406
|
| 1.19.6.1 |
| 10-Jun-2019 |
christos | Sync with HEAD
|
| 1.19.4.6 |
| 26-Jan-2019 |
pgoyette | Sync with HEAD
|
| 1.19.4.5 |
| 18-Jan-2019 |
pgoyette | Synch with HEAD
|
| 1.19.4.4 |
| 26-Nov-2018 |
pgoyette | Sync with HEAD, resolve a couple of conflicts
|
| 1.19.4.3 |
| 20-Oct-2018 |
pgoyette | Sync with head
|
| 1.19.4.2 |
| 30-Sep-2018 |
pgoyette | Ssync with HEAD
|
| 1.19.4.1 |
| 06-Sep-2018 |
pgoyette | Sync with HEAD
Resolve a couple of conflicts (result of the uimin/uimax changes)
|
| 1.33.4.1 |
| 05-Jun-2021 |
martin | Pull up following revision(s) (requested by skrll in ticket #1279):
sys/arch/arm/arm32/arm32_boot.c: revision 1.42
sys/arch/arm/arm32/arm32_boot.c: revision 1.43
G/C
-
Mirror the changes around passing pages to UVM in aarch64_machdep.c:
Two fixes for loading free pages into UVM
- Only consider a boot_physmem (inner loop) range that has its end
(bp_end) after the bootconfig.dram (outer loop) range start (start).
This was harmless as a later condition correctly checks there is only
something to do if start < bp_end.
- Stop processing boot_physmem ranges if all the bootconfig.dram range has
been passed to UVM. This fixes a boot problem for simon@
Copy a comment over and do the VPRINTF before the uvm_page_physload in
the same way as aarch64_machdep.c as well.
|
| 1.35.2.2 |
| 29-Feb-2020 |
ad | Sync with head.
|
| 1.35.2.1 |
| 17-Jan-2020 |
ad | Sync with head.
|
| 1.40.2.1 |
| 14-Dec-2020 |
thorpej | Sync w/ HEAD.
|
| 1.41.4.1 |
| 17-Jun-2021 |
thorpej | Sync w/ HEAD.
|
| 1.42.2.1 |
| 06-Jun-2021 |
cjep | sync with head
|
| 1.44.4.1 |
| 23-Dec-2022 |
martin | Pull up following revision(s) (requested by ryo in ticket #20):
sys/arch/arm/arm/cpufunc.c: revision 1.185
sys/dev/tprof/tprof.c: revision 1.22
sys/arch/arm/arm32/arm32_boot.c: revision 1.45
sys/dev/tprof/tprof_armv8.c: revision 1.19
sys/dev/tprof/tprof_armv7.c: revision 1.12
sys/arch/aarch64/aarch64/cpu.c: revision 1.71
sys/arch/aarch64/aarch64/cpu.c: revision 1.72
tprof_lock is not a spin mutex. use mutex_{enter,exit}(). oops
Explicitly disable overflow interrupts before enabling the cycle counter.
PMCR_EL0.LC should be set. ARM deprecates use of PMCR_EL0.LC=0
Even if an overflow interrupt is occured for a counter outside tprof management,
the bit of onverflow status register must be cleared to prevent an interrupt storm.
|
