arm32_boot.c revision 1.33.4.1
1 /* $NetBSD: arm32_boot.c,v 1.33.4.1 2021/06/05 10:27:10 martin Exp $ */ 2 3 /* 4 * Copyright (c) 2002, 2003, 2005 Genetec Corporation. All rights reserved. 5 * Written by Hiroyuki Bessho for Genetec Corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of Genetec Corporation may not be used to endorse or 16 * promote products derived from this software without specific prior 17 * written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 * 31 * Copyright (c) 2001 Wasabi Systems, Inc. 32 * All rights reserved. 33 * 34 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. All advertising materials mentioning features or use of this software 45 * must display the following acknowledgement: 46 * This product includes software developed for the NetBSD Project by 47 * Wasabi Systems, Inc. 48 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 49 * or promote products derived from this software without specific prior 50 * written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 53 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 54 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 55 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 56 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 57 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 58 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 59 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 60 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 61 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 62 * POSSIBILITY OF SUCH DAMAGE. 63 * 64 * Copyright (c) 1997,1998 Mark Brinicombe. 65 * Copyright (c) 1997,1998 Causality Limited. 66 * All rights reserved. 67 * 68 * Redistribution and use in source and binary forms, with or without 69 * modification, are permitted provided that the following conditions 70 * are met: 71 * 1. Redistributions of source code must retain the above copyright 72 * notice, this list of conditions and the following disclaimer. 73 * 2. Redistributions in binary form must reproduce the above copyright 74 * notice, this list of conditions and the following disclaimer in the 75 * documentation and/or other materials provided with the distribution. 76 * 3. All advertising materials mentioning features or use of this software 77 * must display the following acknowledgement: 78 * This product includes software developed by Mark Brinicombe 79 * for the NetBSD Project. 80 * 4. The name of the company nor the name of the author may be used to 81 * endorse or promote products derived from this software without specific 82 * prior written permission. 83 * 84 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 85 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 86 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 87 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 88 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 89 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 90 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 91 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 92 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 93 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 94 * SUCH DAMAGE. 95 * 96 * Copyright (c) 2007 Microsoft 97 * All rights reserved. 98 * 99 * Redistribution and use in source and binary forms, with or without 100 * modification, are permitted provided that the following conditions 101 * are met: 102 * 1. Redistributions of source code must retain the above copyright 103 * notice, this list of conditions and the following disclaimer. 104 * 2. Redistributions in binary form must reproduce the above copyright 105 * notice, this list of conditions and the following disclaimer in the 106 * documentation and/or other materials provided with the distribution. 107 * 3. All advertising materials mentioning features or use of this software 108 * must display the following acknowledgement: 109 * This product includes software developed by Microsoft 110 * 111 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 112 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 113 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 114 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTERS BE LIABLE FOR ANY DIRECT, 115 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 116 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 117 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 118 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 119 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 120 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 121 * SUCH DAMAGE. 122 */ 123 124 #include <sys/cdefs.h> 125 __KERNEL_RCSID(1, "$NetBSD: arm32_boot.c,v 1.33.4.1 2021/06/05 10:27:10 martin Exp $"); 126 127 #include "opt_arm_debug.h" 128 #include "opt_cputypes.h" 129 #include "opt_ddb.h" 130 #include "opt_kgdb.h" 131 #include "opt_multiprocessor.h" 132 133 #include <sys/param.h> 134 #include <sys/reboot.h> 135 #include <sys/cpu.h> 136 #include <sys/intr.h> 137 #include <sys/atomic.h> 138 #include <sys/device.h> 139 140 #include <uvm/uvm_extern.h> 141 142 #include <arm/locore.h> 143 #include <arm/undefined.h> 144 #include <arm/arm32/machdep.h> 145 146 #include <machine/db_machdep.h> 147 #include <ddb/db_extern.h> 148 149 #include <machine/bootconfig.h> 150 151 #ifdef KGDB 152 #include <sys/kgdb.h> 153 #endif 154 155 #ifdef VERBOSE_INIT_ARM 156 #define VPRINTF(...) printf(__VA_ARGS__) 157 #else 158 #define VPRINTF(...) __nothing 159 #endif 160 161 #ifdef MULTIPROCESSOR 162 static kmutex_t cpu_hatch_lock; 163 #endif 164 165 vaddr_t 166 initarm_common(vaddr_t kvm_base, vsize_t kvm_size, 167 const struct boot_physmem *bp, size_t nbp) 168 { 169 struct bootmem_info * const bmi = &bootmem_info; 170 171 VPRINTF("nfreeblocks = %u, free_pages = %d (%#x)\n", 172 bmi->bmi_nfreeblocks, bmi->bmi_freepages, 173 bmi->bmi_freepages); 174 175 /* 176 * Moved from cpu_startup() as data_abort_handler() references 177 * this during uvm init. 178 */ 179 uvm_lwp_setuarea(&lwp0, kernelstack.pv_va); 180 181 struct lwp * const l = &lwp0; 182 struct pcb * const pcb = lwp_getpcb(l); 183 184 /* Zero out the PCB. */ 185 memset(pcb, 0, sizeof(*pcb)); 186 187 pcb->pcb_ksp = uvm_lwp_getuarea(l) + USPACE_SVC_STACK_TOP; 188 pcb->pcb_ksp -= sizeof(struct trapframe); 189 190 struct trapframe * tf = (struct trapframe *)pcb->pcb_ksp; 191 192 /* Zero out the trapframe. */ 193 memset(tf, 0, sizeof(*tf)); 194 lwp_settrapframe(l, tf); 195 196 #if defined(__ARMEB__) 197 tf->tf_spsr = PSR_USR32_MODE | (CPU_IS_ARMV7_P() ? PSR_E_BIT : 0); 198 #else 199 tf->tf_spsr = PSR_USR32_MODE; 200 #endif 201 202 VPRINTF("bootstrap done.\n"); 203 204 VPRINTF("vectors"); 205 arm32_vector_init(systempage.pv_va, ARM_VEC_ALL); 206 VPRINTF(" %#"PRIxVADDR"\n", vector_page); 207 208 /* 209 * Pages were allocated during the secondary bootstrap for the 210 * stacks for different CPU modes. 211 * We must now set the r13 registers in the different CPU modes to 212 * point to these stacks. 213 * Since the ARM stacks use STMFD etc. we must set r13 to the top end 214 * of the stack memory. 215 */ 216 VPRINTF("init subsystems: stacks "); 217 set_stackptr(PSR_FIQ32_MODE, 218 fiqstack.pv_va + FIQ_STACK_SIZE * PAGE_SIZE); 219 set_stackptr(PSR_IRQ32_MODE, 220 irqstack.pv_va + IRQ_STACK_SIZE * PAGE_SIZE); 221 set_stackptr(PSR_ABT32_MODE, 222 abtstack.pv_va + ABT_STACK_SIZE * PAGE_SIZE); 223 set_stackptr(PSR_UND32_MODE, 224 undstack.pv_va + UND_STACK_SIZE * PAGE_SIZE); 225 226 /* 227 * Well we should set a data abort handler. 228 * Once things get going this will change as we will need a proper 229 * handler. 230 * Until then we will use a handler that just panics but tells us 231 * why. 232 * Initialisation of the vectors will just panic on a data abort. 233 * This just fills in a slightly better one. 234 */ 235 VPRINTF("vectors "); 236 data_abort_handler_address = (u_int)data_abort_handler; 237 prefetch_abort_handler_address = (u_int)prefetch_abort_handler; 238 undefined_handler_address = (u_int)undefinedinstruction_bounce; 239 240 /* Initialise the undefined instruction handlers */ 241 VPRINTF("undefined "); 242 undefined_init(); 243 244 /* Load memory into UVM. */ 245 VPRINTF("page "); 246 uvm_md_init(); 247 248 VPRINTF("pmap_physload\n"); 249 KASSERT(bp != NULL || nbp == 0); 250 KASSERT(bp == NULL || nbp != 0); 251 252 for (size_t i = 0; i < bmi->bmi_nfreeblocks; i++) { 253 pv_addr_t * const pv = &bmi->bmi_freeblocks[i]; 254 paddr_t start = atop(pv->pv_pa); 255 const paddr_t end = start + atop(pv->pv_size); 256 int vm_freelist = VM_FREELIST_DEFAULT; 257 258 VPRINTF("block %2zu start %08lx end %08lx", i, 259 pv->pv_pa, pv->pv_pa + pv->pv_size); 260 261 if (!bp) { 262 VPRINTF("... loading in freelist %d\n", vm_freelist); 263 uvm_page_physload(start, end, start, end, VM_FREELIST_DEFAULT); 264 continue; 265 } 266 VPRINTF("\n"); 267 268 /* 269 * This assumes the bp list is sorted in ascending 270 * order. 271 */ 272 paddr_t segend = end; 273 for (size_t j = 0; j < nbp && start < end; j++) { 274 paddr_t bp_start = bp[j].bp_start; 275 paddr_t bp_end = bp_start + bp[j].bp_pages; 276 277 VPRINTF(" bp %2zu start %08lx end %08lx\n", 278 j, ptoa(bp_start), ptoa(bp_end)); 279 280 KASSERT(bp_start < bp_end); 281 if (start >= bp_end || segend < bp_start) 282 continue; 283 284 if (start < bp_start) 285 start = bp_start; 286 287 if (start < bp_end) { 288 if (segend > bp_end) { 289 segend = bp_end; 290 } 291 vm_freelist = bp[j].bp_freelist; 292 293 VPRINTF(" start %08lx end %08lx" 294 "... loading in freelist %d\n", ptoa(start), 295 ptoa(segend), vm_freelist); 296 297 uvm_page_physload(start, segend, start, segend, 298 vm_freelist); 299 300 start = segend; 301 segend = end; 302 } 303 } 304 } 305 306 /* Boot strap pmap telling it where the managed kernel virtual memory is */ 307 VPRINTF("pmap "); 308 pmap_bootstrap(kvm_base, kvm_base + kvm_size); 309 310 #ifdef __HAVE_MEMORY_DISK__ 311 md_root_setconf(memory_disk, sizeof memory_disk); 312 #endif 313 314 #ifdef BOOTHOWTO 315 boothowto |= BOOTHOWTO; 316 #endif 317 318 #ifdef KGDB 319 if (boothowto & RB_KDB) { 320 kgdb_debug_init = 1; 321 kgdb_connect(1); 322 } 323 #endif 324 325 #ifdef DDB 326 db_machine_init(); 327 ddb_init(0, NULL, NULL); 328 329 if (boothowto & RB_KDB) 330 Debugger(); 331 #endif 332 333 #ifdef MULTIPROCESSOR 334 mutex_init(&cpu_hatch_lock, MUTEX_DEFAULT, IPL_NONE); 335 336 /* 337 * Ensure BP cache is flushed to memory so that APs start cache 338 * coherency with correct view. 339 */ 340 cpu_dcache_wbinv_all(); 341 #endif 342 343 VPRINTF("done.\n"); 344 345 /* We return the new stack pointer address */ 346 return pcb->pcb_ksp; 347 } 348 349 #ifdef MULTIPROCESSOR 350 /* 351 * When we are called, the MMU and caches are on and we are running on the stack 352 * of the idlelwp for this cpu. 353 */ 354 void 355 cpu_hatch(struct cpu_info *ci, u_int cpuindex, void (*md_cpu_init)(struct cpu_info *)) 356 { 357 KASSERT(cpu_index(ci) == cpuindex); 358 359 /* 360 * Raise our IPL to the max 361 */ 362 splhigh(); 363 364 VPRINTF("%s(%s): ", __func__, cpu_name(ci)); 365 ci->ci_ctrl = armreg_sctlr_read(); 366 uint32_t mpidr = armreg_mpidr_read(); 367 ci->ci_mpidr = mpidr; 368 if (mpidr & MPIDR_MT) { 369 ci->ci_smt_id = __SHIFTOUT(mpidr, MPIDR_AFF0); 370 ci->ci_core_id = __SHIFTOUT(mpidr, MPIDR_AFF1); 371 ci->ci_package_id = __SHIFTOUT(mpidr, MPIDR_AFF2); 372 } else { 373 ci->ci_core_id = __SHIFTOUT(mpidr, MPIDR_AFF0); 374 ci->ci_package_id = __SHIFTOUT(mpidr, MPIDR_AFF1); 375 } 376 377 ci->ci_arm_cpuid = cpu_idnum(); 378 ci->ci_arm_cputype = ci->ci_arm_cpuid & CPU_ID_CPU_MASK; 379 ci->ci_arm_cpurev = ci->ci_arm_cpuid & CPU_ID_REVISION_MASK; 380 381 /* 382 * Make sure we have the right vector page. 383 */ 384 VPRINTF(" vectors"); 385 arm32_vector_init(systempage.pv_va, ARM_VEC_ALL); 386 387 /* 388 * Initialize the stack for each mode (we are already running on the 389 * SVC32 stack of the idlelwp). 390 */ 391 VPRINTF(" stacks"); 392 set_stackptr(PSR_FIQ32_MODE, 393 fiqstack.pv_va + (cpu_index(ci) + 1) * FIQ_STACK_SIZE * PAGE_SIZE); 394 set_stackptr(PSR_IRQ32_MODE, 395 irqstack.pv_va + (cpu_index(ci) + 1) * IRQ_STACK_SIZE * PAGE_SIZE); 396 set_stackptr(PSR_ABT32_MODE, 397 abtstack.pv_va + (cpu_index(ci) + 1) * ABT_STACK_SIZE * PAGE_SIZE); 398 set_stackptr(PSR_UND32_MODE, 399 undstack.pv_va + (cpu_index(ci) + 1) * UND_STACK_SIZE * PAGE_SIZE); 400 401 ci->ci_lastlwp = NULL; 402 ci->ci_pmap_lastuser = NULL; 403 #ifdef ARM_MMU_EXTENDED 404 VPRINTF(" tlb"); 405 /* 406 * Attach to the tlb. 407 */ 408 ci->ci_pmap_cur = pmap_kernel(); 409 ci->ci_pmap_asid_cur = KERNEL_PID; 410 #endif 411 412 #ifdef CPU_CORTEX 413 if (CPU_ID_CORTEX_P(ci->ci_arm_cpuid)) { 414 /* 415 * Start and reset the PMC Cycle Counter. 416 */ 417 armreg_pmcr_write(ARM11_PMCCTL_E|ARM11_PMCCTL_P|ARM11_PMCCTL_C); 418 armreg_pmcntenset_write(CORTEX_CNTENS_C); 419 } 420 #endif 421 422 mutex_enter(&cpu_hatch_lock); 423 424 aprint_naive("%s", device_xname(ci->ci_dev)); 425 aprint_normal("%s", device_xname(ci->ci_dev)); 426 identify_arm_cpu(ci->ci_dev, ci); 427 VPRINTF(" vfp"); 428 vfp_attach(ci); 429 430 mutex_exit(&cpu_hatch_lock); 431 432 VPRINTF(" md(%p)", md_cpu_init); 433 if (md_cpu_init != NULL) 434 (*md_cpu_init)(ci); 435 436 VPRINTF(" interrupts"); 437 /* 438 * Let the interrupts do what they need to on this CPU. 439 */ 440 intr_cpu_init(ci); 441 442 VPRINTF(" done!\n"); 443 444 /* Notify cpu_boot_secondary_processors that we're done */ 445 atomic_and_32(&arm_cpu_mbox, ~__BIT(cpuindex)); 446 membar_producer(); 447 __asm __volatile("sev; sev; sev"); 448 } 449 #endif /* MULTIPROCESSOR */ 450
Indexes created Sun Oct 12 05:10:08 GMT 2025