cpu.c revision 1.106.2.7
1 /* $NetBSD: cpu.c,v 1.106.2.7 2017/08/28 17:51:29 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Mark Brinicombe. 5 * Copyright (c) 1995 Brini. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Brini. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * cpu.c 38 * 39 * Probing and configuration for the master CPU 40 * 41 * Created : 10/10/95 42 */ 43 44 #include "opt_armfpe.h" 45 #include "opt_multiprocessor.h" 46 47 #include <sys/param.h> 48 49 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.106.2.7 2017/08/28 17:51:29 skrll Exp $"); 50 51 #include <sys/systm.h> 52 #include <sys/conf.h> 53 #include <sys/cpu.h> 54 #include <sys/device.h> 55 #include <sys/kmem.h> 56 #include <sys/proc.h> 57 58 #include <uvm/uvm_extern.h> 59 60 #include <arm/locore.h> 61 #include <arm/undefined.h> 62 63 extern const char *cpu_arch; 64 65 #ifdef MULTIPROCESSOR 66 volatile u_int arm_cpu_hatched = 0; 67 volatile uint32_t arm_cpu_mbox __cacheline_aligned = 0; 68 uint32_t arm_cpu_marker[2] __cacheline_aligned = { 0, 0 }; 69 u_int arm_cpu_max = 1; 70 #endif 71 72 /* Prototypes */ 73 void identify_arm_cpu(device_t, struct cpu_info *); 74 void identify_cortex_caches(device_t); 75 void identify_features(device_t); 76 77 /* 78 * Identify the master (boot) CPU 79 */ 80 81 void 82 cpu_attach(device_t dv, cpuid_t id) 83 { 84 const char * const xname = device_xname(dv); 85 struct cpu_info *ci; 86 87 if (id == 0) { 88 ci = curcpu(); 89 90 /* Get the CPU ID from coprocessor 15 */ 91 92 ci->ci_arm_cpuid = cpu_idnum(); 93 ci->ci_arm_cputype = ci->ci_arm_cpuid & CPU_ID_CPU_MASK; 94 ci->ci_arm_cpurev = ci->ci_arm_cpuid & CPU_ID_REVISION_MASK; 95 } else { 96 #ifdef MULTIPROCESSOR 97 KASSERT(cpu_info[id] == NULL); 98 ci = kmem_zalloc(sizeof(*ci), KM_SLEEP); 99 ci->ci_cpl = IPL_HIGH; 100 ci->ci_cpuid = id; 101 uint32_t mpidr = armreg_mpidr_read(); 102 if (mpidr & MPIDR_MT) { 103 ci->ci_data.cpu_smt_id = mpidr & MPIDR_AFF0; 104 ci->ci_data.cpu_core_id = mpidr & MPIDR_AFF1; 105 ci->ci_data.cpu_package_id = mpidr & MPIDR_AFF2; 106 } else { 107 ci->ci_data.cpu_core_id = mpidr & MPIDR_AFF0; 108 ci->ci_data.cpu_package_id = mpidr & MPIDR_AFF1; 109 } 110 ci->ci_data.cpu_core_id = id; 111 ci->ci_data.cpu_cc_freq = cpu_info_store.ci_data.cpu_cc_freq; 112 ci->ci_arm_cpuid = cpu_info_store.ci_arm_cpuid; 113 ci->ci_arm_cputype = cpu_info_store.ci_arm_cputype; 114 ci->ci_arm_cpurev = cpu_info_store.ci_arm_cpurev; 115 ci->ci_ctrl = cpu_info_store.ci_ctrl; 116 ci->ci_undefsave[2] = cpu_info_store.ci_undefsave[2]; 117 cpu_info[ci->ci_cpuid] = ci; 118 if ((arm_cpu_hatched & (1 << id)) == 0) { 119 ci->ci_dev = dv; 120 dv->dv_private = ci; 121 aprint_naive(": disabled\n"); 122 aprint_normal(": disabled (unresponsive)\n"); 123 return; 124 } 125 #else 126 aprint_naive(": disabled\n"); 127 aprint_normal(": disabled (uniprocessor kernel)\n"); 128 return; 129 #endif 130 } 131 132 ci->ci_dev = dv; 133 dv->dv_private = ci; 134 135 evcnt_attach_dynamic(&ci->ci_arm700bugcount, EVCNT_TYPE_MISC, 136 NULL, xname, "arm700swibug"); 137 138 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_WRTBUF_0], EVCNT_TYPE_TRAP, 139 NULL, xname, "vector abort"); 140 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_WRTBUF_1], EVCNT_TYPE_TRAP, 141 NULL, xname, "terminal abort"); 142 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_BUSERR_0], EVCNT_TYPE_TRAP, 143 NULL, xname, "external linefetch abort (S)"); 144 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_BUSERR_1], EVCNT_TYPE_TRAP, 145 NULL, xname, "external linefetch abort (P)"); 146 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_BUSERR_2], EVCNT_TYPE_TRAP, 147 NULL, xname, "external non-linefetch abort (S)"); 148 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_BUSERR_3], EVCNT_TYPE_TRAP, 149 NULL, xname, "external non-linefetch abort (P)"); 150 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_BUSTRNL1], EVCNT_TYPE_TRAP, 151 NULL, xname, "external translation abort (L1)"); 152 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_BUSTRNL2], EVCNT_TYPE_TRAP, 153 NULL, xname, "external translation abort (L2)"); 154 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_ALIGN_0], EVCNT_TYPE_TRAP, 155 NULL, xname, "alignment abort (0)"); 156 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_ALIGN_1], EVCNT_TYPE_TRAP, 157 NULL, xname, "alignment abort (1)"); 158 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_TRANS_S], EVCNT_TYPE_TRAP, 159 NULL, xname, "translation abort (S)"); 160 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_TRANS_P], EVCNT_TYPE_TRAP, 161 NULL, xname, "translation abort (P)"); 162 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_DOMAIN_S], EVCNT_TYPE_TRAP, 163 NULL, xname, "domain abort (S)"); 164 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_DOMAIN_P], EVCNT_TYPE_TRAP, 165 NULL, xname, "domain abort (P)"); 166 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_PERM_S], EVCNT_TYPE_TRAP, 167 NULL, xname, "permission abort (S)"); 168 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_PERM_P], EVCNT_TYPE_TRAP, 169 NULL, xname, "permission abort (P)"); 170 evcnt_attach_dynamic_nozero(&ci->ci_und_ev, EVCNT_TYPE_TRAP, 171 NULL, xname, "undefined insn traps"); 172 evcnt_attach_dynamic_nozero(&ci->ci_und_cp15_ev, EVCNT_TYPE_TRAP, 173 NULL, xname, "undefined cp15 insn traps"); 174 175 #ifdef MULTIPROCESSOR 176 /* 177 * and we are done if this is a secondary processor. 178 */ 179 if (id != 0) { 180 #if 1 181 aprint_naive("\n"); 182 aprint_normal("\n"); 183 #else 184 aprint_naive(": %s\n", cpu_getmodel()); 185 aprint_normal(": %s\n", cpu_getmodel()); 186 #endif 187 mi_cpu_attach(ci); 188 #ifdef ARM_MMU_EXTENDED 189 pmap_tlb_info_attach(&pmap_tlb0_info, ci); 190 #endif 191 return; 192 } 193 #endif 194 195 identify_arm_cpu(dv, ci); 196 197 #ifdef CPU_STRONGARM 198 if (ci->ci_arm_cputype == CPU_ID_SA110 && 199 ci->ci_arm_cpurev < 3) { 200 aprint_normal_dev(dv, "SA-110 with bugged STM^ instruction\n"); 201 } 202 #endif 203 204 #ifdef CPU_ARM8 205 if ((ci->ci_arm_cpuid & CPU_ID_CPU_MASK) == CPU_ID_ARM810) { 206 int clock = arm8_clock_config(0, 0); 207 char *fclk; 208 aprint_normal_dev(dv, "ARM810 cp15=%02x", clock); 209 aprint_normal(" clock:%s", (clock & 1) ? " dynamic" : ""); 210 aprint_normal("%s", (clock & 2) ? " sync" : ""); 211 switch ((clock >> 2) & 3) { 212 case 0: 213 fclk = "bus clock"; 214 break; 215 case 1: 216 fclk = "ref clock"; 217 break; 218 case 3: 219 fclk = "pll"; 220 break; 221 default: 222 fclk = "illegal"; 223 break; 224 } 225 aprint_normal(" fclk source=%s\n", fclk); 226 } 227 #endif 228 229 vfp_attach(ci); /* XXX SMP */ 230 } 231 232 enum cpu_class { 233 CPU_CLASS_NONE, 234 CPU_CLASS_ARM2, 235 CPU_CLASS_ARM2AS, 236 CPU_CLASS_ARM3, 237 CPU_CLASS_ARM6, 238 CPU_CLASS_ARM7, 239 CPU_CLASS_ARM7TDMI, 240 CPU_CLASS_ARM8, 241 CPU_CLASS_ARM9TDMI, 242 CPU_CLASS_ARM9ES, 243 CPU_CLASS_ARM9EJS, 244 CPU_CLASS_ARM10E, 245 CPU_CLASS_ARM10EJ, 246 CPU_CLASS_SA1, 247 CPU_CLASS_XSCALE, 248 CPU_CLASS_ARM11J, 249 CPU_CLASS_ARMV4, 250 CPU_CLASS_CORTEX, 251 CPU_CLASS_PJ4B, 252 }; 253 254 static const char * const generic_steppings[16] = { 255 "rev 0", "rev 1", "rev 2", "rev 3", 256 "rev 4", "rev 5", "rev 6", "rev 7", 257 "rev 8", "rev 9", "rev 10", "rev 11", 258 "rev 12", "rev 13", "rev 14", "rev 15", 259 }; 260 261 static const char * const pN_steppings[16] = { 262 "*p0", "*p1", "*p2", "*p3", "*p4", "*p5", "*p6", "*p7", 263 "*p8", "*p9", "*p10", "*p11", "*p12", "*p13", "*p14", "*p15", 264 }; 265 266 static const char * const sa110_steppings[16] = { 267 "rev 0", "step J", "step K", "step S", 268 "step T", "rev 5", "rev 6", "rev 7", 269 "rev 8", "rev 9", "rev 10", "rev 11", 270 "rev 12", "rev 13", "rev 14", "rev 15", 271 }; 272 273 static const char * const sa1100_steppings[16] = { 274 "rev 0", "step B", "step C", "rev 3", 275 "rev 4", "rev 5", "rev 6", "rev 7", 276 "step D", "step E", "rev 10" "step G", 277 "rev 12", "rev 13", "rev 14", "rev 15", 278 }; 279 280 static const char * const sa1110_steppings[16] = { 281 "step A-0", "rev 1", "rev 2", "rev 3", 282 "step B-0", "step B-1", "step B-2", "step B-3", 283 "step B-4", "step B-5", "rev 10", "rev 11", 284 "rev 12", "rev 13", "rev 14", "rev 15", 285 }; 286 287 static const char * const ixp12x0_steppings[16] = { 288 "(IXP1200 step A)", "(IXP1200 step B)", 289 "rev 2", "(IXP1200 step C)", 290 "(IXP1200 step D)", "(IXP1240/1250 step A)", 291 "(IXP1240 step B)", "(IXP1250 step B)", 292 "rev 8", "rev 9", "rev 10", "rev 11", 293 "rev 12", "rev 13", "rev 14", "rev 15", 294 }; 295 296 static const char * const xscale_steppings[16] = { 297 "step A-0", "step A-1", "step B-0", "step C-0", 298 "step D-0", "rev 5", "rev 6", "rev 7", 299 "rev 8", "rev 9", "rev 10", "rev 11", 300 "rev 12", "rev 13", "rev 14", "rev 15", 301 }; 302 303 static const char * const i80321_steppings[16] = { 304 "step A-0", "step B-0", "rev 2", "rev 3", 305 "rev 4", "rev 5", "rev 6", "rev 7", 306 "rev 8", "rev 9", "rev 10", "rev 11", 307 "rev 12", "rev 13", "rev 14", "rev 15", 308 }; 309 310 static const char * const i80219_steppings[16] = { 311 "step A-0", "rev 1", "rev 2", "rev 3", 312 "rev 4", "rev 5", "rev 6", "rev 7", 313 "rev 8", "rev 9", "rev 10", "rev 11", 314 "rev 12", "rev 13", "rev 14", "rev 15", 315 }; 316 317 /* Steppings for PXA2[15]0 */ 318 static const char * const pxa2x0_steppings[16] = { 319 "step A-0", "step A-1", "step B-0", "step B-1", 320 "step B-2", "step C-0", "rev 6", "rev 7", 321 "rev 8", "rev 9", "rev 10", "rev 11", 322 "rev 12", "rev 13", "rev 14", "rev 15", 323 }; 324 325 /* Steppings for PXA255/26x. 326 * rev 5: PXA26x B0, rev 6: PXA255 A0 327 */ 328 static const char * const pxa255_steppings[16] = { 329 "rev 0", "rev 1", "rev 2", "step A-0", 330 "rev 4", "step B-0", "step A-0", "rev 7", 331 "rev 8", "rev 9", "rev 10", "rev 11", 332 "rev 12", "rev 13", "rev 14", "rev 15", 333 }; 334 335 /* Stepping for PXA27x */ 336 static const char * const pxa27x_steppings[16] = { 337 "step A-0", "step A-1", "step B-0", "step B-1", 338 "step C-0", "rev 5", "rev 6", "rev 7", 339 "rev 8", "rev 9", "rev 10", "rev 11", 340 "rev 12", "rev 13", "rev 14", "rev 15", 341 }; 342 343 static const char * const ixp425_steppings[16] = { 344 "step 0", "rev 1", "rev 2", "rev 3", 345 "rev 4", "rev 5", "rev 6", "rev 7", 346 "rev 8", "rev 9", "rev 10", "rev 11", 347 "rev 12", "rev 13", "rev 14", "rev 15", 348 }; 349 350 struct cpuidtab { 351 uint32_t cpuid; 352 enum cpu_class cpu_class; 353 const char *cpu_classname; 354 const char * const *cpu_steppings; 355 char cpu_arch[8]; 356 }; 357 358 const struct cpuidtab cpuids[] = { 359 { CPU_ID_ARM2, CPU_CLASS_ARM2, "ARM2", 360 generic_steppings, "2" }, 361 { CPU_ID_ARM250, CPU_CLASS_ARM2AS, "ARM250", 362 generic_steppings, "2" }, 363 364 { CPU_ID_ARM3, CPU_CLASS_ARM3, "ARM3", 365 generic_steppings, "2A" }, 366 367 { CPU_ID_ARM600, CPU_CLASS_ARM6, "ARM600", 368 generic_steppings, "3" }, 369 { CPU_ID_ARM610, CPU_CLASS_ARM6, "ARM610", 370 generic_steppings, "3" }, 371 { CPU_ID_ARM620, CPU_CLASS_ARM6, "ARM620", 372 generic_steppings, "3" }, 373 374 { CPU_ID_ARM700, CPU_CLASS_ARM7, "ARM700", 375 generic_steppings, "3" }, 376 { CPU_ID_ARM710, CPU_CLASS_ARM7, "ARM710", 377 generic_steppings, "3" }, 378 { CPU_ID_ARM7500, CPU_CLASS_ARM7, "ARM7500", 379 generic_steppings, "3" }, 380 { CPU_ID_ARM710A, CPU_CLASS_ARM7, "ARM710a", 381 generic_steppings, "3" }, 382 { CPU_ID_ARM7500FE, CPU_CLASS_ARM7, "ARM7500FE", 383 generic_steppings, "3" }, 384 385 { CPU_ID_ARM810, CPU_CLASS_ARM8, "ARM810", 386 generic_steppings, "4" }, 387 388 { CPU_ID_SA110, CPU_CLASS_SA1, "SA-110", 389 sa110_steppings, "4" }, 390 { CPU_ID_SA1100, CPU_CLASS_SA1, "SA-1100", 391 sa1100_steppings, "4" }, 392 { CPU_ID_SA1110, CPU_CLASS_SA1, "SA-1110", 393 sa1110_steppings, "4" }, 394 395 { CPU_ID_FA526, CPU_CLASS_ARMV4, "FA526", 396 generic_steppings, "4" }, 397 398 { CPU_ID_IXP1200, CPU_CLASS_SA1, "IXP1200", 399 ixp12x0_steppings, "4" }, 400 401 { CPU_ID_ARM710T, CPU_CLASS_ARM7TDMI, "ARM710T", 402 generic_steppings, "4T" }, 403 { CPU_ID_ARM720T, CPU_CLASS_ARM7TDMI, "ARM720T", 404 generic_steppings, "4T" }, 405 { CPU_ID_ARM740T8K, CPU_CLASS_ARM7TDMI, "ARM740T (8 KB cache)", 406 generic_steppings, "4T" }, 407 { CPU_ID_ARM740T4K, CPU_CLASS_ARM7TDMI, "ARM740T (4 KB cache)", 408 generic_steppings, "4T" }, 409 { CPU_ID_ARM920T, CPU_CLASS_ARM9TDMI, "ARM920T", 410 generic_steppings, "4T" }, 411 { CPU_ID_ARM922T, CPU_CLASS_ARM9TDMI, "ARM922T", 412 generic_steppings, "4T" }, 413 { CPU_ID_ARM940T, CPU_CLASS_ARM9TDMI, "ARM940T", 414 generic_steppings, "4T" }, 415 { CPU_ID_TI925T, CPU_CLASS_ARM9TDMI, "TI ARM925T", 416 generic_steppings, "4T" }, 417 418 { CPU_ID_ARM946ES, CPU_CLASS_ARM9ES, "ARM946E-S", 419 generic_steppings, "5TE" }, 420 { CPU_ID_ARM966ES, CPU_CLASS_ARM9ES, "ARM966E-S", 421 generic_steppings, "5TE" }, 422 { CPU_ID_ARM966ESR1, CPU_CLASS_ARM9ES, "ARM966E-S", 423 generic_steppings, "5TE" }, 424 { CPU_ID_MV88SV131, CPU_CLASS_ARM9ES, "Sheeva 88SV131", 425 generic_steppings, "5TE" }, 426 { CPU_ID_MV88FR571_VD, CPU_CLASS_ARM9ES, "Sheeva 88FR571-vd", 427 generic_steppings, "5TE" }, 428 429 { CPU_ID_80200, CPU_CLASS_XSCALE, "i80200", 430 xscale_steppings, "5TE" }, 431 432 { CPU_ID_80321_400, CPU_CLASS_XSCALE, "i80321 400MHz", 433 i80321_steppings, "5TE" }, 434 { CPU_ID_80321_600, CPU_CLASS_XSCALE, "i80321 600MHz", 435 i80321_steppings, "5TE" }, 436 { CPU_ID_80321_400_B0, CPU_CLASS_XSCALE, "i80321 400MHz", 437 i80321_steppings, "5TE" }, 438 { CPU_ID_80321_600_B0, CPU_CLASS_XSCALE, "i80321 600MHz", 439 i80321_steppings, "5TE" }, 440 441 { CPU_ID_80219_400, CPU_CLASS_XSCALE, "i80219 400MHz", 442 i80219_steppings, "5TE" }, 443 { CPU_ID_80219_600, CPU_CLASS_XSCALE, "i80219 600MHz", 444 i80219_steppings, "5TE" }, 445 446 { CPU_ID_PXA27X, CPU_CLASS_XSCALE, "PXA27x", 447 pxa27x_steppings, "5TE" }, 448 { CPU_ID_PXA250A, CPU_CLASS_XSCALE, "PXA250", 449 pxa2x0_steppings, "5TE" }, 450 { CPU_ID_PXA210A, CPU_CLASS_XSCALE, "PXA210", 451 pxa2x0_steppings, "5TE" }, 452 { CPU_ID_PXA250B, CPU_CLASS_XSCALE, "PXA250", 453 pxa2x0_steppings, "5TE" }, 454 { CPU_ID_PXA210B, CPU_CLASS_XSCALE, "PXA210", 455 pxa2x0_steppings, "5TE" }, 456 { CPU_ID_PXA250C, CPU_CLASS_XSCALE, "PXA255/26x", 457 pxa255_steppings, "5TE" }, 458 { CPU_ID_PXA210C, CPU_CLASS_XSCALE, "PXA210", 459 pxa2x0_steppings, "5TE" }, 460 461 { CPU_ID_IXP425_533, CPU_CLASS_XSCALE, "IXP425 533MHz", 462 ixp425_steppings, "5TE" }, 463 { CPU_ID_IXP425_400, CPU_CLASS_XSCALE, "IXP425 400MHz", 464 ixp425_steppings, "5TE" }, 465 { CPU_ID_IXP425_266, CPU_CLASS_XSCALE, "IXP425 266MHz", 466 ixp425_steppings, "5TE" }, 467 468 { CPU_ID_ARM1020E, CPU_CLASS_ARM10E, "ARM1020E", 469 generic_steppings, "5TE" }, 470 { CPU_ID_ARM1022ES, CPU_CLASS_ARM10E, "ARM1022E-S", 471 generic_steppings, "5TE" }, 472 473 { CPU_ID_ARM1026EJS, CPU_CLASS_ARM10EJ, "ARM1026EJ-S", 474 generic_steppings, "5TEJ" }, 475 { CPU_ID_ARM926EJS, CPU_CLASS_ARM9EJS, "ARM926EJ-S", 476 generic_steppings, "5TEJ" }, 477 478 { CPU_ID_ARM1136JS, CPU_CLASS_ARM11J, "ARM1136J-S r0", 479 pN_steppings, "6J" }, 480 { CPU_ID_ARM1136JSR1, CPU_CLASS_ARM11J, "ARM1136J-S r1", 481 pN_steppings, "6J" }, 482 #if 0 483 /* The ARM1156T2-S only has a memory protection unit */ 484 { CPU_ID_ARM1156T2S, CPU_CLASS_ARM11J, "ARM1156T2-S r0", 485 pN_steppings, "6T2" }, 486 #endif 487 { CPU_ID_ARM1176JZS, CPU_CLASS_ARM11J, "ARM1176JZ-S r0", 488 pN_steppings, "6ZK" }, 489 490 { CPU_ID_ARM11MPCORE, CPU_CLASS_ARM11J, "ARM11 MPCore", 491 generic_steppings, "6K" }, 492 493 { CPU_ID_CORTEXA5R0, CPU_CLASS_CORTEX, "Cortex-A5 r0", 494 pN_steppings, "7A" }, 495 { CPU_ID_CORTEXA7R0, CPU_CLASS_CORTEX, "Cortex-A7 r0", 496 pN_steppings, "7A" }, 497 { CPU_ID_CORTEXA8R1, CPU_CLASS_CORTEX, "Cortex-A8 r1", 498 pN_steppings, "7A" }, 499 { CPU_ID_CORTEXA8R2, CPU_CLASS_CORTEX, "Cortex-A8 r2", 500 pN_steppings, "7A" }, 501 { CPU_ID_CORTEXA8R3, CPU_CLASS_CORTEX, "Cortex-A8 r3", 502 pN_steppings, "7A" }, 503 { CPU_ID_CORTEXA9R1, CPU_CLASS_CORTEX, "Cortex-A9 r1", 504 pN_steppings, "7A" }, 505 { CPU_ID_CORTEXA9R2, CPU_CLASS_CORTEX, "Cortex-A9 r2", 506 pN_steppings, "7A" }, 507 { CPU_ID_CORTEXA9R3, CPU_CLASS_CORTEX, "Cortex-A9 r3", 508 pN_steppings, "7A" }, 509 { CPU_ID_CORTEXA9R4, CPU_CLASS_CORTEX, "Cortex-A9 r4", 510 pN_steppings, "7A" }, 511 { CPU_ID_CORTEXA15R2, CPU_CLASS_CORTEX, "Cortex-A15 r2", 512 pN_steppings, "7A" }, 513 { CPU_ID_CORTEXA15R3, CPU_CLASS_CORTEX, "Cortex-A15 r3", 514 pN_steppings, "7A" }, 515 { CPU_ID_CORTEXA17R1, CPU_CLASS_CORTEX, "Cortex-A17 r1", 516 pN_steppings, "7A" }, 517 { CPU_ID_CORTEXA53R0, CPU_CLASS_CORTEX, "Cortex-A53 r0", 518 pN_steppings, "8A" }, 519 { CPU_ID_CORTEXA57R0, CPU_CLASS_CORTEX, "Cortex-A57 r0", 520 pN_steppings, "8A" }, 521 { CPU_ID_CORTEXA57R1, CPU_CLASS_CORTEX, "Cortex-A57 r1", 522 pN_steppings, "8A" }, 523 { CPU_ID_CORTEXA72R0, CPU_CLASS_CORTEX, "Cortex-A72 r0", 524 pN_steppings, "8A" }, 525 526 { CPU_ID_MV88SV581X_V6, CPU_CLASS_PJ4B, "Sheeva 88SV581x", 527 generic_steppings }, 528 { CPU_ID_ARM_88SV581X_V6, CPU_CLASS_PJ4B, "Sheeva 88SV581x", 529 generic_steppings }, 530 { CPU_ID_MV88SV581X_V7, CPU_CLASS_PJ4B, "Sheeva 88SV581x", 531 generic_steppings }, 532 { CPU_ID_ARM_88SV581X_V7, CPU_CLASS_PJ4B, "Sheeva 88SV581x", 533 generic_steppings }, 534 { CPU_ID_MV88SV584X_V6, CPU_CLASS_PJ4B, "Sheeva 88SV584x", 535 generic_steppings }, 536 { CPU_ID_ARM_88SV584X_V6, CPU_CLASS_PJ4B, "Sheeva 88SV584x", 537 generic_steppings }, 538 { CPU_ID_MV88SV584X_V7, CPU_CLASS_PJ4B, "Sheeva 88SV584x", 539 generic_steppings }, 540 541 542 { 0, CPU_CLASS_NONE, NULL, NULL, "" } 543 }; 544 545 struct cpu_classtab { 546 const char *class_name; 547 const char *class_option; 548 }; 549 550 const struct cpu_classtab cpu_classes[] = { 551 [CPU_CLASS_NONE] = { "unknown", NULL }, 552 [CPU_CLASS_ARM2] = { "ARM2", "CPU_ARM2" }, 553 [CPU_CLASS_ARM2AS] = { "ARM2as", "CPU_ARM250" }, 554 [CPU_CLASS_ARM3] = { "ARM3", "CPU_ARM3" }, 555 [CPU_CLASS_ARM6] = { "ARM6", "CPU_ARM6" }, 556 [CPU_CLASS_ARM7] = { "ARM7", "CPU_ARM7" }, 557 [CPU_CLASS_ARM7TDMI] = { "ARM7TDMI", "CPU_ARM7TDMI" }, 558 [CPU_CLASS_ARM8] = { "ARM8", "CPU_ARM8" }, 559 [CPU_CLASS_ARM9TDMI] = { "ARM9TDMI", NULL }, 560 [CPU_CLASS_ARM9ES] = { "ARM9E-S", "CPU_ARM9E" }, 561 [CPU_CLASS_ARM9EJS] = { "ARM9EJ-S", "CPU_ARM9E" }, 562 [CPU_CLASS_ARM10E] = { "ARM10E", "CPU_ARM10" }, 563 [CPU_CLASS_ARM10EJ] = { "ARM10EJ", "CPU_ARM10" }, 564 [CPU_CLASS_SA1] = { "SA-1", "CPU_SA110" }, 565 [CPU_CLASS_XSCALE] = { "XScale", "CPU_XSCALE_..." }, 566 [CPU_CLASS_ARM11J] = { "ARM11J", "CPU_ARM11" }, 567 [CPU_CLASS_ARMV4] = { "ARMv4", "CPU_ARMV4" }, 568 [CPU_CLASS_CORTEX] = { "Cortex", "CPU_CORTEX" }, 569 [CPU_CLASS_PJ4B] = { "Marvell", "CPU_PJ4B" }, 570 }; 571 572 /* 573 * Report the type of the specified arm processor. This uses the generic and 574 * arm specific information in the CPU structure to identify the processor. 575 * The remaining fields in the CPU structure are filled in appropriately. 576 */ 577 578 static const char * const wtnames[] = { 579 "write-through", 580 "write-back", 581 "write-back", 582 "**unknown 3**", 583 "**unknown 4**", 584 "write-back-locking", /* XXX XScale-specific? */ 585 "write-back-locking-A", 586 "write-back-locking-B", 587 "**unknown 8**", 588 "**unknown 9**", 589 "**unknown 10**", 590 "**unknown 11**", 591 "write-back", 592 "write-back-locking-line", 593 "write-back-locking-C", 594 "write-back-locking-D", 595 }; 596 597 static void 598 print_cache_info(device_t dv, struct arm_cache_info *info, u_int level) 599 { 600 if (info->cache_unified) { 601 aprint_normal_dev(dv, "%dKB/%dB %d-way %s L%u %cI%cT Unified cache\n", 602 info->dcache_size / 1024, 603 info->dcache_line_size, info->dcache_ways, 604 wtnames[info->cache_type], level + 1, 605 info->dcache_type & CACHE_TYPE_PIxx ? 'P' : 'V', 606 info->dcache_type & CACHE_TYPE_xxPT ? 'P' : 'V'); 607 } else { 608 aprint_normal_dev(dv, "%dKB/%dB %d-way L%u %cI%cT Instruction cache\n", 609 info->icache_size / 1024, 610 info->icache_line_size, info->icache_ways, level + 1, 611 info->icache_type & CACHE_TYPE_PIxx ? 'P' : 'V', 612 info->icache_type & CACHE_TYPE_xxPT ? 'P' : 'V'); 613 aprint_normal_dev(dv, "%dKB/%dB %d-way %s L%u %cI%cT Data cache\n", 614 info->dcache_size / 1024, 615 info->dcache_line_size, info->dcache_ways, 616 wtnames[info->cache_type], level + 1, 617 info->dcache_type & CACHE_TYPE_PIxx ? 'P' : 'V', 618 info->dcache_type & CACHE_TYPE_xxPT ? 'P' : 'V'); 619 } 620 } 621 622 static enum cpu_class 623 identify_arm_model(uint32_t cpuid, char *buf, size_t len) 624 { 625 enum cpu_class cpu_class = CPU_CLASS_NONE; 626 for (const struct cpuidtab *id = cpuids; id->cpuid != 0; id++) { 627 if (id->cpuid == (cpuid & CPU_ID_CPU_MASK)) { 628 const char *steppingstr = 629 id->cpu_steppings[cpuid & CPU_ID_REVISION_MASK]; 630 cpu_arch = id->cpu_arch; 631 cpu_class = id->cpu_class; 632 snprintf(buf, len, "%s%s%s (%s V%s core)", 633 id->cpu_classname, 634 steppingstr[0] == '*' ? "" : " ", 635 &steppingstr[steppingstr[0] == '*'], 636 cpu_classes[cpu_class].class_name, 637 cpu_arch); 638 return cpu_class; 639 } 640 } 641 642 snprintf(buf, len, "unknown CPU (ID = 0x%x)", cpuid); 643 return cpu_class; 644 } 645 646 void 647 identify_arm_cpu(device_t dv, struct cpu_info *ci) 648 { 649 const uint32_t arm_cpuid = ci->ci_arm_cpuid; 650 const char * const xname = device_xname(dv); 651 char model[128]; 652 653 if (arm_cpuid == 0) { 654 aprint_error("Processor failed probe - no CPU ID\n"); 655 return; 656 } 657 658 const enum cpu_class cpu_class = identify_arm_model(arm_cpuid, 659 model, sizeof(model)); 660 if (ci->ci_cpuid == 0) { 661 cpu_setmodel("%s", model); 662 } 663 664 if (ci->ci_data.cpu_cc_freq != 0) { 665 char freqbuf[10]; 666 humanize_number(freqbuf, sizeof(freqbuf), ci->ci_data.cpu_cc_freq, 667 "Hz", 1000); 668 669 aprint_naive(": %s %s\n", freqbuf, model); 670 aprint_normal(": %s %s\n", freqbuf, model); 671 } else { 672 aprint_naive(": %s\n", model); 673 aprint_normal(": %s\n", model); 674 } 675 676 aprint_normal("%s:", xname); 677 678 switch (cpu_class) { 679 case CPU_CLASS_ARM6: 680 case CPU_CLASS_ARM7: 681 case CPU_CLASS_ARM7TDMI: 682 case CPU_CLASS_ARM8: 683 if ((ci->ci_ctrl & CPU_CONTROL_IDC_ENABLE) == 0) 684 aprint_normal(" IDC disabled"); 685 else 686 aprint_normal(" IDC enabled"); 687 break; 688 case CPU_CLASS_ARM9TDMI: 689 case CPU_CLASS_ARM9ES: 690 case CPU_CLASS_ARM9EJS: 691 case CPU_CLASS_ARM10E: 692 case CPU_CLASS_ARM10EJ: 693 case CPU_CLASS_SA1: 694 case CPU_CLASS_XSCALE: 695 case CPU_CLASS_ARM11J: 696 case CPU_CLASS_ARMV4: 697 case CPU_CLASS_CORTEX: 698 case CPU_CLASS_PJ4B: 699 if ((ci->ci_ctrl & CPU_CONTROL_DC_ENABLE) == 0) 700 aprint_normal(" DC disabled"); 701 else 702 aprint_normal(" DC enabled"); 703 if ((ci->ci_ctrl & CPU_CONTROL_IC_ENABLE) == 0) 704 aprint_normal(" IC disabled"); 705 else 706 aprint_normal(" IC enabled"); 707 break; 708 default: 709 break; 710 } 711 if ((ci->ci_ctrl & CPU_CONTROL_WBUF_ENABLE) == 0) 712 aprint_normal(" WB disabled"); 713 else 714 aprint_normal(" WB enabled"); 715 716 if (ci->ci_ctrl & CPU_CONTROL_LABT_ENABLE) 717 aprint_normal(" LABT"); 718 else 719 aprint_normal(" EABT"); 720 721 if (ci->ci_ctrl & CPU_CONTROL_BPRD_ENABLE) 722 aprint_normal(" branch prediction enabled"); 723 724 aprint_normal("\n"); 725 726 if (CPU_ID_CORTEX_P(arm_cpuid) || CPU_ID_ARM11_P(arm_cpuid) || CPU_ID_MV88SV58XX_P(arm_cpuid)) { 727 identify_features(dv); 728 } 729 730 /* Print cache info. */ 731 if (arm_pcache.icache_line_size != 0 || arm_pcache.dcache_line_size != 0) { 732 print_cache_info(dv, &arm_pcache, 0); 733 } 734 if (arm_scache.icache_line_size != 0 || arm_scache.dcache_line_size != 0) { 735 print_cache_info(dv, &arm_scache, 1); 736 } 737 738 739 switch (cpu_class) { 740 #ifdef CPU_ARM2 741 case CPU_CLASS_ARM2: 742 #endif 743 #ifdef CPU_ARM250 744 case CPU_CLASS_ARM2AS: 745 #endif 746 #ifdef CPU_ARM3 747 case CPU_CLASS_ARM3: 748 #endif 749 #ifdef CPU_ARM6 750 case CPU_CLASS_ARM6: 751 #endif 752 #ifdef CPU_ARM7 753 case CPU_CLASS_ARM7: 754 #endif 755 #ifdef CPU_ARM7TDMI 756 case CPU_CLASS_ARM7TDMI: 757 #endif 758 #ifdef CPU_ARM8 759 case CPU_CLASS_ARM8: 760 #endif 761 #ifdef CPU_ARM9 762 case CPU_CLASS_ARM9TDMI: 763 #endif 764 #if defined(CPU_ARM9E) || defined(CPU_SHEEVA) 765 case CPU_CLASS_ARM9ES: 766 case CPU_CLASS_ARM9EJS: 767 #endif 768 #ifdef CPU_ARM10 769 case CPU_CLASS_ARM10E: 770 case CPU_CLASS_ARM10EJ: 771 #endif 772 #if defined(CPU_SA110) || defined(CPU_SA1100) || \ 773 defined(CPU_SA1110) || defined(CPU_IXP12X0) 774 case CPU_CLASS_SA1: 775 #endif 776 #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 777 defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425) 778 case CPU_CLASS_XSCALE: 779 #endif 780 #if defined(CPU_ARM11) 781 case CPU_CLASS_ARM11J: 782 #endif 783 #if defined(CPU_CORTEX) 784 case CPU_CLASS_CORTEX: 785 #endif 786 #if defined(CPU_PJ4B) 787 case CPU_CLASS_PJ4B: 788 #endif 789 #if defined(CPU_FA526) 790 case CPU_CLASS_ARMV4: 791 #endif 792 break; 793 default: 794 if (cpu_classes[cpu_class].class_option == NULL) { 795 aprint_error_dev(dv, "%s does not fully support this CPU.\n", 796 ostype); 797 } else { 798 aprint_error_dev(dv, "This kernel does not fully support " 799 "this CPU.\n"); 800 aprint_normal_dev(dv, "Recompile with \"options %s\" to " 801 "correct this.\n", cpu_classes[cpu_class].class_option); 802 } 803 break; 804 } 805 } 806 807 extern int cpu_instruction_set_attributes[6]; 808 extern int cpu_memory_model_features[4]; 809 extern int cpu_processor_features[2]; 810 extern int cpu_simd_present; 811 extern int cpu_simdex_present; 812 813 void 814 identify_features(device_t dv) 815 { 816 cpu_instruction_set_attributes[0] = armreg_isar0_read(); 817 cpu_instruction_set_attributes[1] = armreg_isar1_read(); 818 cpu_instruction_set_attributes[2] = armreg_isar2_read(); 819 cpu_instruction_set_attributes[3] = armreg_isar3_read(); 820 cpu_instruction_set_attributes[4] = armreg_isar4_read(); 821 cpu_instruction_set_attributes[5] = armreg_isar5_read(); 822 823 cpu_hwdiv_present = 824 ((cpu_instruction_set_attributes[0] >> 24) & 0x0f) >= 2; 825 cpu_simd_present = 826 ((cpu_instruction_set_attributes[3] >> 4) & 0x0f) >= 3; 827 cpu_simdex_present = cpu_simd_present 828 && ((cpu_instruction_set_attributes[1] >> 12) & 0x0f) >= 2; 829 cpu_synchprim_present = 830 ((cpu_instruction_set_attributes[3] >> 8) & 0xf0) 831 | ((cpu_instruction_set_attributes[4] >> 20) & 0x0f); 832 833 cpu_memory_model_features[0] = armreg_mmfr0_read(); 834 cpu_memory_model_features[1] = armreg_mmfr1_read(); 835 cpu_memory_model_features[2] = armreg_mmfr2_read(); 836 cpu_memory_model_features[3] = armreg_mmfr3_read(); 837 838 #if 0 839 if (__SHIFTOUT(cpu_memory_model_features[3], __BITS(23,20))) { 840 /* 841 * Updates to the translation tables do not require a clean 842 * to the point of unification to ensure visibility by 843 * subsequent translation table walks. 844 */ 845 pmap_needs_pte_sync = 0; 846 } 847 #endif 848 849 cpu_processor_features[0] = armreg_pfr0_read(); 850 cpu_processor_features[1] = armreg_pfr1_read(); 851 852 aprint_debug_dev(dv, "sctlr: %#x\n", armreg_sctlr_read()); 853 aprint_debug_dev(dv, "actlr: %#x\n", armreg_auxctl_read()); 854 aprint_debug_dev(dv, "revidr: %#x\n", armreg_revidr_read()); 855 #ifdef MULTIPROCESSOR 856 aprint_debug_dev(dv, "mpidr: %#x\n", armreg_mpidr_read()); 857 #endif 858 aprint_debug_dev(dv, 859 "isar: [0]=%#x [1]=%#x [2]=%#x [3]=%#x, [4]=%#x, [5]=%#x\n", 860 cpu_instruction_set_attributes[0], 861 cpu_instruction_set_attributes[1], 862 cpu_instruction_set_attributes[2], 863 cpu_instruction_set_attributes[3], 864 cpu_instruction_set_attributes[4], 865 cpu_instruction_set_attributes[5]); 866 aprint_debug_dev(dv, 867 "mmfr: [0]=%#x [1]=%#x [2]=%#x [3]=%#x\n", 868 cpu_memory_model_features[0], cpu_memory_model_features[1], 869 cpu_memory_model_features[2], cpu_memory_model_features[3]); 870 aprint_debug_dev(dv, 871 "pfr: [0]=%#x [1]=%#x\n", 872 cpu_processor_features[0], cpu_processor_features[1]); 873 } 874
Indexes created Wed Oct 22 13:09:56 GMT 2025