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History log of /src/sys/arch/arm/arm32/cpu.c
RevisionDateAuthorComments
 1.155  09-Oct-2025  skrll Add the beginnings of a GENERIC_V5 kernel that targets armv5 boards and
uses FDT.

In this first iteration some support is added for OLinuXino boards.

Thanks to Yuri Honegger for doing the vast majority of the work.
 1.154  09-May-2024  pho kern/58195: arm: Support drvctl -d and -r for cpufeaturebus

This is required for detaching and re-attaching the vmt(4) driver on aarch64.
 1.153  03-Mar-2022  riastradh arm: Use device_set_private for cpuN.

For cpu at fdt, nix the fdt softc -- this was leaked and never used
for anything. The device's private storage is the cpu_info.
 1.152  31-Oct-2021  skrll Rework Arm (32bit and 64bit) AP startup so that cpu_hatch doesn't sleep.

The AP initialisation code in cpu_init_secondary_processor will read and
initialise the required system registers and state for the BP to attach
and report.

Rework the interrupt handler code for this new sequence. Thankfully,
this removes a bunch of code for bcm2836mp.

The VFP detection handler on <= armv7 relies on the global undefined
handler being in place until the BP attaches vfp. That is, after the
APs have been spun up.

gicv3_its.c has a serialisation issue which is protected against in
the gicv3_its_cpu_init, which is called from cpu_hatch, with a spin
lock. The serialisation issue needs addressing more completely.

Tested on RPI3, Apple M1, QEMU, and lx2k

Fixes PR port-arm/56264:
diagnostic assertion "l->l_stat == LSONPROC" failed on RPI3
 1.151  11-Oct-2021  rin For some classic CPUs, info->[id]cache_sets are not initialized.
Calculate and print numbers of sets in this case.
 1.150  11-Oct-2021  rin pN steppings are used for ARM926EJ-S, although only r0 seems to be available.
 1.149  23-Sep-2021  skrll Print the cache information in similar formats and arm and aarch64, e.g.

arm before
[ 1.0000000] cpu0: 32KB/64B 2-way L1 PIPT Instruction cache
[ 1.0000000] cpu0: 32KB/64B 2-way write-back-locking-C L1 PIPT Data cache
[ 1.0000000] cpu0: 2304KB/64B 16-way write-through L2 PIPT Unified cache

arm after
[ 1.0000000] cpu0: L1 32KB/64B 2-way (256 set) PIPT Instruction cache
[ 1.0000000] cpu0: L1 32KB/64B 2-way (256 set) write-back-locking-C PIPT Data cache
[ 1.0000000] cpu0: L2 2304KB/64B 16-way (2304 set) write-through PIPT Unified cache

aarch64 before
[ 1.0000030] cpu1: L1 48KB/64B*256L*3W PIPT Instruction cache
[ 1.0000030] cpu1: L1 32KB/64B*256L*2W PIPT Data cache
[ 1.0000030] cpu1: L2 2048KB/64B*2048L*16W PIPT Unified cache

aarch64 after
[ 1.0000030] cpu1: L1 48KB/64B 3-way (256 set) PIPT Instruction cache
[ 1.0000030] cpu1: L1 32KB/64B 2-way (256 set) PIPT Data cache
[ 1.0000030] cpu1: L2 2048KB/64B 16-way (2048 set) PIPT Unified cache
 1.148  06-Jul-2021  skrll Assume all ARM11[37]6 r0 variants are missing ISAR and friends. This is
certainly the case for r0 variants I could find TRMs for.

PR/50596 CPU_ID_ARM1136JS r0p4 does not support feature registers
 1.147  02-Jul-2020  martin branches: 1.147.6;
Initialize ci_kfpu_spl earlier for secondary CPUs. From riastradh
 1.146  29-Jun-2020  riastradh Implement fpu_kern_enter/leave for arm32.
 1.145  20-Jun-2020  skrll KNF #includes

Remove some unnecessary ones while I'm here.
 1.144  15-Feb-2020  skrll Various updates and improvements to cpu start up on arm/aarch64

- start sharing more code around the AP startup messaging.
- call arm_cpu_topology_set early so that ci_core_id is available for
drivers, e.g. bcm2835_intr.c
- both arm and aarch64 now have
- a static cpu_info_store array
- the same arm_cpu_{hatched,mbox}
 1.143  22-Jan-2020  skrll #ifdef whack-a-mole for the pmap_maxproc_set functionality
 1.142  20-Jan-2020  skrll s/_ARM_ARCH_6/ARM_MMU_EXTENDED/ in the #ifdef for the recent 4k pages
change
 1.141  18-Jan-2020  skrll Use 4K pages on ARM_MMU_EXTENDED platforms (all armv[67] except RPI) by
creating a new pool l1ttpl for the userland L1 translation table which
needs to be 8KB and 8KB aligned.

Limit the pool to maxproc and add hooks to allow the sysctl changing of
maxproc to adjust the pool.

This comes at a 5% performance penalty for build.sh -j8 kernel on a
Tegra TK1.
 1.140  15-Jan-2020  mrg port the arm64 cpu topology setup for big.little to arm.

rename arm64 cpu_do_topology() to arm_cpu_do_topology() and
call it from both arm cpu_attach().

replace both aarch64_set_topology() inline code in arm
cpu_attach() with new arm_cpu_do_topology(), which is called
by the arm64 locore as well (possibly not needed, which would
allow it to become static.)

not yet tested on a real big.little armv7 system. tested
on rockpro64 and pinebook pro.
 1.139  09-Jan-2020  ad - Many small tweaks to the SMT awareness in the scheduler. It does a much
better job now at keeping all physical CPUs busy, while using the extra
threads to help out. In particular, during preempt() if we're using SMT,
try to find a better CPU to run on and teleport curlwp there.

- Change the CPU topology stuff so it can work on asymmetric systems. This
mainly entails rearranging one of the CPU lists so it makes sense in all
configurations.

- Add a parameter to cpu_topology_set() to note that a CPU is "slow", for
where there are fast CPUs and slow CPUs, like with the Rockwell RK3399.
Extend the SMT awareness to try and handle that situation too (keep fast
CPUs busy, use slow CPUs as helpers).
 1.138  09-Jan-2020  martin When attaching the first fdtbus, use the root "comptabile" (or failing that:
"model") property to set the cpu model (in userland aka sysctl hw.model).
When attaching the first cpu, do not overwrite a cpu model if it already
had been set.
 1.137  08-Jan-2020  jmcneill cpu_hatch is too late to report AP topology, do it at attach time instead
 1.136  20-Dec-2019  ad branches: 1.136.2;
Some more CPU topology stuff:

- Use cegger@'s ACPI SRAT parsing code to figure out NUMA node ID for each
CPU as it is attached.

- For scheduler experiments with SMT, flag CPUs with the lowest numbered SMT
IDs as "primaries", link back to the primaries from secondaries, and build
a circular list of CPUs in each package with identical SMT IDs.

- No need for package/core/smt/numa IDs to be anything other than a u_int.
 1.135  02-Dec-2019  ad Take the basic CPU topology information we already collect, and use it
to make circular lists of CPU siblings in the same core, and in the
same package. Nothing fancy, just enough to have a bit of fun in the
scheduler trying out different tactics.
 1.134  20-Oct-2019  jmcneill cpu_hatched_p only for MULTIPROCESSOR
 1.133  19-Oct-2019  jmcneill Increase aarch64 MAXCPUS to 256.
 1.132  29-Sep-2019  skrll aprint_debug_dev output alignment
 1.131  08-Sep-2019  tnn report A12 as A17 to the user. A12 is retcon'ed by ARM.
 1.130  07-Sep-2019  tnn Cortex A12 is marketed as A17 but has a distinct part number

observed on Rockchip RK3288
 1.129  17-Mar-2019  skrll branches: 1.129.4;
Wrap arm_cpu_marker if #ifdef MPDEBUG.

One day a9_mpsubr.S will die
 1.128  27-Jan-2019  pgoyette Merge the [pgoyette-compat] branch
 1.127  25-Jan-2019  skrll Make sure ci_{smt,core,package}_id are all filled in appropriately.

Previously the BP was missed and __SHIFTOUT wasn't used.
 1.126  03-Jan-2019  jmcneill Read mpidr and cpuid from the secondary processor itself instead of the
boot processor. While here, add Cortex-A15 r4p0 to supported list.
 1.125  03-Jan-2019  skrll Start CPUs more like aarch64 by using a cpu_mpidr array (if populated)
to map MPIDRs to an index for each CPU.

Towards big.LITTLE support.
 1.124  02-Jan-2019  skrll Don't overwrite the setting of cpu_core_id from mpidr
 1.123  18-Oct-2018  skrll Provide generic start code that assumes the MMU is off and caches are
disabled as per the linux booting protocol for ARMv6 and ARMv7 boards.
u-boot image type should be changed to 'linux' for correct behaviour.

The new start code builds a minimal "bootstrap" L1PT with cached access
disabled and uses the same table for all processors. AP startup is
performed in less steps and more code is written in C.

The bootstrap tables and stack are placed into an (orphaned) section
"_init_memory" which is given to uvm when it is no longer used.

Various kernels have been converted to use this code and tested. Some
boards were provided by TNF. Thanks!

The GENERIC kernel now boots on boards using the TEGRA, SUNXI and EXYNOS
kernels. The GENERIC kernel will also work on RPI2 using u-boot.

Thanks to martin@ and aymeric@ for testing on parallella and nanosoc
respectively
 1.122  08-Oct-2018  skrll Trialing whitespace
 1.121  06-Oct-2018  skrll Use __BIT. NFC.
 1.120  15-Aug-2018  skrll KNF
 1.119  15-Aug-2018  skrll Fix includes (sys/cdefs.h then sys/param.h)
 1.118  15-Aug-2018  skrll Sprinkle #include "opt_cputypes.h"
 1.117  10-Aug-2018  maxv Retire CPU_ARM2, CPU_ARM250 and CPU_ARM3, they are all leftovers of
acorn26.

ok jmcneill@ skrll@
 1.116  16-Sep-2017  matt branches: 1.116.2; 1.116.4;
Add Cortex-A35 CPU ID.
 1.115  01-Jun-2017  chs branches: 1.115.6;
remove checks for failure after memory allocation calls that cannot fail:

kmem_alloc() with KM_SLEEP
kmem_zalloc() with KM_SLEEP
percpu_alloc()
pserialize_create()
psref_class_create()

all of these paths include an assertion that the allocation has not failed,
so callers should not assert that again.
 1.114  11-Jul-2016  kiyohara Add Cortex-A9 r1.
 1.113  03-Mar-2016  skrll Get the RPI3 working (in aarch32 mode) by recognising Cortex A53 CPUs.
While I'm here add some A57/A72 info as well.

My RPI3 works with FB console - the uart needs some help with its clocks.
 1.112  23-Jan-2016  christos Rename the cpu_id() define to cpu_idnum() so that it does not conflict with
dtrace and friends.
 1.111  12-Nov-2015  jmcneill change some register dumps from aprint_verbose to aprint_debug
 1.110  08-Jul-2015  skrll aprint_verbose [sa]ctlr
 1.109  05-Jun-2015  skrll Print the Revision ID regster (verbose)
 1.108  17-May-2015  matt Print out mpidr on MP systems (verbose print)
 1.107  03-Mar-2015  jmcneill cache type 12 is "write-back", from matt
 1.106  27-Nov-2014  matt branches: 1.106.2;
Add entry for Cortex-A17 r1
 1.105  01-Sep-2014  reinoud Increase the `freqbuf' buffer that holds the result of humanize_number(). Now
it prints 1600 Mhz instead of 1 Ghz.
Pitty enough humanize_number(9) doesn't do 1.6 Ghz type output.
 1.104  28-Mar-2014  matt branches: 1.104.4;
Various MP changes.
 1.103  24-Mar-2014  christos use cpu_{g,s}etmodel
 1.102  20-Mar-2014  matt Define cache type 13
 1.101  03-Mar-2014  matt Add most of the cpu_* variables to <arm/locore.h>
Add and initialize cpu_synchprim_present
 1.100  20-Feb-2014  matt Keep track of what each cache is (VIVT/VIPT/PIPT).

cpu0: 32KB/32B 2-way L1 VIPT Instruction cache
cpu0: 32KB/64B 4-way write-back-locking-C L1 PIPT Data cache
cpu0: 256KB/64B 8-way write-through L2 PIPT Unified cache
 1.99  07-Sep-2013  matt Add a machdep.hwdiv_present sysctl (cortex A7 and A15 have hwdiv instructions)
 1.98  07-Sep-2013  matt Add CPU_ID_CORTEXA7R0 entry
 1.97  18-Aug-2013  matt Move parts of cpu.h that are not needed by MI code in <arm/locore.h>
Don't include <machine/cpu.h> or <machine/frame.h>, use <arm/locore.h>
Use <arm/asm.h> instead of <machine/arm.h>
 1.96  12-Jun-2013  matt branches: 1.96.2;
Nuke cpu_pfr, just use the armreg_pfr?_read inlines
 1.95  12-Jun-2013  matt Use the armreg_pfr?_read inlines.
 1.94  19-May-2013  rkujawa Plug support for PJ4B into our ARM CPU infrastructure.

Obtained from Marvell, Semihalf.
 1.93  03-Feb-2013  matt Add a machdep.cpu_arch sysctl
 1.92  31-Jan-2013  matt Add simple sysctls for cpu_id, fpu_id, neon_present, simd_present,
simdex_present.
Add struct sysctls to return the isar, mmfr, pfr, and mvfr sets.
 1.91  05-Dec-2012  matt ARMFPE hasn't compiled since NetBSD 4. Remove it.
Complete support for FPU_VFP.
fpregs now contains vfpreg.
XXX vfpreg only has space for 16 64-bit FP registers though VFPv3 and later
have 32 64-bit FP registers.
 1.90  30-Nov-2012  msaitoh Use snprintf() instead of sprintf().
 1.89  30-Nov-2012  msaitoh s/,/;/
 1.88  12-Nov-2012  skrll C99 types
 1.87  22-Sep-2012  matt Don't use an asm in pmap_activate to update the TTBR, use cpu_setttb instead
but add a second argument to it to indicate whether the TLB/caches need to be
flushed. Default cortex to pmap_needs_fixup = 1. But check the MMFR3 field
to see if the fixed can be skipped.
Use a cf_flag bit 0 to indicate whether the A9 L2 cache should disable (bit 0 = 1)
or enabeld (bit = 0).

With these changes, the A9 MMU can use traverse caches to do MMU tablewalks
Also, make sure all memory has the shareable bit for the A9.
 1.86  07-Sep-2012  matt branches: 1.86.2;
Switch cortex_a9 back to need_ptesync = 1
Add code to disable the L2 cache on cortex-a9 (for now).
Add evcnt for all the fault types.
Move cache info in a structure and have one for the pcache and one for scache.
Probe L1/L2 caches properly for ARMv7
 1.85  29-Aug-2012  matt Use new armv7 CP15 register to print out cache types.
If the cpu_cc_freq is set, report it.
Add macros to make inlines for reading/writing co-processor registers.
 1.84  14-Aug-2012  matt Use device_t
 1.83  12-Aug-2012  matt Rework VFP support to use PCU.
Add emulation of instruction which save/restore the VFP FPSCR.
Add a sysarch hook to VFP FPSCR manipulation.

[The emulation will be used by libc to store/fetch exception modes and
rounding mode on a per-thread basis.]
 1.82  14-Jul-2012  matt Refresh cortex cpus
 1.81  20-May-2012  skrll Remove the ARM1156T2 bloat - it only has an MPU. Prompted by matt@
 1.80  20-May-2012  skrll Add the ARM1156T2-S
 1.79  20-May-2012  skrll Add the 'Z' to the 1176 cpu product name.

ok matt@
 1.78  10-Mar-2011  bsh branches: 1.78.4; 1.78.8; 1.78.10;
add MPCore to CPU-ID table
add branch predict bit to arm11_options
 1.77  02-Oct-2010  kiyohara branches: 1.77.2;
Add support Marvell Sheeva Core and SoC. (Orion/Kirkwood)
Discovery Innovation not yet.
 1.76  19-Jun-2010  matt Fix cache probing on Cortex. Add missing CORTEX dependency in cpu.c
 1.75  19-Jun-2010  matt Fix c&p error.
 1.74  19-Jun-2010  matt Cleanup the armv7 changes. Add ARM_ARCH_7. Use CPU_CORTEX instead of
CPU_CORTEXA8 everywhere since there more types of Cortex than just the A8.
CPU_CORTEXA8 still exists but causes CPU_CORTEX to be defined.
Add CPU_CORTEXA9 as well. Use .arch armv7a to get us the isb/dsb
instructions.

Test booted to root device prompt on a Beagleboard.
All ARM kernels successfully test built.
 1.73  16-Jun-2010  jmcneill PR port-arm/43299: Support added for igepv2/cortexa8/omap3530

Apply patch from PR, with build fixes. ok skrll, matt
 1.72  23-Jan-2010  mrg branches: 1.72.2; 1.72.4;
rename a local cpu_name structure member to avoid potential conflict
with <sys/cpu.h>'s.
 1.71  25-Oct-2008  matt branches: 1.71.4; 1.71.12;
Fix some missing things for CPU_ID_FA526.
 1.70  24-Oct-2008  matt Add entry for FA526.
 1.69  21-Oct-2008  matt Add Cortex cpus
 1.68  27-Apr-2008  matt branches: 1.68.6;
Merge kernel changes in matt-armv6 to HEAD.
 1.67  15-Mar-2008  rearnsha branches: 1.67.2; 1.67.4;
VFP support.
 1.66  17-Oct-2007  garbled branches: 1.66.12; 1.66.16;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.
 1.65  17-May-2007  yamt branches: 1.65.10; 1.65.12;
merge yamt-idlelwp branch. asked by core@. some ports still needs work.

from doc/BRANCHES:

idle lwp, and some changes depending on it.

1. separate context switching and thread scheduling.
(cf. gmcgarry_ctxsw)
2. implement idle lwp.
3. clean up related MD/MI interfaces.
4. make scheduler(s) modular.
 1.64  06-Jan-2007  christos branches: 1.64.2; 1.64.6; 1.64.8; 1.64.14;
Scott Allan in http://mail-index.netbsd.org/port-arm/2006/07/31/0000.html
Patch to add support for ARM9E
 1.63  06-Jan-2007  christos From Scott Alan in http://mail-index.netbsd.org/port-arm/2006/07/26/0000.html
identify_arm_cpu() prints out a helpful message when it detects that you're
trying to run on a CPU that you didn't configure for. Unfortunately, the
check for class_option being NULL is backward, so it either won't print the
class_option, or it will try to dereference a NULL. The patch just flips the
!= NULL to be == NULL.
 1.62  15-Mar-2006  drochner branches: 1.62.10; 1.62.14;
use km_alloc to get wired kernel memory for kernel stacks
of idle processes for secondary CPUs
(affects the MULTIPROCESSOR case only - does this exist?)
(untested)
 1.61  11-Dec-2005  christos branches: 1.61.4; 1.61.6; 1.61.8; 1.61.10;
merge ktrace-lwp.
 1.60  20-Jul-2005  nonaka Added i80219.
 1.59  04-Jul-2005  bsh branches: 1.59.2;
The first step to support Intel PXA270.

kernel config option CPU_XSCALE_PXA2X0 is now obsoleted by
CPU_XSCALE_PXA250 and CPU_XSCALE_PXA270. If both of them are defined,
CPU is determined run-time.
 1.58  03-Jun-2005  rearnsha Very basic support for the ARM1136.

This code takes no advantage of any 'new' features provided by
architecture 6 devices (such as physically tagged caches or new
MMU features), and basically runs the chip in a 'legacy v5' mode.
 1.57  10-May-2005  rearnsha Add support for arm1026ej-s.
 1.56  14-Apr-2004  bsh distinguish PXA255/26x from PXA2[15]0 in CPU attach message
 1.55  13-Feb-2004  wiz Uppercase CPU, plural is CPUs.
 1.54  26-Oct-2003  chris Fix up some unitialised variables.
 1.53  06-Sep-2003  rearnsha Support for ARM10E class devices.
 1.52  03-Sep-2003  mycroft Recognize some TI processors -- not that you'd want to use them.
 1.51  23-Jun-2003  martin branches: 1.51.2;
Make sure to include opt_foo.h if a defflag option FOO is used.
 1.50  23-May-2003  ichiro support IXP425 Intel Network Processor
running on BigEndian
 1.49  29-Apr-2003  thorpej Use aprint*().
 1.48  14-Feb-2003  rjs Add CPU IDs for PXA B2 and C0 steppings.
 1.47  06-Jan-2003  wiz specified, not specifed.
 1.46  17-Nov-2002  chs change uvm_uarea_alloc() to indicate whether the returned uarea is already
backed by physical pages (ie. because it reused a previously-freed one),
so that we can skip a bunch of useless work in that case.
this fixes the underlying problem behind PR 18543, and also speeds up fork()
quite a bit (eg. 7% on my pc, 1% on my ultra2) when we get a cache hit.
 1.45  13-Oct-2002  chris branches: 1.45.2;
Fix arm kernel build breaks for non multiprocessor systems.
 1.44  13-Oct-2002  bjh21 It appears that MI code requires ci_cpuid to be the CPU number of the CPU
in question, whereas the ARM code was using it to hold the model
identification. To fix this, rename:

ci_cpuid -> ci_arm_cpuid
ci_cputype -> ci_arm_cputype (for consistency)
ci_cpurev -> ci_arm_cpurev (ditto)
ci_cpunum -> ci_cpuid

This makes top(1) give correct CPU numbers in its "STATE" column (all 0 for
now).
 1.43  12-Oct-2002  bjh21 Remember the location of each CPU's idle PCB in struct cpu_info.
Move allocation of the idle PCB from hydra.c to cpu.c and add some
extra initialisation from cpu_fork().
 1.42  01-Oct-2002  bjh21 constify various string tables.
 1.41  06-Sep-2002  gehenna Merge the gehenna-devsw branch into the trunk.

This merge changes the device switch tables from static array to
dynamically generated by config(8).

- All device switches is defined as a constant structure in device drivers.

- The new grammer ``device-major'' is introduced to ``files''.

device-major <prefix> char <num> [block <num>] [<rules>]

- All device major numbers must be listed up in port dependent majors.<arch>
by using this grammer.

- Added the new naming convention.
The name of the device switch must be <prefix>_[bc]devsw for auto-generation
of device switch tables.

- The backward compatibility of loading block/character device
switch by LKM framework is broken. This is necessary to convert
from block/character device major to device name in runtime and vice versa.

- The restriction to assign device major by LKM is completely removed.
We don't need to reserve LKM entries for dynamic loading of device switch.

- In compile time, device major numbers list is packed into the kernel and
the LKM framework will refer it to assign device major number dynamically.
 1.40  22-Jul-2002  briggs Handle i80200 step D0 and i80321 step B0
 1.39  10-Jul-2002  ichiro add cpu id for "PXA250/210 3rd version CPUcore".

for using many PDA/xscale-core.
 1.38  07-Jun-2002  thorpej Add the CPU ID for the 600MHz i80321 part.
 1.37  12-May-2002  ichiro branches: 1.37.2; 1.37.4;
change ICP12x0 steppings.
define CPU_IXP12X0
 1.36  10-May-2002  thorpej Add IXP1200 steppings.
 1.35  03-May-2002  thorpej Add support for the Intel PXA210 and PXA250. From Hiroyuki Bessho, PR 16617.
 1.34  02-May-2002  rjs Enable CPU_CLASS_SA1 for SA1100 and SA1110.
 1.33  12-Apr-2002  thorpej Centralize ARM CPU configuration information by adding a new header
file, <arm/cpuconf.h>, which pulls in "opt_cputypes.h" and then defines
the following:
* CPU_NTYPES -- now many CPU types are configured into the kernel. What
you really want to know is "== 1" or "> 1".
* Defines ARM_ARCH_2, ARM_ARCH_3, ARM_ARCH_4, ARM_ARCH_5, depending
on which ARM architecture versions are configured (based on CPU_*
options). Also defines ARM_NARCH to determins how many architecture
versions are configured.
* Defines ARM_MMU_MEMC, ARM_MMU_GENERIC, ARM_MMU_XSCALE depending on
which classes of ARM MMUs are configured into the kernel, and ARM_NMMUS
to determine how many MMU classes are configured.

Remove the needless inclusion of "opt_cputypes.h" in several places.
Convert remaining users to <arm/cpuconf.h>.
 1.32  27-Mar-2002  thorpej The 80321 manual lies; it does have a CPU ID distinct from the 80200.
Add that CPU ID, and add a case for it.
 1.31  26-Mar-2002  thorpej Restructure a few things in order to support other XScale core
I/O processors:
* The i80200 and the i80321 have the same CPU ID, so split the
CPU_XSCALE option into CPU_XSCALE_80200 and CPU_XSCALE_80321
options, and don't let them both be defined at the same time.
XXX May want to revisit this in the future.
* Split some registers common between the i80200 and i80321 into
<arm/xscale/xscalereg.h>.
* Rename a few existing functions.
 1.30  24-Mar-2002  thorpej Cache the cpu type and cpu revision in cpu_info.
 1.29  16-Mar-2002  bjh21 Only put the CPU type into cpu_model, not the state of the control register.
Instead, print the control register state on the next line at startup.
 1.28  16-Mar-2002  bjh21 Add CPU ID for the ARM1022ES.
Also add a CPU class for ARM10E processors in general.
 1.27  11-Mar-2002  reinoud When ARMFPE wasn't enabled the `usearmfpe' flag was statically initialised
but not used resulting in a compiler error. By splitting the declaration
and the initialisation this is solved.

Better would be to not even declare the flag when ARMFPE isnt enabled but
that would just add to the #ifdef jungle.
 1.26  10-Mar-2002  bjh21 __RCSID -> __KERNEL_RCSID
 1.25  10-Mar-2002  bjh21 Re-work the way that FPAs are handled. If ARMFPE isn't configured, don't
even bother probing for an FPA. If ARMFPE is configured, always use it,
even if there's an FPA (since it provides the FPA support code). Move all
printfs about FPAs into armfpe_init.c.

This means I can delete the last two elements from struct _cpu, so that the
structure, and the whole of <arm/cpus.h> is redundant and can be deleted.
 1.24  10-Mar-2002  bjh21 Remove fpu_model from struct _cpu. Instead, have initialise_arm_fpe()
printf() the FPE version number itself.
 1.23  10-Mar-2002  bjh21 Add a ci_dev element to struct cpu_info, pointing to the device that
corresponds to the CPU.
 1.22  10-Mar-2002  bjh21 Kill the fpu_flags element from struct _cpu. It was only ever set to 0
anyway.
 1.21  10-Mar-2002  bjh21 Clean up inline assembler. Rather than saving R0, copying FPSR to R0,
copying it to the output register and then restoring R0, just copy the
FPSR straight to the output.
 1.20  09-Mar-2002  bjh21 Remove the cpu_model member from struct _cpu, and just use the cpu_model
variable directly. While we're at it, make cpu_model rather larger.
 1.19  09-Mar-2002  bjh21 Remove the cpu_class element from struct _cpu, and make it a local variable
in identify_arm_cpu(), since it's almost unused elsewhere.

Change the detection of bugged StrongARMs to use the cpu ID rather than the
class. This turns "almost" into "entirely".
 1.18  09-Mar-2002  bjh21 Replace cpu_id and cpu_ctrl in struct _cpu with ci_cpuid and ci_ctrl in
struct cpu_info. Also kill the cpuctrl global while we're here, and make
identify_arm_cpu() take a struct cpu_info * as an argument alongside the CPU
number.
 1.17  09-Mar-2002  bjh21 Move arm700bugcount into stuct cpu_info, and attach it in
identify_master_cpu().
 1.16  17-Feb-2002  bjh21 Our assembler handles FPA instructions fine, so don't use .word for them.
 1.15  17-Feb-2002  bjh21 ANSIfy, and othe KNF cleanup.
 1.14  27-Jan-2002  bjh21 Add revision->stepping maps for the SA-110, SA-1100 and SA-1110.
Those for the SA-1100 and SA-1110 are from Intel's documentation.
The mapping for the SA-110 is from various sources on the net, since Intel
don't seem to document it.

Also, change the layout of the maps to have four steppings per line,
so they aren't quite so unwieldy.
 1.13  24-Jan-2002  thorpej Use a table to look up stepping names. Add a generic stepping
table ("rev 0", "rev 1", etc.) and an i80200 stepping table that
has the stepping names that appear in the i80200 manuals/errata..
 1.12  29-Nov-2001  thorpej Fetch cache info from the Cache Type register on ARM7TDMI and "greater"
processors. Report this when the processor is attached.
 1.11  24-Nov-2001  thorpej Move the ARM, Ltd. floating point emulator to arch/arm.
 1.10  23-Nov-2001  thorpej Use <arm/undefined.h> instead of <machine/undefined.h>.
 1.9  06-Nov-2001  thorpej branches: 1.9.2;
Const poisoning of cpu/class names.
 1.8  06-Nov-2001  thorpej "i80200", not "80200".
 1.7  06-Nov-2001  thorpej "XScale", not "Xscale".
 1.6  18-Oct-2001  rearnsha branches: 1.6.2;
Support for ARM9.
 1.5  28-Sep-2001  chris Add extra arg to fpa_test as it should have 4 args. Also add prototypes for fpa_test and fpa_handler.
 1.4  05-Sep-2001  matt branches: 1.4.2;
Flesh XSCALE support.
 1.3  03-Jun-2001  chris branches: 1.3.2; 1.3.4;
Add support for ARM7TDMI, as provided in a patch from John Fremlin to port-arm32.

Shouldn't effect any currently in tree ports.
 1.2  13-May-2001  bjh21 Use get_bootconf_option() to find boot options, rather than home-grown
strstr()-based hacks.
 1.1  20-Apr-2001  matt branches: 1.1.2;
Split cpu from mainbus so that cpu can attached to other buses (like ofbus).
 1.1.2.2  23-Apr-2001  bouyer Sync with HEAD.
 1.1.2.1  20-Apr-2001  bouyer file cpu.c was added on branch thorpej_scsipi on 2001-04-23 09:41:33 +0000
 1.3.4.7  10-Oct-2002  jdolecek sync kqueue with -current; this includes merge of gehenna-devsw branch,
merge of i386 MP branch, and part of autoconf rototil work
 1.3.4.6  06-Sep-2002  jdolecek sync kqueue branch with HEAD
 1.3.4.5  23-Jun-2002  jdolecek catch up with -current on kqueue branch
 1.3.4.4  16-Mar-2002  jdolecek Catch up with -current.
 1.3.4.3  11-Feb-2002  jdolecek Sync w/ -current.
 1.3.4.2  10-Jan-2002  thorpej Sync kqueue branch with -current.
 1.3.4.1  13-Sep-2001  thorpej Update the kqueue branch to HEAD.
 1.3.2.1  21-Jun-2001  nathanw Catch up to -current.
 1.4.2.1  01-Oct-2001  fvdl Catch up with -current.
 1.6.2.1  12-Nov-2001  thorpej Sync the thorpej-mips-cache branch with -current.
 1.9.2.11  07-Jan-2003  thorpej Sync with HEAD.
 1.9.2.10  11-Dec-2002  thorpej Sync with HEAD.
 1.9.2.9  18-Oct-2002  nathanw Catch up to -current.
 1.9.2.8  17-Sep-2002  nathanw Catch up to -current.
 1.9.2.7  01-Aug-2002  nathanw Catch up to -current.
 1.9.2.6  20-Jun-2002  nathanw Catch up to -current.
 1.9.2.5  17-Apr-2002  nathanw Catch up to -current.
 1.9.2.4  01-Apr-2002  nathanw Catch up to -current.
(CVS: It's not just a program. It's an adventure!)
 1.9.2.3  28-Feb-2002  nathanw Catch up to -current.
 1.9.2.2  08-Jan-2002  nathanw Catch up to -current.
 1.9.2.1  06-Nov-2001  nathanw file cpu.c was added on branch nathanw_sa on 2002-01-08 00:23:08 +0000
 1.37.4.2  29-Jul-2002  lukem Pull up revision 1.40 (requested by thorpej in ticket #549):
Handle i80200 step D0 and i80321 step B0
 1.37.4.1  07-Jun-2002  thorpej pullup-1-6 ticket #208:

syssrc/sys/arch/arm/arm/cpufunc.c 1.46
syssrc/sys/arch/arm/arm32/cpu.c 1.38
syssrc/sys/arch/arm/include/armreg.h 1.19

Original log message:

Add the CPU ID for the 600MHz i80321 part.
 1.37.2.4  30-Aug-2002  gehenna catch up with -current.
 1.37.2.3  16-Jul-2002  gehenna catch up with -current.
 1.37.2.2  14-Jul-2002  gehenna catch up with -current.
 1.37.2.1  19-May-2002  gehenna Remove unnecessary #include
 1.45.2.1  19-Oct-2002  bjh21 In cpu_attach(), allocate an idle PCB if the CPU doesn't already have one
(which the boot CPU won't).
 1.51.2.4  10-Nov-2005  skrll Sync with HEAD. Here we go again...
 1.51.2.3  21-Sep-2004  skrll Fix the sync with head I botched.
 1.51.2.2  18-Sep-2004  skrll Sync with HEAD.
 1.51.2.1  03-Aug-2004  skrll Sync with HEAD
 1.59.2.4  17-Mar-2008  yamt sync with head.
 1.59.2.3  03-Sep-2007  yamt sync with head.
 1.59.2.2  26-Feb-2007  yamt sync with head.
 1.59.2.1  21-Jun-2006  yamt sync with head.
 1.61.10.1  19-Apr-2006  elad sync with head - hopefully this will work
 1.61.8.1  01-Apr-2006  yamt sync with head.
 1.61.6.1  22-Apr-2006  simonb Sync with head.
 1.61.4.1  09-Sep-2006  rpaulo sync with head
 1.62.14.2  21-Feb-2007  snj branches: 1.62.14.2.4;
Pull up following revision(s) (requested by matt in ticket #457):
sys/arch/arm/include/cpufunc.h: revision 1.38
sys/arch/arm/arm/cpufunc.c: revision 1.78
sys/arch/arm/arm/cpufunc_asm_arm10.S: revision 1.6
sys/arch/arm/include/armreg.h: revision 1.37
sys/arch/arm/arm32/cpu.c: revision 1.64
sys/arch/arm/arm/cpufunc_asm_armv5.S: revision 1.3
sys/arch/arm/include/cpuconf.h: revision 1.13
sys/arch/arm/conf/files.arm: revision 1.82
sys/arch/arm/arm/cpufunc_asm_armv5_ec.S: revision 1.1
Scott Allan in http://mail-index.netbsd.org/port-arm/2006/07/31/0000.html
Patch to add support for ARM9E
 1.62.14.1  21-Feb-2007  snj Pull up following revision(s) (requested by matt in ticket #457):
sys/arch/arm/arm32/cpu.c: revision 1.63
From Scott Allan in http://mail-index.netbsd.org/port-arm/2006/07/26/0000.html
identify_arm_cpu() prints out a helpful message when it detects that
you're trying to run on a CPU that you didn't configure for.
Unfortunately, the check for class_option being NULL is backward, so it
either won't print the class_option, or it will try to dereference a
NULL. The patch just flips the != NULL to be == NULL.
 1.62.14.2.4.1  10-Nov-2007  matt Add AT91 support from Sami Kantoluoto
Add TI OMAP2430 support from Marty Fouts @ Danger Inc
 1.62.10.1  12-Jan-2007  ad Sync with head.
 1.64.14.1  22-May-2007  matt Update to HEAD.
 1.64.8.1  11-Jul-2007  mjf Sync with head.
 1.64.6.1  27-May-2007  ad Sync with head.
 1.64.2.1  29-Mar-2007  skrll Adapt arm32. Thanks to scw for helping out.

Tested on my cats (SA1)

XXX hydra should die. i've made some changes, but no guarantees.
 1.65.12.2  23-Mar-2008  matt sync with HEAD
 1.65.12.1  28-Aug-2007  matt Add 1176 and print arm11 rev as rVpR (r0p6, r1p0).
 1.65.10.2  21-Mar-2008  chris Sync with head.
 1.65.10.1  01-Jan-2008  chris Sync with HEAD.
 1.66.16.3  17-Jan-2009  mjf Sync with HEAD.
 1.66.16.2  02-Jun-2008  mjf Sync with HEAD.
 1.66.16.1  03-Apr-2008  mjf Sync with HEAD.
 1.66.12.1  24-Mar-2008  keiichi sync with head.
 1.67.4.5  09-Oct-2010  yamt sync with head
 1.67.4.4  11-Aug-2010  yamt sync with head.
 1.67.4.3  11-Mar-2010  yamt sync with head
 1.67.4.2  04-May-2009  yamt sync with head.
 1.67.4.1  16-May-2008  yamt sync with head.
 1.67.2.1  18-May-2008  yamt sync with head.
 1.68.6.1  13-Dec-2008  haad Update haad-dm branch to haad-dm-base2.
 1.71.12.1  15-Feb-2014  matt Merge armv7 support from HEAD, specifically support for the BCM5301X
and BCM56340 evbarm kernels.
 1.71.4.1  20-Jan-2013  bouyer Pull up following revision(s) (requested by msaitoh in ticket #1841):
sys/arch/arm/arm32/cpu.c: revision 1.89
S/,/;/
 1.72.4.3  21-Apr-2011  rmind sync with head
 1.72.4.2  05-Mar-2011  rmind sync with head
 1.72.4.1  03-Jul-2010  rmind sync with head
 1.72.2.2  22-Oct-2010  uebayasi Sync with HEAD (-D20101022).
 1.72.2.1  17-Aug-2010  uebayasi Sync with HEAD.
 1.77.2.1  06-Jun-2011  jruoho Sync with HEAD.
 1.78.10.2  08-Feb-2013  riz Pull up following revision(s) (requested by msaitoh in ticket #788):
sys/arch/arm/arm32/cpu.c: revision 1.89
S/,/;/
 1.78.10.1  09-Aug-2012  jdc branches: 1.78.10.1.2;
Pull up revisions:
src/sys/arch/evbarm/dev/plcomreg.h revisions 1.2,1.3,1.4
src/sys/arch/evbarm/conf/INTEGRATOR revision 1.65
src/sys/arch/evbarm/dev/plcom.c revisions 1.34,1.35,1.36,1.37,1.38,1.39,1.40
src/sys/arch/evbarm/ifpga/plcom_ifpga.c revisions 1.12,1.13,1.14
src/sys/arch/evbarm/dev/plcomvar.h revisions 1.9,1.10,1.11
src/sys/arch/evbarm/ifpga/plcom_ifpgavar.h revision 1.2
src/sys/arch/arm/arm/cpufunc.c revisions 1.105,1.108
src/sys/arch/arm/arm32/cpu.c revision 1.79
src/sys/arch/arm/include/armreg.h revisions 1.49,1.54
src/sys/arch/arm/arm32/pmap.c revision 1.229
src/sys/arch/arm/arm32/arm32_machdep.c revision 1.77
src/sys/arch/arm/include/cpu.h revision 1.64
src/sys/arch/arm/arm/cpufunc_asm_arm1136.S revision 1.3
src/sys/arch/arm/arm/cpufunc_asm_arm11x6.S revision 1.1
src/sys/arch/arm/conf/files.arm revision 1.106
src/sys/arch/arm/include/cpufunc.h revision 1.57
src/sys/dev/sdmmc/sdhc.c revisions 1.14,1.24
src/sys/dev/sdmmc/sdhcvar.h revisions 1.7,1.8
src/sys/arch/evbarm/ifpga/ifpgareg.h revision 1.4
src/sys/arch/evbarm/integrator/integrator_machdep.c revision 1.69
src/sys/arch/arm/broadcom/bcm2835_dma.c revision 1.1
src/sys/arch/arm/broadcom/bcm2835_emmc.c revision 1.1
src/sys/arch/arm/broadcom/bcm2835_intr.c revision 1.1
src/sys/arch/arm/broadcom/bcm2835_intr.h revision 1.1
src/sys/arch/arm/broadcom/bcm2835_obio.c revision 1.1
src/sys/arch/arm/broadcom/bcm2835_plcom.c revision 1.1
src/sys/arch/arm/broadcom/bcm2835_pm.c revision 1.1
src/sys/arch/arm/broadcom/bcm2835_pmvar.h revision 1.1
src/sys/arch/arm/broadcom/bcm2835_space.c revision 1.1
src/sys/arch/arm/broadcom/bcm2835_tmr.c revision 1.1
src/sys/arch/arm/broadcom/bcm2835reg.h revision 1.1
src/sys/arch/arm/broadcom/bcm2835var.h revision 1.1
src/sys/arch/arm/broadcom/bcm_amba.h revision 1.1
src/sys/arch/arm/broadcom/files.bcm2835 revision 1.1
src/sys/arch/evbarm/Makefile revision 1.9
src/sys/arch/evbarm/conf/RPI revision 1.1
src/sys/arch/evbarm/conf/files.rpi revision 1.1
src/sys/arch/evbarm/conf/mk.rpi revision 1.1
src/sys/arch/evbarm/conf/std.rpi revision 1.1
src/sys/arch/evbarm/rpi/genassym.cf revision 1.1
src/sys/arch/evbarm/rpi/rpi.h revision 1.1
src/sys/arch/evbarm/rpi/rpi_machdep.c revision 1.1
src/sys/arch/evbarm/rpi/rpi_start.S revision 1.1,1.2
src/etc/etc.evbarm/Makefile.inc revision 1.28
(requested by skrll in ticket #454).

don't mix #define<TAB> and #define<SPACE> in a file.

avoid warning with options PLCOM_DEBUG for INTEGRATOR.

Rename register values. No functional change - same code before and after.

Existing names are prefixed with PL01X_ where they're common between the
PL010 and the PL011. The PL010_/PL011_ prefixes are added where they're
found only on the respective chips.

Replace the simple_lock with a kmutex_t. Update the locking to match
com(4) in the few places it didn't already.

DOH. Replace a line that got accidently deleted in the last commit.

device_t/softc split
struct device * -> device_t
struct cfdata * -> cfdata_t

Add the 'Z' to the 1176 cpu product name.

ok matt@

Fix locking botch introduced in 1.36.

Fix a KASSERT. From/OK'ed by matt@

Fix racy softint dispatch that lead to KASSERT(si->si_active) in
softint_execute

Discussed with matt@. "Looks good to me"

Add the documented ARM11[37]6 Auxiliary control register defines.

Add support for the ARM1176JZS

Add a flag for the lack of LED_ON in HOST_CTL (ti omap3 doesn't do that).

Provide a method for attachments to specify capabilites.

Add support for the PL011 to plcom. Pull across a bunch of fixes from
com(4) while I'm here and do some other tidyup.

Tested on a RaspberryPi.

PL010 not tested.

Initial commit of support for the RaspberryPI (www.raspberrypi.org)

This is enough for serial console via the gpio header pins and to get to
multiuser.

A huge thank you to Matt Thomas for all his help.

Add RPI to KERNEL_SETS

Remove #if 0 code.
 1.78.10.1.2.1  28-Nov-2012  matt Merge improved arm support (especially Cortex) from HEAD
including OMAP and BCM53xx support.
 1.78.8.1  02-Jun-2012  mrg sync to latest -current.
 1.78.4.4  22-May-2014  yamt sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
 1.78.4.3  16-Jan-2013  yamt sync with (a bit old) head
 1.78.4.2  30-Oct-2012  yamt sync with head
 1.78.4.1  23-May-2012  yamt sync with head.
 1.86.2.5  03-Dec-2017  jdolecek update from HEAD
 1.86.2.4  20-Aug-2014  tls Rebase to HEAD as of a few days ago.
 1.86.2.3  23-Jun-2013  tls resync from head
 1.86.2.2  25-Feb-2013  tls resync with head
 1.86.2.1  20-Nov-2012  tls Resync to 2012-11-19 00:00:00 UTC
 1.96.2.2  18-May-2014  rmind sync with head
 1.96.2.1  28-Aug-2013  rmind sync with head
 1.104.4.2  26-Jul-2017  snj Pull up following revision(s) (requested by jmcneill in ticket #1435):
sys/arch/arm/arm32/cpu.c: 1.113 via patch
sys/arch/arm/broadcom/bcm2835_bsc.c: 1.6 via patch
sys/arch/arm/broadcom/bcm2835_plcom.c: 1.4 via patch
sys/arch/arm/cortex/gtmr.c: 1.18 via patch
sys/arch/arm/include/armreg.h: 1.110 via patch
sys/arch/arm/include/vfpreg.h: 1.15 via patch
sys/arch/arm/vfp/vfp_init.c: 1.50 via patch
sys/arch/evbarm/rpi/rpi_machdep.c: 1.59, 1.70-1.72 via patch
sys/arch/evbarm/rpi/vcprop.h: 1.16
Get the RPI3 working (in aarch32 mode) by recognising Cortex A53 CPUs.
While I'm here add some A57/A72 info as well.
My RPI3 works with FB console - the uart needs some help with its clocks.
--
Do invalidate the cache as RPI2 build with Clang can't fetch the memory
config otherwise.
--
Use the VC property mailbox to request the UART clock rate and use it
appropriately
Newer firmwares use 48MHz
--
Disable BSC0 on Raspberry Pi 3 and Zero W boards.
--
Interrupts are enabled before the timer is configured. Ensure that the
timer is disabled when attaching so it doesn't go crazy between the time
interrupts are enabled and clocks are initialized. My RPI3 makes it
multi-user now.
--
Enable UART0 (PL011) on GPIO header for Raspberry Pi 3 / Zero W
 1.104.4.1  06-Apr-2015  snj Pull up following revision(s) (requested by jmcneill in ticket #663):
sys/arch/arm/arm32/cpu.c: revision 1.105
Increase the `freqbuf' buffer that holds the result of humanize_number(). Now
it prints 1600 Mhz instead of 1 Ghz.
Pitty enough humanize_number(9) doesn't do 1.6 Ghz type output.
 1.106.2.7  28-Aug-2017  skrll Sync with HEAD
 1.106.2.6  05-Oct-2016  skrll Sync with HEAD
 1.106.2.5  19-Mar-2016  skrll Sync with HEAD
 1.106.2.4  27-Dec-2015  skrll Sync with HEAD (as of 26th Dec)
 1.106.2.3  22-Sep-2015  skrll Sync with HEAD
 1.106.2.2  06-Jun-2015  skrll Sync with HEAD
 1.106.2.1  06-Apr-2015  skrll Sync with HEAD
 1.115.6.1  13-Dec-2017  matt Add Cortex A35
 1.116.4.3  13-Apr-2020  martin Mostly merge changes from HEAD upto 20200411
 1.116.4.2  08-Apr-2020  martin Merge changes from current as of 20200406
 1.116.4.1  10-Jun-2019  christos Sync with HEAD
 1.116.2.4  26-Jan-2019  pgoyette Sync with HEAD
 1.116.2.3  18-Jan-2019  pgoyette Synch with HEAD
 1.116.2.2  20-Oct-2018  pgoyette Sync with head
 1.116.2.1  06-Sep-2018  pgoyette Sync with HEAD

Resolve a couple of conflicts (result of the uimin/uimax changes)
 1.129.4.2  09-Jan-2020  snj Pull up following revision(s) (requested by martin in ticket #614):

sys/arch/aarch64/aarch64/cpu.c: 1.32
sys/arch/arm/arm32/cpu.c: 1.138
sys/dev/fdt/fdtbus.c: 1.31

When attaching the first fdtbus, use the root "comptabile" (or failing that:
"model") property to set the cpu model (in userland aka sysctl hw.model).
When attaching the first cpu, do not overwrite a cpu model if it already
had been set.
 1.129.4.1  23-Oct-2019  martin Pull up following revision(s) (requested by jmcneill in ticket #359):

sys/arch/aarch64/aarch64/locore.S: revision 1.42
sys/arch/aarch64/aarch64/locore.S: revision 1.43
sys/arch/aarch64/aarch64/locore.S: revision 1.44
sys/arch/arm/fdt/cpu_fdt.c: revision 1.28
sys/arch/aarch64/include/cpu.h: revision 1.14
sys/arch/aarch64/include/param.h: revision 1.12
sys/arch/arm/arm32/cpu.c: revision 1.133
sys/arch/arm/arm32/cpu.c: revision 1.134
sys/arch/arm/include/cpu.h: revision 1.101
sys/arch/arm/acpi/cpu_acpi.c: revision 1.7
sys/arch/aarch64/aarch64/cpu.c: revision 1.23
sys/arch/aarch64/aarch64/cpu.c: revision 1.24
sys/arch/aarch64/aarch64/cpu.c: revision 1.25

Increase aarch64 MAXCPUS to 256.

-

Invalidate dcache before polling AP hatched status

-

Avoid overlap between BP and last AP stack. AP stacks are now in order of
increasing address order.

Spotted by and idea from mlelstv.

-

Use separate cacheline aligned arrays for mbox and hatched as before.

-

cpu_hatched_p only for MULTIPROCESSOR
 1.136.2.3  29-Feb-2020  ad Sync with head.
 1.136.2.2  25-Jan-2020  ad Sync with head.
 1.136.2.1  17-Jan-2020  ad Sync with head.
 1.147.6.1  01-Aug-2021  thorpej Sync with HEAD.

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