cpu.c revision 1.135
1 /* $NetBSD: cpu.c,v 1.135 2019/12/02 23:22:43 ad Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Mark Brinicombe. 5 * Copyright (c) 1995 Brini. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Brini. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * cpu.c 38 * 39 * Probing and configuration for the master CPU 40 * 41 * Created : 10/10/95 42 */ 43 44 #include "opt_armfpe.h" 45 #include "opt_cputypes.h" 46 #include "opt_multiprocessor.h" 47 48 #include <sys/cdefs.h> 49 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.135 2019/12/02 23:22:43 ad Exp $"); 50 51 #include <sys/param.h> 52 #include <sys/conf.h> 53 #include <sys/cpu.h> 54 #include <sys/device.h> 55 #include <sys/kmem.h> 56 #include <sys/proc.h> 57 #include <sys/systm.h> 58 59 #include <uvm/uvm_extern.h> 60 61 #include <arm/locore.h> 62 #include <arm/undefined.h> 63 64 extern const char *cpu_arch; 65 66 #ifdef MULTIPROCESSOR 67 uint32_t cpu_mpidr[MAXCPUS] = { 68 [0 ... MAXCPUS - 1] = ~0, 69 }; 70 71 volatile u_int arm_cpu_hatched __cacheline_aligned = 0; 72 volatile uint32_t arm_cpu_mbox __cacheline_aligned = 0; 73 u_int arm_cpu_max = 1; 74 75 #ifdef MPDEBUG 76 uint32_t arm_cpu_marker[2] __cacheline_aligned = { 0, 0 }; 77 #endif 78 79 #endif 80 81 /* Prototypes */ 82 void identify_arm_cpu(device_t, struct cpu_info *); 83 void identify_cortex_caches(device_t); 84 void identify_features(device_t); 85 86 /* 87 * Identify the master (boot) CPU 88 */ 89 90 void 91 cpu_attach(device_t dv, cpuid_t id) 92 { 93 const char * const xname = device_xname(dv); 94 const int unit = device_unit(dv); 95 struct cpu_info *ci; 96 97 if (unit == 0) { 98 ci = curcpu(); 99 100 /* Read SCTLR from cpu */ 101 ci->ci_ctrl = cpu_control(0, 0); 102 103 /* Get the CPU ID from coprocessor 15 */ 104 105 ci->ci_cpuid = id; 106 ci->ci_arm_cpuid = cpu_idnum(); 107 ci->ci_arm_cputype = ci->ci_arm_cpuid & CPU_ID_CPU_MASK; 108 ci->ci_arm_cpurev = ci->ci_arm_cpuid & CPU_ID_REVISION_MASK; 109 #ifdef MULTIPROCESSOR 110 uint32_t mpidr = armreg_mpidr_read(); 111 ci->ci_mpidr = mpidr; 112 113 if (mpidr & MPIDR_MT) { 114 cpu_topology_set(ci, 115 __SHIFTOUT(mpidr, MPIDR_AFF2), 116 __SHIFTOUT(mpidr, MPIDR_AFF1), 117 __SHIFTOUT(mpidr, MPIDR_AFF0)); 118 } else { 119 cpu_topology_set(ci, 120 __SHIFTOUT(mpidr, MPIDR_AFF1), 121 __SHIFTOUT(mpidr, MPIDR_AFF0), 122 0); 123 } 124 #endif 125 } else { 126 #ifdef MULTIPROCESSOR 127 KASSERT(cpu_info[unit] == NULL); 128 ci = kmem_zalloc(sizeof(*ci), KM_SLEEP); 129 ci->ci_cpl = IPL_HIGH; 130 ci->ci_cpuid = id; 131 ci->ci_data.cpu_cc_freq = cpu_info_store.ci_data.cpu_cc_freq; 132 133 ci->ci_undefsave[2] = cpu_info_store.ci_undefsave[2]; 134 135 cpu_info[unit] = ci; 136 if (cpu_hatched_p(unit) == false) { 137 ci->ci_dev = dv; 138 dv->dv_private = ci; 139 aprint_naive(": disabled\n"); 140 aprint_normal(": disabled (unresponsive)\n"); 141 return; 142 } 143 #else 144 aprint_naive(": disabled\n"); 145 aprint_normal(": disabled (uniprocessor kernel)\n"); 146 return; 147 #endif 148 } 149 150 ci->ci_dev = dv; 151 dv->dv_private = ci; 152 153 evcnt_attach_dynamic(&ci->ci_arm700bugcount, EVCNT_TYPE_MISC, 154 NULL, xname, "arm700swibug"); 155 156 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_WRTBUF_0], EVCNT_TYPE_TRAP, 157 NULL, xname, "vector abort"); 158 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_WRTBUF_1], EVCNT_TYPE_TRAP, 159 NULL, xname, "terminal abort"); 160 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_BUSERR_0], EVCNT_TYPE_TRAP, 161 NULL, xname, "external linefetch abort (S)"); 162 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_BUSERR_1], EVCNT_TYPE_TRAP, 163 NULL, xname, "external linefetch abort (P)"); 164 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_BUSERR_2], EVCNT_TYPE_TRAP, 165 NULL, xname, "external non-linefetch abort (S)"); 166 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_BUSERR_3], EVCNT_TYPE_TRAP, 167 NULL, xname, "external non-linefetch abort (P)"); 168 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_BUSTRNL1], EVCNT_TYPE_TRAP, 169 NULL, xname, "external translation abort (L1)"); 170 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_BUSTRNL2], EVCNT_TYPE_TRAP, 171 NULL, xname, "external translation abort (L2)"); 172 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_ALIGN_0], EVCNT_TYPE_TRAP, 173 NULL, xname, "alignment abort (0)"); 174 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_ALIGN_1], EVCNT_TYPE_TRAP, 175 NULL, xname, "alignment abort (1)"); 176 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_TRANS_S], EVCNT_TYPE_TRAP, 177 NULL, xname, "translation abort (S)"); 178 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_TRANS_P], EVCNT_TYPE_TRAP, 179 NULL, xname, "translation abort (P)"); 180 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_DOMAIN_S], EVCNT_TYPE_TRAP, 181 NULL, xname, "domain abort (S)"); 182 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_DOMAIN_P], EVCNT_TYPE_TRAP, 183 NULL, xname, "domain abort (P)"); 184 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_PERM_S], EVCNT_TYPE_TRAP, 185 NULL, xname, "permission abort (S)"); 186 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_PERM_P], EVCNT_TYPE_TRAP, 187 NULL, xname, "permission abort (P)"); 188 evcnt_attach_dynamic_nozero(&ci->ci_und_ev, EVCNT_TYPE_TRAP, 189 NULL, xname, "undefined insn traps"); 190 evcnt_attach_dynamic_nozero(&ci->ci_und_cp15_ev, EVCNT_TYPE_TRAP, 191 NULL, xname, "undefined cp15 insn traps"); 192 193 #ifdef MULTIPROCESSOR 194 /* 195 * and we are done if this is a secondary processor. 196 */ 197 if (unit != 0) { 198 aprint_naive("\n"); 199 aprint_normal("\n"); 200 mi_cpu_attach(ci); 201 #ifdef ARM_MMU_EXTENDED 202 pmap_tlb_info_attach(&pmap_tlb0_info, ci); 203 #endif 204 return; 205 } 206 #endif 207 208 identify_arm_cpu(dv, ci); 209 210 #ifdef CPU_STRONGARM 211 if (ci->ci_arm_cputype == CPU_ID_SA110 && 212 ci->ci_arm_cpurev < 3) { 213 aprint_normal_dev(dv, "SA-110 with bugged STM^ instruction\n"); 214 } 215 #endif 216 217 #ifdef CPU_ARM8 218 if ((ci->ci_arm_cpuid & CPU_ID_CPU_MASK) == CPU_ID_ARM810) { 219 int clock = arm8_clock_config(0, 0); 220 char *fclk; 221 aprint_normal_dev(dv, "ARM810 cp15=%02x", clock); 222 aprint_normal(" clock:%s", (clock & 1) ? " dynamic" : ""); 223 aprint_normal("%s", (clock & 2) ? " sync" : ""); 224 switch ((clock >> 2) & 3) { 225 case 0: 226 fclk = "bus clock"; 227 break; 228 case 1: 229 fclk = "ref clock"; 230 break; 231 case 3: 232 fclk = "pll"; 233 break; 234 default: 235 fclk = "illegal"; 236 break; 237 } 238 aprint_normal(" fclk source=%s\n", fclk); 239 } 240 #endif 241 242 vfp_attach(ci); /* XXX SMP */ 243 } 244 245 #ifdef MULTIPROCESSOR 246 bool 247 cpu_hatched_p(u_int cpuindex) 248 { 249 membar_consumer(); 250 return (arm_cpu_hatched & __BIT(cpuindex)) != 0; 251 } 252 #endif 253 254 enum cpu_class { 255 CPU_CLASS_NONE, 256 CPU_CLASS_ARM2, 257 CPU_CLASS_ARM2AS, 258 CPU_CLASS_ARM3, 259 CPU_CLASS_ARM6, 260 CPU_CLASS_ARM7, 261 CPU_CLASS_ARM7TDMI, 262 CPU_CLASS_ARM8, 263 CPU_CLASS_ARM9TDMI, 264 CPU_CLASS_ARM9ES, 265 CPU_CLASS_ARM9EJS, 266 CPU_CLASS_ARM10E, 267 CPU_CLASS_ARM10EJ, 268 CPU_CLASS_SA1, 269 CPU_CLASS_XSCALE, 270 CPU_CLASS_ARM11J, 271 CPU_CLASS_ARMV4, 272 CPU_CLASS_CORTEX, 273 CPU_CLASS_PJ4B, 274 }; 275 276 static const char * const generic_steppings[16] = { 277 "rev 0", "rev 1", "rev 2", "rev 3", 278 "rev 4", "rev 5", "rev 6", "rev 7", 279 "rev 8", "rev 9", "rev 10", "rev 11", 280 "rev 12", "rev 13", "rev 14", "rev 15", 281 }; 282 283 static const char * const pN_steppings[16] = { 284 "*p0", "*p1", "*p2", "*p3", "*p4", "*p5", "*p6", "*p7", 285 "*p8", "*p9", "*p10", "*p11", "*p12", "*p13", "*p14", "*p15", 286 }; 287 288 static const char * const sa110_steppings[16] = { 289 "rev 0", "step J", "step K", "step S", 290 "step T", "rev 5", "rev 6", "rev 7", 291 "rev 8", "rev 9", "rev 10", "rev 11", 292 "rev 12", "rev 13", "rev 14", "rev 15", 293 }; 294 295 static const char * const sa1100_steppings[16] = { 296 "rev 0", "step B", "step C", "rev 3", 297 "rev 4", "rev 5", "rev 6", "rev 7", 298 "step D", "step E", "rev 10" "step G", 299 "rev 12", "rev 13", "rev 14", "rev 15", 300 }; 301 302 static const char * const sa1110_steppings[16] = { 303 "step A-0", "rev 1", "rev 2", "rev 3", 304 "step B-0", "step B-1", "step B-2", "step B-3", 305 "step B-4", "step B-5", "rev 10", "rev 11", 306 "rev 12", "rev 13", "rev 14", "rev 15", 307 }; 308 309 static const char * const ixp12x0_steppings[16] = { 310 "(IXP1200 step A)", "(IXP1200 step B)", 311 "rev 2", "(IXP1200 step C)", 312 "(IXP1200 step D)", "(IXP1240/1250 step A)", 313 "(IXP1240 step B)", "(IXP1250 step B)", 314 "rev 8", "rev 9", "rev 10", "rev 11", 315 "rev 12", "rev 13", "rev 14", "rev 15", 316 }; 317 318 static const char * const xscale_steppings[16] = { 319 "step A-0", "step A-1", "step B-0", "step C-0", 320 "step D-0", "rev 5", "rev 6", "rev 7", 321 "rev 8", "rev 9", "rev 10", "rev 11", 322 "rev 12", "rev 13", "rev 14", "rev 15", 323 }; 324 325 static const char * const i80321_steppings[16] = { 326 "step A-0", "step B-0", "rev 2", "rev 3", 327 "rev 4", "rev 5", "rev 6", "rev 7", 328 "rev 8", "rev 9", "rev 10", "rev 11", 329 "rev 12", "rev 13", "rev 14", "rev 15", 330 }; 331 332 static const char * const i80219_steppings[16] = { 333 "step A-0", "rev 1", "rev 2", "rev 3", 334 "rev 4", "rev 5", "rev 6", "rev 7", 335 "rev 8", "rev 9", "rev 10", "rev 11", 336 "rev 12", "rev 13", "rev 14", "rev 15", 337 }; 338 339 /* Steppings for PXA2[15]0 */ 340 static const char * const pxa2x0_steppings[16] = { 341 "step A-0", "step A-1", "step B-0", "step B-1", 342 "step B-2", "step C-0", "rev 6", "rev 7", 343 "rev 8", "rev 9", "rev 10", "rev 11", 344 "rev 12", "rev 13", "rev 14", "rev 15", 345 }; 346 347 /* Steppings for PXA255/26x. 348 * rev 5: PXA26x B0, rev 6: PXA255 A0 349 */ 350 static const char * const pxa255_steppings[16] = { 351 "rev 0", "rev 1", "rev 2", "step A-0", 352 "rev 4", "step B-0", "step A-0", "rev 7", 353 "rev 8", "rev 9", "rev 10", "rev 11", 354 "rev 12", "rev 13", "rev 14", "rev 15", 355 }; 356 357 /* Stepping for PXA27x */ 358 static const char * const pxa27x_steppings[16] = { 359 "step A-0", "step A-1", "step B-0", "step B-1", 360 "step C-0", "rev 5", "rev 6", "rev 7", 361 "rev 8", "rev 9", "rev 10", "rev 11", 362 "rev 12", "rev 13", "rev 14", "rev 15", 363 }; 364 365 static const char * const ixp425_steppings[16] = { 366 "step 0", "rev 1", "rev 2", "rev 3", 367 "rev 4", "rev 5", "rev 6", "rev 7", 368 "rev 8", "rev 9", "rev 10", "rev 11", 369 "rev 12", "rev 13", "rev 14", "rev 15", 370 }; 371 372 struct cpuidtab { 373 uint32_t cpuid; 374 enum cpu_class cpu_class; 375 const char *cpu_classname; 376 const char * const *cpu_steppings; 377 char cpu_arch[8]; 378 }; 379 380 const struct cpuidtab cpuids[] = { 381 { CPU_ID_ARM2, CPU_CLASS_ARM2, "ARM2", 382 generic_steppings, "2" }, 383 { CPU_ID_ARM250, CPU_CLASS_ARM2AS, "ARM250", 384 generic_steppings, "2" }, 385 386 { CPU_ID_ARM3, CPU_CLASS_ARM3, "ARM3", 387 generic_steppings, "2A" }, 388 389 { CPU_ID_ARM600, CPU_CLASS_ARM6, "ARM600", 390 generic_steppings, "3" }, 391 { CPU_ID_ARM610, CPU_CLASS_ARM6, "ARM610", 392 generic_steppings, "3" }, 393 { CPU_ID_ARM620, CPU_CLASS_ARM6, "ARM620", 394 generic_steppings, "3" }, 395 396 { CPU_ID_ARM700, CPU_CLASS_ARM7, "ARM700", 397 generic_steppings, "3" }, 398 { CPU_ID_ARM710, CPU_CLASS_ARM7, "ARM710", 399 generic_steppings, "3" }, 400 { CPU_ID_ARM7500, CPU_CLASS_ARM7, "ARM7500", 401 generic_steppings, "3" }, 402 { CPU_ID_ARM710A, CPU_CLASS_ARM7, "ARM710a", 403 generic_steppings, "3" }, 404 { CPU_ID_ARM7500FE, CPU_CLASS_ARM7, "ARM7500FE", 405 generic_steppings, "3" }, 406 407 { CPU_ID_ARM810, CPU_CLASS_ARM8, "ARM810", 408 generic_steppings, "4" }, 409 410 { CPU_ID_SA110, CPU_CLASS_SA1, "SA-110", 411 sa110_steppings, "4" }, 412 { CPU_ID_SA1100, CPU_CLASS_SA1, "SA-1100", 413 sa1100_steppings, "4" }, 414 { CPU_ID_SA1110, CPU_CLASS_SA1, "SA-1110", 415 sa1110_steppings, "4" }, 416 417 { CPU_ID_FA526, CPU_CLASS_ARMV4, "FA526", 418 generic_steppings, "4" }, 419 420 { CPU_ID_IXP1200, CPU_CLASS_SA1, "IXP1200", 421 ixp12x0_steppings, "4" }, 422 423 { CPU_ID_ARM710T, CPU_CLASS_ARM7TDMI, "ARM710T", 424 generic_steppings, "4T" }, 425 { CPU_ID_ARM720T, CPU_CLASS_ARM7TDMI, "ARM720T", 426 generic_steppings, "4T" }, 427 { CPU_ID_ARM740T8K, CPU_CLASS_ARM7TDMI, "ARM740T (8 KB cache)", 428 generic_steppings, "4T" }, 429 { CPU_ID_ARM740T4K, CPU_CLASS_ARM7TDMI, "ARM740T (4 KB cache)", 430 generic_steppings, "4T" }, 431 { CPU_ID_ARM920T, CPU_CLASS_ARM9TDMI, "ARM920T", 432 generic_steppings, "4T" }, 433 { CPU_ID_ARM922T, CPU_CLASS_ARM9TDMI, "ARM922T", 434 generic_steppings, "4T" }, 435 { CPU_ID_ARM940T, CPU_CLASS_ARM9TDMI, "ARM940T", 436 generic_steppings, "4T" }, 437 { CPU_ID_TI925T, CPU_CLASS_ARM9TDMI, "TI ARM925T", 438 generic_steppings, "4T" }, 439 440 { CPU_ID_ARM946ES, CPU_CLASS_ARM9ES, "ARM946E-S", 441 generic_steppings, "5TE" }, 442 { CPU_ID_ARM966ES, CPU_CLASS_ARM9ES, "ARM966E-S", 443 generic_steppings, "5TE" }, 444 { CPU_ID_ARM966ESR1, CPU_CLASS_ARM9ES, "ARM966E-S", 445 generic_steppings, "5TE" }, 446 { CPU_ID_MV88SV131, CPU_CLASS_ARM9ES, "Sheeva 88SV131", 447 generic_steppings, "5TE" }, 448 { CPU_ID_MV88FR571_VD, CPU_CLASS_ARM9ES, "Sheeva 88FR571-vd", 449 generic_steppings, "5TE" }, 450 451 { CPU_ID_80200, CPU_CLASS_XSCALE, "i80200", 452 xscale_steppings, "5TE" }, 453 454 { CPU_ID_80321_400, CPU_CLASS_XSCALE, "i80321 400MHz", 455 i80321_steppings, "5TE" }, 456 { CPU_ID_80321_600, CPU_CLASS_XSCALE, "i80321 600MHz", 457 i80321_steppings, "5TE" }, 458 { CPU_ID_80321_400_B0, CPU_CLASS_XSCALE, "i80321 400MHz", 459 i80321_steppings, "5TE" }, 460 { CPU_ID_80321_600_B0, CPU_CLASS_XSCALE, "i80321 600MHz", 461 i80321_steppings, "5TE" }, 462 463 { CPU_ID_80219_400, CPU_CLASS_XSCALE, "i80219 400MHz", 464 i80219_steppings, "5TE" }, 465 { CPU_ID_80219_600, CPU_CLASS_XSCALE, "i80219 600MHz", 466 i80219_steppings, "5TE" }, 467 468 { CPU_ID_PXA27X, CPU_CLASS_XSCALE, "PXA27x", 469 pxa27x_steppings, "5TE" }, 470 { CPU_ID_PXA250A, CPU_CLASS_XSCALE, "PXA250", 471 pxa2x0_steppings, "5TE" }, 472 { CPU_ID_PXA210A, CPU_CLASS_XSCALE, "PXA210", 473 pxa2x0_steppings, "5TE" }, 474 { CPU_ID_PXA250B, CPU_CLASS_XSCALE, "PXA250", 475 pxa2x0_steppings, "5TE" }, 476 { CPU_ID_PXA210B, CPU_CLASS_XSCALE, "PXA210", 477 pxa2x0_steppings, "5TE" }, 478 { CPU_ID_PXA250C, CPU_CLASS_XSCALE, "PXA255/26x", 479 pxa255_steppings, "5TE" }, 480 { CPU_ID_PXA210C, CPU_CLASS_XSCALE, "PXA210", 481 pxa2x0_steppings, "5TE" }, 482 483 { CPU_ID_IXP425_533, CPU_CLASS_XSCALE, "IXP425 533MHz", 484 ixp425_steppings, "5TE" }, 485 { CPU_ID_IXP425_400, CPU_CLASS_XSCALE, "IXP425 400MHz", 486 ixp425_steppings, "5TE" }, 487 { CPU_ID_IXP425_266, CPU_CLASS_XSCALE, "IXP425 266MHz", 488 ixp425_steppings, "5TE" }, 489 490 { CPU_ID_ARM1020E, CPU_CLASS_ARM10E, "ARM1020E", 491 generic_steppings, "5TE" }, 492 { CPU_ID_ARM1022ES, CPU_CLASS_ARM10E, "ARM1022E-S", 493 generic_steppings, "5TE" }, 494 495 { CPU_ID_ARM1026EJS, CPU_CLASS_ARM10EJ, "ARM1026EJ-S", 496 generic_steppings, "5TEJ" }, 497 { CPU_ID_ARM926EJS, CPU_CLASS_ARM9EJS, "ARM926EJ-S", 498 generic_steppings, "5TEJ" }, 499 500 { CPU_ID_ARM1136JS, CPU_CLASS_ARM11J, "ARM1136J-S r0", 501 pN_steppings, "6J" }, 502 { CPU_ID_ARM1136JSR1, CPU_CLASS_ARM11J, "ARM1136J-S r1", 503 pN_steppings, "6J" }, 504 #if 0 505 /* The ARM1156T2-S only has a memory protection unit */ 506 { CPU_ID_ARM1156T2S, CPU_CLASS_ARM11J, "ARM1156T2-S r0", 507 pN_steppings, "6T2" }, 508 #endif 509 { CPU_ID_ARM1176JZS, CPU_CLASS_ARM11J, "ARM1176JZ-S r0", 510 pN_steppings, "6ZK" }, 511 512 { CPU_ID_ARM11MPCORE, CPU_CLASS_ARM11J, "ARM11 MPCore", 513 generic_steppings, "6K" }, 514 515 { CPU_ID_CORTEXA5R0, CPU_CLASS_CORTEX, "Cortex-A5 r0", 516 pN_steppings, "7A" }, 517 { CPU_ID_CORTEXA7R0, CPU_CLASS_CORTEX, "Cortex-A7 r0", 518 pN_steppings, "7A" }, 519 { CPU_ID_CORTEXA8R1, CPU_CLASS_CORTEX, "Cortex-A8 r1", 520 pN_steppings, "7A" }, 521 { CPU_ID_CORTEXA8R2, CPU_CLASS_CORTEX, "Cortex-A8 r2", 522 pN_steppings, "7A" }, 523 { CPU_ID_CORTEXA8R3, CPU_CLASS_CORTEX, "Cortex-A8 r3", 524 pN_steppings, "7A" }, 525 { CPU_ID_CORTEXA9R1, CPU_CLASS_CORTEX, "Cortex-A9 r1", 526 pN_steppings, "7A" }, 527 { CPU_ID_CORTEXA9R2, CPU_CLASS_CORTEX, "Cortex-A9 r2", 528 pN_steppings, "7A" }, 529 { CPU_ID_CORTEXA9R3, CPU_CLASS_CORTEX, "Cortex-A9 r3", 530 pN_steppings, "7A" }, 531 { CPU_ID_CORTEXA9R4, CPU_CLASS_CORTEX, "Cortex-A9 r4", 532 pN_steppings, "7A" }, 533 { CPU_ID_CORTEXA12R0, CPU_CLASS_CORTEX, "Cortex-A17(A12) r0", /* A12 was rebranded A17 */ 534 pN_steppings, "7A" }, 535 { CPU_ID_CORTEXA15R2, CPU_CLASS_CORTEX, "Cortex-A15 r2", 536 pN_steppings, "7A" }, 537 { CPU_ID_CORTEXA15R3, CPU_CLASS_CORTEX, "Cortex-A15 r3", 538 pN_steppings, "7A" }, 539 { CPU_ID_CORTEXA15R4, CPU_CLASS_CORTEX, "Cortex-A15 r4", 540 pN_steppings, "7A" }, 541 { CPU_ID_CORTEXA17R1, CPU_CLASS_CORTEX, "Cortex-A17 r1", 542 pN_steppings, "7A" }, 543 { CPU_ID_CORTEXA35R0, CPU_CLASS_CORTEX, "Cortex-A35 r0", 544 pN_steppings, "8A" }, 545 { CPU_ID_CORTEXA53R0, CPU_CLASS_CORTEX, "Cortex-A53 r0", 546 pN_steppings, "8A" }, 547 { CPU_ID_CORTEXA57R0, CPU_CLASS_CORTEX, "Cortex-A57 r0", 548 pN_steppings, "8A" }, 549 { CPU_ID_CORTEXA57R1, CPU_CLASS_CORTEX, "Cortex-A57 r1", 550 pN_steppings, "8A" }, 551 { CPU_ID_CORTEXA72R0, CPU_CLASS_CORTEX, "Cortex-A72 r0", 552 pN_steppings, "8A" }, 553 554 { CPU_ID_MV88SV581X_V6, CPU_CLASS_PJ4B, "Sheeva 88SV581x", 555 generic_steppings }, 556 { CPU_ID_ARM_88SV581X_V6, CPU_CLASS_PJ4B, "Sheeva 88SV581x", 557 generic_steppings }, 558 { CPU_ID_MV88SV581X_V7, CPU_CLASS_PJ4B, "Sheeva 88SV581x", 559 generic_steppings }, 560 { CPU_ID_ARM_88SV581X_V7, CPU_CLASS_PJ4B, "Sheeva 88SV581x", 561 generic_steppings }, 562 { CPU_ID_MV88SV584X_V6, CPU_CLASS_PJ4B, "Sheeva 88SV584x", 563 generic_steppings }, 564 { CPU_ID_ARM_88SV584X_V6, CPU_CLASS_PJ4B, "Sheeva 88SV584x", 565 generic_steppings }, 566 { CPU_ID_MV88SV584X_V7, CPU_CLASS_PJ4B, "Sheeva 88SV584x", 567 generic_steppings }, 568 569 570 { 0, CPU_CLASS_NONE, NULL, NULL, "" } 571 }; 572 573 struct cpu_classtab { 574 const char *class_name; 575 const char *class_option; 576 }; 577 578 const struct cpu_classtab cpu_classes[] = { 579 [CPU_CLASS_NONE] = { "unknown", NULL }, 580 [CPU_CLASS_ARM2] = { "ARM2", "CPU_ARM2" }, 581 [CPU_CLASS_ARM2AS] = { "ARM2as", "CPU_ARM250" }, 582 [CPU_CLASS_ARM3] = { "ARM3", "CPU_ARM3" }, 583 [CPU_CLASS_ARM6] = { "ARM6", "CPU_ARM6" }, 584 [CPU_CLASS_ARM7] = { "ARM7", "CPU_ARM7" }, 585 [CPU_CLASS_ARM7TDMI] = { "ARM7TDMI", "CPU_ARM7TDMI" }, 586 [CPU_CLASS_ARM8] = { "ARM8", "CPU_ARM8" }, 587 [CPU_CLASS_ARM9TDMI] = { "ARM9TDMI", NULL }, 588 [CPU_CLASS_ARM9ES] = { "ARM9E-S", "CPU_ARM9E" }, 589 [CPU_CLASS_ARM9EJS] = { "ARM9EJ-S", "CPU_ARM9E" }, 590 [CPU_CLASS_ARM10E] = { "ARM10E", "CPU_ARM10" }, 591 [CPU_CLASS_ARM10EJ] = { "ARM10EJ", "CPU_ARM10" }, 592 [CPU_CLASS_SA1] = { "SA-1", "CPU_SA110" }, 593 [CPU_CLASS_XSCALE] = { "XScale", "CPU_XSCALE_..." }, 594 [CPU_CLASS_ARM11J] = { "ARM11J", "CPU_ARM11" }, 595 [CPU_CLASS_ARMV4] = { "ARMv4", "CPU_ARMV4" }, 596 [CPU_CLASS_CORTEX] = { "Cortex", "CPU_CORTEX" }, 597 [CPU_CLASS_PJ4B] = { "Marvell", "CPU_PJ4B" }, 598 }; 599 600 /* 601 * Report the type of the specified arm processor. This uses the generic and 602 * arm specific information in the CPU structure to identify the processor. 603 * The remaining fields in the CPU structure are filled in appropriately. 604 */ 605 606 static const char * const wtnames[] = { 607 "write-through", 608 "write-back", 609 "write-back", 610 "**unknown 3**", 611 "**unknown 4**", 612 "write-back-locking", /* XXX XScale-specific? */ 613 "write-back-locking-A", 614 "write-back-locking-B", 615 "**unknown 8**", 616 "**unknown 9**", 617 "**unknown 10**", 618 "**unknown 11**", 619 "write-back", 620 "write-back-locking-line", 621 "write-back-locking-C", 622 "write-back-locking-D", 623 }; 624 625 static void 626 print_cache_info(device_t dv, struct arm_cache_info *info, u_int level) 627 { 628 if (info->cache_unified) { 629 aprint_normal_dev(dv, "%dKB/%dB %d-way %s L%u %cI%cT Unified cache\n", 630 info->dcache_size / 1024, 631 info->dcache_line_size, info->dcache_ways, 632 wtnames[info->cache_type], level + 1, 633 info->dcache_type & CACHE_TYPE_PIxx ? 'P' : 'V', 634 info->dcache_type & CACHE_TYPE_xxPT ? 'P' : 'V'); 635 } else { 636 aprint_normal_dev(dv, "%dKB/%dB %d-way L%u %cI%cT Instruction cache\n", 637 info->icache_size / 1024, 638 info->icache_line_size, info->icache_ways, level + 1, 639 info->icache_type & CACHE_TYPE_PIxx ? 'P' : 'V', 640 info->icache_type & CACHE_TYPE_xxPT ? 'P' : 'V'); 641 aprint_normal_dev(dv, "%dKB/%dB %d-way %s L%u %cI%cT Data cache\n", 642 info->dcache_size / 1024, 643 info->dcache_line_size, info->dcache_ways, 644 wtnames[info->cache_type], level + 1, 645 info->dcache_type & CACHE_TYPE_PIxx ? 'P' : 'V', 646 info->dcache_type & CACHE_TYPE_xxPT ? 'P' : 'V'); 647 } 648 } 649 650 static enum cpu_class 651 identify_arm_model(uint32_t cpuid, char *buf, size_t len) 652 { 653 enum cpu_class cpu_class = CPU_CLASS_NONE; 654 for (const struct cpuidtab *id = cpuids; id->cpuid != 0; id++) { 655 if (id->cpuid == (cpuid & CPU_ID_CPU_MASK)) { 656 const char *steppingstr = 657 id->cpu_steppings[cpuid & CPU_ID_REVISION_MASK]; 658 cpu_arch = id->cpu_arch; 659 cpu_class = id->cpu_class; 660 snprintf(buf, len, "%s%s%s (%s V%s core)", 661 id->cpu_classname, 662 steppingstr[0] == '*' ? "" : " ", 663 &steppingstr[steppingstr[0] == '*'], 664 cpu_classes[cpu_class].class_name, 665 cpu_arch); 666 return cpu_class; 667 } 668 } 669 670 snprintf(buf, len, "unknown CPU (ID = 0x%x)", cpuid); 671 return cpu_class; 672 } 673 674 void 675 identify_arm_cpu(device_t dv, struct cpu_info *ci) 676 { 677 const uint32_t arm_cpuid = ci->ci_arm_cpuid; 678 const char * const xname = device_xname(dv); 679 char model[128]; 680 681 if (arm_cpuid == 0) { 682 aprint_error("Processor failed probe - no CPU ID\n"); 683 return; 684 } 685 686 const enum cpu_class cpu_class = identify_arm_model(arm_cpuid, 687 model, sizeof(model)); 688 if (ci->ci_cpuid == 0) { 689 cpu_setmodel("%s", model); 690 } 691 692 if (ci->ci_data.cpu_cc_freq != 0) { 693 char freqbuf[10]; 694 humanize_number(freqbuf, sizeof(freqbuf), ci->ci_data.cpu_cc_freq, 695 "Hz", 1000); 696 697 aprint_naive(": %s %s\n", freqbuf, model); 698 aprint_normal(": %s %s\n", freqbuf, model); 699 } else { 700 aprint_naive(": %s\n", model); 701 aprint_normal(": %s\n", model); 702 } 703 704 aprint_debug_dev(dv, "midr: %#x\n", arm_cpuid); 705 706 aprint_normal("%s:", xname); 707 708 switch (cpu_class) { 709 case CPU_CLASS_ARM6: 710 case CPU_CLASS_ARM7: 711 case CPU_CLASS_ARM7TDMI: 712 case CPU_CLASS_ARM8: 713 if ((ci->ci_ctrl & CPU_CONTROL_IDC_ENABLE) == 0) 714 aprint_normal(" IDC disabled"); 715 else 716 aprint_normal(" IDC enabled"); 717 break; 718 case CPU_CLASS_ARM9TDMI: 719 case CPU_CLASS_ARM9ES: 720 case CPU_CLASS_ARM9EJS: 721 case CPU_CLASS_ARM10E: 722 case CPU_CLASS_ARM10EJ: 723 case CPU_CLASS_SA1: 724 case CPU_CLASS_XSCALE: 725 case CPU_CLASS_ARM11J: 726 case CPU_CLASS_ARMV4: 727 case CPU_CLASS_CORTEX: 728 case CPU_CLASS_PJ4B: 729 if ((ci->ci_ctrl & CPU_CONTROL_DC_ENABLE) == 0) 730 aprint_normal(" DC disabled"); 731 else 732 aprint_normal(" DC enabled"); 733 if ((ci->ci_ctrl & CPU_CONTROL_IC_ENABLE) == 0) 734 aprint_normal(" IC disabled"); 735 else 736 aprint_normal(" IC enabled"); 737 break; 738 default: 739 break; 740 } 741 if ((ci->ci_ctrl & CPU_CONTROL_WBUF_ENABLE) == 0) 742 aprint_normal(" WB disabled"); 743 else 744 aprint_normal(" WB enabled"); 745 746 if (ci->ci_ctrl & CPU_CONTROL_LABT_ENABLE) 747 aprint_normal(" LABT"); 748 else 749 aprint_normal(" EABT"); 750 751 if (ci->ci_ctrl & CPU_CONTROL_BPRD_ENABLE) 752 aprint_normal(" branch prediction enabled"); 753 754 aprint_normal("\n"); 755 756 if (CPU_ID_CORTEX_P(arm_cpuid) || CPU_ID_ARM11_P(arm_cpuid) || CPU_ID_MV88SV58XX_P(arm_cpuid)) { 757 identify_features(dv); 758 } 759 760 /* Print cache info. */ 761 if (arm_pcache.icache_line_size != 0 || arm_pcache.dcache_line_size != 0) { 762 print_cache_info(dv, &arm_pcache, 0); 763 } 764 if (arm_scache.icache_line_size != 0 || arm_scache.dcache_line_size != 0) { 765 print_cache_info(dv, &arm_scache, 1); 766 } 767 768 769 switch (cpu_class) { 770 #ifdef CPU_ARM6 771 case CPU_CLASS_ARM6: 772 #endif 773 #ifdef CPU_ARM7 774 case CPU_CLASS_ARM7: 775 #endif 776 #ifdef CPU_ARM7TDMI 777 case CPU_CLASS_ARM7TDMI: 778 #endif 779 #ifdef CPU_ARM8 780 case CPU_CLASS_ARM8: 781 #endif 782 #ifdef CPU_ARM9 783 case CPU_CLASS_ARM9TDMI: 784 #endif 785 #if defined(CPU_ARM9E) || defined(CPU_SHEEVA) 786 case CPU_CLASS_ARM9ES: 787 case CPU_CLASS_ARM9EJS: 788 #endif 789 #ifdef CPU_ARM10 790 case CPU_CLASS_ARM10E: 791 case CPU_CLASS_ARM10EJ: 792 #endif 793 #if defined(CPU_SA110) || defined(CPU_SA1100) || \ 794 defined(CPU_SA1110) || defined(CPU_IXP12X0) 795 case CPU_CLASS_SA1: 796 #endif 797 #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 798 defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425) 799 case CPU_CLASS_XSCALE: 800 #endif 801 #if defined(CPU_ARM11) 802 case CPU_CLASS_ARM11J: 803 #endif 804 #if defined(CPU_CORTEX) 805 case CPU_CLASS_CORTEX: 806 #endif 807 #if defined(CPU_PJ4B) 808 case CPU_CLASS_PJ4B: 809 #endif 810 #if defined(CPU_FA526) 811 case CPU_CLASS_ARMV4: 812 #endif 813 break; 814 default: 815 if (cpu_classes[cpu_class].class_option == NULL) { 816 aprint_error_dev(dv, "%s does not fully support this CPU.\n", 817 ostype); 818 } else { 819 aprint_error_dev(dv, "This kernel does not fully support " 820 "this CPU.\n"); 821 aprint_normal_dev(dv, "Recompile with \"options %s\" to " 822 "correct this.\n", cpu_classes[cpu_class].class_option); 823 } 824 break; 825 } 826 } 827 828 extern int cpu_instruction_set_attributes[6]; 829 extern int cpu_memory_model_features[4]; 830 extern int cpu_processor_features[2]; 831 extern int cpu_simd_present; 832 extern int cpu_simdex_present; 833 834 void 835 identify_features(device_t dv) 836 { 837 cpu_instruction_set_attributes[0] = armreg_isar0_read(); 838 cpu_instruction_set_attributes[1] = armreg_isar1_read(); 839 cpu_instruction_set_attributes[2] = armreg_isar2_read(); 840 cpu_instruction_set_attributes[3] = armreg_isar3_read(); 841 cpu_instruction_set_attributes[4] = armreg_isar4_read(); 842 cpu_instruction_set_attributes[5] = armreg_isar5_read(); 843 844 cpu_hwdiv_present = 845 ((cpu_instruction_set_attributes[0] >> 24) & 0x0f) >= 2; 846 cpu_simd_present = 847 ((cpu_instruction_set_attributes[3] >> 4) & 0x0f) >= 3; 848 cpu_simdex_present = cpu_simd_present 849 && ((cpu_instruction_set_attributes[1] >> 12) & 0x0f) >= 2; 850 cpu_synchprim_present = 851 ((cpu_instruction_set_attributes[3] >> 8) & 0xf0) 852 | ((cpu_instruction_set_attributes[4] >> 20) & 0x0f); 853 854 cpu_memory_model_features[0] = armreg_mmfr0_read(); 855 cpu_memory_model_features[1] = armreg_mmfr1_read(); 856 cpu_memory_model_features[2] = armreg_mmfr2_read(); 857 cpu_memory_model_features[3] = armreg_mmfr3_read(); 858 859 #if 0 860 if (__SHIFTOUT(cpu_memory_model_features[3], __BITS(23,20))) { 861 /* 862 * Updates to the translation tables do not require a clean 863 * to the point of unification to ensure visibility by 864 * subsequent translation table walks. 865 */ 866 pmap_needs_pte_sync = 0; 867 } 868 #endif 869 870 cpu_processor_features[0] = armreg_pfr0_read(); 871 cpu_processor_features[1] = armreg_pfr1_read(); 872 873 aprint_debug_dev(dv, "sctlr: %#x\n", armreg_sctlr_read()); 874 aprint_debug_dev(dv, "actlr: %#x\n", armreg_auxctl_read()); 875 aprint_debug_dev(dv, "revidr: %#x\n", armreg_revidr_read()); 876 #ifdef MULTIPROCESSOR 877 aprint_debug_dev(dv, "mpidr: %#x\n", armreg_mpidr_read()); 878 #endif 879 aprint_debug_dev(dv, 880 "isar: [0]=%#x [1]=%#x [2]=%#x [3]=%#x, [4]=%#x, [5]=%#x\n", 881 cpu_instruction_set_attributes[0], 882 cpu_instruction_set_attributes[1], 883 cpu_instruction_set_attributes[2], 884 cpu_instruction_set_attributes[3], 885 cpu_instruction_set_attributes[4], 886 cpu_instruction_set_attributes[5]); 887 aprint_debug_dev(dv, 888 "mmfr: [0]=%#x [1]=%#x [2]=%#x [3]=%#x\n", 889 cpu_memory_model_features[0], cpu_memory_model_features[1], 890 cpu_memory_model_features[2], cpu_memory_model_features[3]); 891 aprint_debug_dev(dv, 892 "pfr: [0]=%#x [1]=%#x\n", 893 cpu_processor_features[0], cpu_processor_features[1]); 894 } 895
Indexes created Tue Oct 21 16:10:11 GMT 2025