cpu.c revision 1.27
1 /* $NetBSD: cpu.c,v 1.27 2002/03/11 11:50:12 reinoud Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Mark Brinicombe. 5 * Copyright (c) 1995 Brini. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Brini. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * cpu.c 38 * 39 * Probing and configuration for the master cpu 40 * 41 * Created : 10/10/95 42 */ 43 44 #include "opt_armfpe.h" 45 #include "opt_cputypes.h" 46 47 #include <sys/param.h> 48 49 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.27 2002/03/11 11:50:12 reinoud Exp $"); 50 51 #include <sys/systm.h> 52 #include <sys/malloc.h> 53 #include <sys/device.h> 54 #include <sys/proc.h> 55 #include <uvm/uvm_extern.h> 56 #include <machine/conf.h> 57 #include <machine/cpu.h> 58 #include <arm/undefined.h> 59 60 #ifdef ARMFPE 61 #include <machine/bootconfig.h> /* For boot args */ 62 #include <arm/fpe-arm/armfpe.h> 63 #endif 64 65 char cpu_model[256]; 66 67 /* Prototypes */ 68 void identify_arm_cpu(struct device *dv, struct cpu_info *); 69 70 /* 71 * Identify the master (boot) CPU 72 */ 73 74 void 75 cpu_attach(struct device *dv) 76 { 77 int usearmfpe; 78 79 usearmfpe = 1; /* when compiled in, its enabled by default */ 80 81 curcpu()->ci_dev = dv; 82 83 evcnt_attach_dynamic(&curcpu()->ci_arm700bugcount, EVCNT_TYPE_MISC, 84 NULL, dv->dv_xname, "arm700swibug"); 85 86 /* Get the cpu ID from coprocessor 15 */ 87 88 curcpu()->ci_cpuid = cpu_id(); 89 90 identify_arm_cpu(dv, curcpu()); 91 92 if ((curcpu()->ci_cpuid & CPU_ID_CPU_MASK) == CPU_ID_SA110 93 && (curcpu()->ci_cpuid & CPU_ID_REVISION_MASK) < 3) { 94 printf("%s: SA-110 with bugged STM^ instruction\n", 95 dv->dv_xname); 96 } 97 98 #ifdef CPU_ARM8 99 if ((curcpu()->ci_cpuid & CPU_ID_CPU_MASK) == CPU_ID_ARM810) { 100 int clock = arm8_clock_config(0, 0); 101 char *fclk; 102 printf("%s: ARM810 cp15=%02x", dv->dv_xname, clock); 103 printf(" clock:%s", (clock & 1) ? " dynamic" : ""); 104 printf("%s", (clock & 2) ? " sync" : ""); 105 switch ((clock >> 2) & 3) { 106 case 0: 107 fclk = "bus clock"; 108 break; 109 case 1: 110 fclk = "ref clock"; 111 break; 112 case 3: 113 fclk = "pll"; 114 break; 115 default: 116 fclk = "illegal"; 117 break; 118 } 119 printf(" fclk source=%s\n", fclk); 120 } 121 #endif 122 123 #ifdef ARMFPE 124 /* 125 * Ok now we test for an FPA 126 * At this point no floating point emulator has been installed. 127 * This means any FP instruction will cause undefined exception. 128 * We install a temporay coproc 1 handler which will modify 129 * undefined_test if it is called. 130 * We then try to read the FP status register. If undefined_test 131 * has been decremented then the instruction was not handled by 132 * an FPA so we know the FPA is missing. If undefined_test is 133 * still 1 then we know the instruction was handled by an FPA. 134 * We then remove our test handler and look at the 135 * FP status register for identification. 136 */ 137 138 /* 139 * Ok if ARMFPE is defined and the boot options request the 140 * ARM FPE then it will be installed as the FPE. 141 * This is just while I work on integrating the new FPE. 142 * It means the new FPE gets installed if compiled int (ARMFPE 143 * defined) and also gives me a on/off option when I boot in 144 * case the new FPE is causing panics. 145 */ 146 147 148 if (boot_args) 149 get_bootconf_option(boot_args, "armfpe", 150 BOOTOPT_TYPE_BOOLEAN, &usearmfpe); 151 if (usearmfpe) 152 initialise_arm_fpe(); 153 #endif 154 } 155 156 enum cpu_class { 157 CPU_CLASS_NONE, 158 CPU_CLASS_ARM2, 159 CPU_CLASS_ARM2AS, 160 CPU_CLASS_ARM3, 161 CPU_CLASS_ARM6, 162 CPU_CLASS_ARM7, 163 CPU_CLASS_ARM7TDMI, 164 CPU_CLASS_ARM8, 165 CPU_CLASS_ARM9TDMI, 166 CPU_CLASS_ARM9ES, 167 CPU_CLASS_SA1, 168 CPU_CLASS_XSCALE, 169 }; 170 171 static const char *generic_steppings[16] = { 172 "rev 0", "rev 1", "rev 2", "rev 3", 173 "rev 4", "rev 5", "rev 6", "rev 7", 174 "rev 8", "rev 9", "rev 10", "rev 11", 175 "rev 12", "rev 13", "rev 14", "rev 15", 176 }; 177 178 static const char *sa110_steppings[16] = { 179 "rev 0", "step J", "step K", "step S", 180 "step T", "rev 5", "rev 6", "rev 7", 181 "rev 8", "rev 9", "rev 10", "rev 11", 182 "rev 12", "rev 13", "rev 14", "rev 15", 183 }; 184 185 static const char *sa1100_steppings[16] = { 186 "rev 0", "step B", "step C", "rev 3", 187 "rev 4", "rev 5", "rev 6", "rev 7", 188 "step D", "step E", "rev 10" "step G", 189 "rev 12", "rev 13", "rev 14", "rev 15", 190 }; 191 192 static const char *sa1110_steppings[16] = { 193 "step A-0", "rev 1", "rev 2", "rev 3", 194 "step B-0", "step B-1", "step B-2", "step B-3", 195 "step B-4", "step B-5", "rev 10", "rev 11", 196 "rev 12", "rev 13", "rev 14", "rev 15", 197 }; 198 199 static const char *i80200_steppings[16] = { 200 "step A-0", "step A-1", "step B-0", "step C-0", 201 "rev 4", "rev 5", "rev 6", "rev 7", 202 "rev 8", "rev 9", "rev 10", "rev 11", 203 "rev 12", "rev 13", "rev 14", "rev 15", 204 }; 205 206 struct cpuidtab { 207 u_int32_t cpuid; 208 enum cpu_class cpu_class; 209 const char *cpu_name; 210 const char **cpu_steppings; 211 }; 212 213 const struct cpuidtab cpuids[] = { 214 { CPU_ID_ARM2, CPU_CLASS_ARM2, "ARM2", 215 generic_steppings }, 216 { CPU_ID_ARM250, CPU_CLASS_ARM2AS, "ARM250", 217 generic_steppings }, 218 219 { CPU_ID_ARM3, CPU_CLASS_ARM3, "ARM3", 220 generic_steppings }, 221 222 { CPU_ID_ARM600, CPU_CLASS_ARM6, "ARM600", 223 generic_steppings }, 224 { CPU_ID_ARM610, CPU_CLASS_ARM6, "ARM610", 225 generic_steppings }, 226 { CPU_ID_ARM620, CPU_CLASS_ARM6, "ARM620", 227 generic_steppings }, 228 229 { CPU_ID_ARM700, CPU_CLASS_ARM7, "ARM700", 230 generic_steppings }, 231 { CPU_ID_ARM710, CPU_CLASS_ARM7, "ARM710", 232 generic_steppings }, 233 { CPU_ID_ARM7500, CPU_CLASS_ARM7, "ARM7500", 234 generic_steppings }, 235 { CPU_ID_ARM710A, CPU_CLASS_ARM7, "ARM710a", 236 generic_steppings }, 237 { CPU_ID_ARM7500FE, CPU_CLASS_ARM7, "ARM7500FE", 238 generic_steppings }, 239 { CPU_ID_ARM710T, CPU_CLASS_ARM7TDMI, "ARM710T", 240 generic_steppings }, 241 { CPU_ID_ARM720T, CPU_CLASS_ARM7TDMI, "ARM720T", 242 generic_steppings }, 243 { CPU_ID_ARM740T8K, CPU_CLASS_ARM7TDMI, "ARM740T (8 KB cache)", 244 generic_steppings }, 245 { CPU_ID_ARM740T4K, CPU_CLASS_ARM7TDMI, "ARM740T (4 KB cache)", 246 generic_steppings }, 247 248 { CPU_ID_ARM810, CPU_CLASS_ARM8, "ARM810", 249 generic_steppings }, 250 251 { CPU_ID_ARM920T, CPU_CLASS_ARM9TDMI, "ARM920T", 252 generic_steppings }, 253 { CPU_ID_ARM922T, CPU_CLASS_ARM9TDMI, "ARM922T", 254 generic_steppings }, 255 { CPU_ID_ARM940T, CPU_CLASS_ARM9TDMI, "ARM940T", 256 generic_steppings }, 257 { CPU_ID_ARM946ES, CPU_CLASS_ARM9ES, "ARM946E-S", 258 generic_steppings }, 259 { CPU_ID_ARM966ES, CPU_CLASS_ARM9ES, "ARM966E-S", 260 generic_steppings }, 261 { CPU_ID_ARM966ESR1, CPU_CLASS_ARM9ES, "ARM966E-S", 262 generic_steppings }, 263 264 { CPU_ID_SA110, CPU_CLASS_SA1, "SA-110", 265 sa110_steppings }, 266 { CPU_ID_SA1100, CPU_CLASS_SA1, "SA-1100", 267 sa1100_steppings }, 268 { CPU_ID_SA1110, CPU_CLASS_SA1, "SA-1110", 269 sa1110_steppings }, 270 271 { CPU_ID_I80200, CPU_CLASS_XSCALE, "i80200", 272 i80200_steppings }, 273 274 { 0, CPU_CLASS_NONE, NULL, NULL } 275 }; 276 277 struct cpu_classtab { 278 const char *class_name; 279 const char *class_option; 280 }; 281 282 const struct cpu_classtab cpu_classes[] = { 283 { "unknown", NULL }, /* CPU_CLASS_NONE */ 284 { "ARM2", "CPU_ARM2" }, /* CPU_CLASS_ARM2 */ 285 { "ARM2as", "CPU_ARM250" }, /* CPU_CLASS_ARM2AS */ 286 { "ARM3", "CPU_ARM3" }, /* CPU_CLASS_ARM3 */ 287 { "ARM6", "CPU_ARM6" }, /* CPU_CLASS_ARM6 */ 288 { "ARM7", "CPU_ARM7" }, /* CPU_CLASS_ARM7 */ 289 { "ARM7TDMI", "CPU_ARM7TDMI" }, /* CPU_CLASS_ARM7TDMI */ 290 { "ARM8", "CPU_ARM8" }, /* CPU_CLASS_ARM8 */ 291 { "ARM9TDMI", NULL }, /* CPU_CLASS_ARM9TDMI */ 292 { "ARM9E-S", NULL }, /* CPU_CLASS_ARM9ES */ 293 { "SA-1", "CPU_SA110" }, /* CPU_CLASS_SA1 */ 294 { "XScale", "CPU_XSCALE" }, /* CPU_CLASS_XSCALE */ 295 }; 296 297 /* 298 * Report the type of the specifed arm processor. This uses the generic and 299 * arm specific information in the cpu structure to identify the processor. 300 * The remaining fields in the cpu structure are filled in appropriately. 301 */ 302 303 static const char *wtnames[] = { 304 "write-through", 305 "write-back", 306 "write-back", 307 "**unknown 3**", 308 "**unknown 4**", 309 "write-back-locking", /* XXX XScale-specific? */ 310 "write-back-locking-A", 311 "write-back-locking-B", 312 "**unknown 8**", 313 "**unknown 9**", 314 "**unknown 10**", 315 "**unknown 11**", 316 "**unknown 12**", 317 "**unknown 13**", 318 "**unknown 14**", 319 "**unknown 15**", 320 }; 321 322 void 323 identify_arm_cpu(struct device *dv, struct cpu_info *ci) 324 { 325 u_int cpuid; 326 enum cpu_class cpu_class; 327 int i; 328 329 cpuid = ci->ci_cpuid; 330 331 if (cpuid == 0) { 332 printf("Processor failed probe - no CPU ID\n"); 333 return; 334 } 335 336 for (i = 0; cpuids[i].cpuid != 0; i++) 337 if (cpuids[i].cpuid == (cpuid & CPU_ID_CPU_MASK)) { 338 cpu_class = cpuids[i].cpu_class; 339 sprintf(cpu_model, "%s %s (%s core)", 340 cpuids[i].cpu_name, 341 cpuids[i].cpu_steppings[cpuid & 342 CPU_ID_REVISION_MASK], 343 cpu_classes[cpu_class].class_name); 344 break; 345 } 346 347 if (cpuids[i].cpuid == 0) 348 sprintf(cpu_model, "unknown CPU (ID = 0x%x)", cpuid); 349 350 switch (cpu_class) { 351 case CPU_CLASS_ARM6: 352 case CPU_CLASS_ARM7: 353 case CPU_CLASS_ARM7TDMI: 354 case CPU_CLASS_ARM8: 355 if ((ci->ci_ctrl & CPU_CONTROL_IDC_ENABLE) == 0) 356 strcat(cpu_model, " IDC disabled"); 357 else 358 strcat(cpu_model, " IDC enabled"); 359 break; 360 case CPU_CLASS_ARM9TDMI: 361 case CPU_CLASS_SA1: 362 case CPU_CLASS_XSCALE: 363 if ((ci->ci_ctrl & CPU_CONTROL_DC_ENABLE) == 0) 364 strcat(cpu_model, " DC disabled"); 365 else 366 strcat(cpu_model, " DC enabled"); 367 if ((ci->ci_ctrl & CPU_CONTROL_IC_ENABLE) == 0) 368 strcat(cpu_model, " IC disabled"); 369 else 370 strcat(cpu_model, " IC enabled"); 371 break; 372 default: 373 break; 374 } 375 if ((ci->ci_ctrl & CPU_CONTROL_WBUF_ENABLE) == 0) 376 strcat(cpu_model, " WB disabled"); 377 else 378 strcat(cpu_model, " WB enabled"); 379 380 if (ci->ci_ctrl & CPU_CONTROL_LABT_ENABLE) 381 strcat(cpu_model, " LABT"); 382 else 383 strcat(cpu_model, " EABT"); 384 385 if (ci->ci_ctrl & CPU_CONTROL_BPRD_ENABLE) 386 strcat(cpu_model, " branch prediction enabled"); 387 388 /* Print the info */ 389 printf(": %s\n", cpu_model); 390 391 /* Print cache info. */ 392 if (arm_picache_line_size == 0 && arm_pdcache_line_size == 0) 393 goto skip_pcache; 394 395 if (arm_pcache_unified) { 396 printf("%s: %dKB/%dB %d-way %s unified cache\n", 397 dv->dv_xname, arm_pdcache_size / 1024, 398 arm_pdcache_line_size, arm_pdcache_ways, 399 wtnames[arm_pcache_type]); 400 } else { 401 printf("%s: %dKB/%dB %d-way Instruction cache\n", 402 dv->dv_xname, arm_picache_size / 1024, 403 arm_picache_line_size, arm_picache_ways); 404 printf("%s: %dKB/%dB %d-way %s Data cache\n", 405 dv->dv_xname, arm_pdcache_size / 1024, 406 arm_pdcache_line_size, arm_pdcache_ways, 407 wtnames[arm_pcache_type]); 408 } 409 410 skip_pcache: 411 412 switch (cpu_class) { 413 #ifdef CPU_ARM2 414 case CPU_CLASS_ARM2: 415 #endif 416 #ifdef CPU_ARM250 417 case CPU_CLASS_ARM2AS: 418 #endif 419 #ifdef CPU_ARM3 420 case CPU_CLASS_ARM3: 421 #endif 422 #ifdef CPU_ARM6 423 case CPU_CLASS_ARM6: 424 #endif 425 #ifdef CPU_ARM7 426 case CPU_CLASS_ARM7: 427 #endif 428 #ifdef CPU_ARM7TDMI 429 case CPU_CLASS_ARM7TDMI: 430 #endif 431 #ifdef CPU_ARM8 432 case CPU_CLASS_ARM8: 433 #endif 434 #ifdef CPU_ARM9 435 case CPU_CLASS_ARM9TDMI: 436 #endif 437 #ifdef CPU_SA110 438 case CPU_CLASS_SA1: 439 #endif 440 #ifdef CPU_XSCALE 441 case CPU_CLASS_XSCALE: 442 #endif 443 break; 444 default: 445 if (cpu_classes[cpu_class].class_option != NULL) 446 printf("%s: %s does not fully support this CPU." 447 "\n", dv->dv_xname, ostype); 448 else { 449 printf("%s: This kernel does not fully support " 450 "this CPU.\n", dv->dv_xname); 451 printf("%s: Recompile with \"options %s\" to " 452 "correct this.\n", dv->dv_xname, 453 cpu_classes[cpu_class].class_option); 454 } 455 break; 456 } 457 458 } 459 460 /* End of cpu.c */ 461
Indexes created Fri Sep 26 20:09:58 GMT 2025