cpu.c revision 1.29
1 /* $NetBSD: cpu.c,v 1.29 2002/03/16 18:47:51 bjh21 Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Mark Brinicombe. 5 * Copyright (c) 1995 Brini. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Brini. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * cpu.c 38 * 39 * Probing and configuration for the master cpu 40 * 41 * Created : 10/10/95 42 */ 43 44 #include "opt_armfpe.h" 45 #include "opt_cputypes.h" 46 47 #include <sys/param.h> 48 49 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.29 2002/03/16 18:47:51 bjh21 Exp $"); 50 51 #include <sys/systm.h> 52 #include <sys/malloc.h> 53 #include <sys/device.h> 54 #include <sys/proc.h> 55 #include <uvm/uvm_extern.h> 56 #include <machine/conf.h> 57 #include <machine/cpu.h> 58 #include <arm/undefined.h> 59 60 #ifdef ARMFPE 61 #include <machine/bootconfig.h> /* For boot args */ 62 #include <arm/fpe-arm/armfpe.h> 63 #endif 64 65 char cpu_model[256]; 66 67 /* Prototypes */ 68 void identify_arm_cpu(struct device *dv, struct cpu_info *); 69 70 /* 71 * Identify the master (boot) CPU 72 */ 73 74 void 75 cpu_attach(struct device *dv) 76 { 77 int usearmfpe; 78 79 usearmfpe = 1; /* when compiled in, its enabled by default */ 80 81 curcpu()->ci_dev = dv; 82 83 evcnt_attach_dynamic(&curcpu()->ci_arm700bugcount, EVCNT_TYPE_MISC, 84 NULL, dv->dv_xname, "arm700swibug"); 85 86 /* Get the cpu ID from coprocessor 15 */ 87 88 curcpu()->ci_cpuid = cpu_id(); 89 90 identify_arm_cpu(dv, curcpu()); 91 92 if ((curcpu()->ci_cpuid & CPU_ID_CPU_MASK) == CPU_ID_SA110 93 && (curcpu()->ci_cpuid & CPU_ID_REVISION_MASK) < 3) { 94 printf("%s: SA-110 with bugged STM^ instruction\n", 95 dv->dv_xname); 96 } 97 98 #ifdef CPU_ARM8 99 if ((curcpu()->ci_cpuid & CPU_ID_CPU_MASK) == CPU_ID_ARM810) { 100 int clock = arm8_clock_config(0, 0); 101 char *fclk; 102 printf("%s: ARM810 cp15=%02x", dv->dv_xname, clock); 103 printf(" clock:%s", (clock & 1) ? " dynamic" : ""); 104 printf("%s", (clock & 2) ? " sync" : ""); 105 switch ((clock >> 2) & 3) { 106 case 0: 107 fclk = "bus clock"; 108 break; 109 case 1: 110 fclk = "ref clock"; 111 break; 112 case 3: 113 fclk = "pll"; 114 break; 115 default: 116 fclk = "illegal"; 117 break; 118 } 119 printf(" fclk source=%s\n", fclk); 120 } 121 #endif 122 123 #ifdef ARMFPE 124 /* 125 * Ok now we test for an FPA 126 * At this point no floating point emulator has been installed. 127 * This means any FP instruction will cause undefined exception. 128 * We install a temporay coproc 1 handler which will modify 129 * undefined_test if it is called. 130 * We then try to read the FP status register. If undefined_test 131 * has been decremented then the instruction was not handled by 132 * an FPA so we know the FPA is missing. If undefined_test is 133 * still 1 then we know the instruction was handled by an FPA. 134 * We then remove our test handler and look at the 135 * FP status register for identification. 136 */ 137 138 /* 139 * Ok if ARMFPE is defined and the boot options request the 140 * ARM FPE then it will be installed as the FPE. 141 * This is just while I work on integrating the new FPE. 142 * It means the new FPE gets installed if compiled int (ARMFPE 143 * defined) and also gives me a on/off option when I boot in 144 * case the new FPE is causing panics. 145 */ 146 147 148 if (boot_args) 149 get_bootconf_option(boot_args, "armfpe", 150 BOOTOPT_TYPE_BOOLEAN, &usearmfpe); 151 if (usearmfpe) 152 initialise_arm_fpe(); 153 #endif 154 } 155 156 enum cpu_class { 157 CPU_CLASS_NONE, 158 CPU_CLASS_ARM2, 159 CPU_CLASS_ARM2AS, 160 CPU_CLASS_ARM3, 161 CPU_CLASS_ARM6, 162 CPU_CLASS_ARM7, 163 CPU_CLASS_ARM7TDMI, 164 CPU_CLASS_ARM8, 165 CPU_CLASS_ARM9TDMI, 166 CPU_CLASS_ARM9ES, 167 CPU_CLASS_SA1, 168 CPU_CLASS_XSCALE, 169 CPU_CLASS_ARM10E 170 }; 171 172 static const char *generic_steppings[16] = { 173 "rev 0", "rev 1", "rev 2", "rev 3", 174 "rev 4", "rev 5", "rev 6", "rev 7", 175 "rev 8", "rev 9", "rev 10", "rev 11", 176 "rev 12", "rev 13", "rev 14", "rev 15", 177 }; 178 179 static const char *sa110_steppings[16] = { 180 "rev 0", "step J", "step K", "step S", 181 "step T", "rev 5", "rev 6", "rev 7", 182 "rev 8", "rev 9", "rev 10", "rev 11", 183 "rev 12", "rev 13", "rev 14", "rev 15", 184 }; 185 186 static const char *sa1100_steppings[16] = { 187 "rev 0", "step B", "step C", "rev 3", 188 "rev 4", "rev 5", "rev 6", "rev 7", 189 "step D", "step E", "rev 10" "step G", 190 "rev 12", "rev 13", "rev 14", "rev 15", 191 }; 192 193 static const char *sa1110_steppings[16] = { 194 "step A-0", "rev 1", "rev 2", "rev 3", 195 "step B-0", "step B-1", "step B-2", "step B-3", 196 "step B-4", "step B-5", "rev 10", "rev 11", 197 "rev 12", "rev 13", "rev 14", "rev 15", 198 }; 199 200 static const char *i80200_steppings[16] = { 201 "step A-0", "step A-1", "step B-0", "step C-0", 202 "rev 4", "rev 5", "rev 6", "rev 7", 203 "rev 8", "rev 9", "rev 10", "rev 11", 204 "rev 12", "rev 13", "rev 14", "rev 15", 205 }; 206 207 struct cpuidtab { 208 u_int32_t cpuid; 209 enum cpu_class cpu_class; 210 const char *cpu_name; 211 const char **cpu_steppings; 212 }; 213 214 const struct cpuidtab cpuids[] = { 215 { CPU_ID_ARM2, CPU_CLASS_ARM2, "ARM2", 216 generic_steppings }, 217 { CPU_ID_ARM250, CPU_CLASS_ARM2AS, "ARM250", 218 generic_steppings }, 219 220 { CPU_ID_ARM3, CPU_CLASS_ARM3, "ARM3", 221 generic_steppings }, 222 223 { CPU_ID_ARM600, CPU_CLASS_ARM6, "ARM600", 224 generic_steppings }, 225 { CPU_ID_ARM610, CPU_CLASS_ARM6, "ARM610", 226 generic_steppings }, 227 { CPU_ID_ARM620, CPU_CLASS_ARM6, "ARM620", 228 generic_steppings }, 229 230 { CPU_ID_ARM700, CPU_CLASS_ARM7, "ARM700", 231 generic_steppings }, 232 { CPU_ID_ARM710, CPU_CLASS_ARM7, "ARM710", 233 generic_steppings }, 234 { CPU_ID_ARM7500, CPU_CLASS_ARM7, "ARM7500", 235 generic_steppings }, 236 { CPU_ID_ARM710A, CPU_CLASS_ARM7, "ARM710a", 237 generic_steppings }, 238 { CPU_ID_ARM7500FE, CPU_CLASS_ARM7, "ARM7500FE", 239 generic_steppings }, 240 { CPU_ID_ARM710T, CPU_CLASS_ARM7TDMI, "ARM710T", 241 generic_steppings }, 242 { CPU_ID_ARM720T, CPU_CLASS_ARM7TDMI, "ARM720T", 243 generic_steppings }, 244 { CPU_ID_ARM740T8K, CPU_CLASS_ARM7TDMI, "ARM740T (8 KB cache)", 245 generic_steppings }, 246 { CPU_ID_ARM740T4K, CPU_CLASS_ARM7TDMI, "ARM740T (4 KB cache)", 247 generic_steppings }, 248 249 { CPU_ID_ARM810, CPU_CLASS_ARM8, "ARM810", 250 generic_steppings }, 251 252 { CPU_ID_ARM920T, CPU_CLASS_ARM9TDMI, "ARM920T", 253 generic_steppings }, 254 { CPU_ID_ARM922T, CPU_CLASS_ARM9TDMI, "ARM922T", 255 generic_steppings }, 256 { CPU_ID_ARM940T, CPU_CLASS_ARM9TDMI, "ARM940T", 257 generic_steppings }, 258 { CPU_ID_ARM946ES, CPU_CLASS_ARM9ES, "ARM946E-S", 259 generic_steppings }, 260 { CPU_ID_ARM966ES, CPU_CLASS_ARM9ES, "ARM966E-S", 261 generic_steppings }, 262 { CPU_ID_ARM966ESR1, CPU_CLASS_ARM9ES, "ARM966E-S", 263 generic_steppings }, 264 265 { CPU_ID_SA110, CPU_CLASS_SA1, "SA-110", 266 sa110_steppings }, 267 { CPU_ID_SA1100, CPU_CLASS_SA1, "SA-1100", 268 sa1100_steppings }, 269 { CPU_ID_SA1110, CPU_CLASS_SA1, "SA-1110", 270 sa1110_steppings }, 271 272 { CPU_ID_I80200, CPU_CLASS_XSCALE, "i80200", 273 i80200_steppings }, 274 275 { CPU_ID_ARM1022ES, CPU_CLASS_ARM10E, "ARM1022ES", 276 generic_steppings }, 277 278 { 0, CPU_CLASS_NONE, NULL, NULL } 279 }; 280 281 struct cpu_classtab { 282 const char *class_name; 283 const char *class_option; 284 }; 285 286 const struct cpu_classtab cpu_classes[] = { 287 { "unknown", NULL }, /* CPU_CLASS_NONE */ 288 { "ARM2", "CPU_ARM2" }, /* CPU_CLASS_ARM2 */ 289 { "ARM2as", "CPU_ARM250" }, /* CPU_CLASS_ARM2AS */ 290 { "ARM3", "CPU_ARM3" }, /* CPU_CLASS_ARM3 */ 291 { "ARM6", "CPU_ARM6" }, /* CPU_CLASS_ARM6 */ 292 { "ARM7", "CPU_ARM7" }, /* CPU_CLASS_ARM7 */ 293 { "ARM7TDMI", "CPU_ARM7TDMI" }, /* CPU_CLASS_ARM7TDMI */ 294 { "ARM8", "CPU_ARM8" }, /* CPU_CLASS_ARM8 */ 295 { "ARM9TDMI", NULL }, /* CPU_CLASS_ARM9TDMI */ 296 { "ARM9E-S", NULL }, /* CPU_CLASS_ARM9ES */ 297 { "SA-1", "CPU_SA110" }, /* CPU_CLASS_SA1 */ 298 { "XScale", "CPU_XSCALE" }, /* CPU_CLASS_XSCALE */ 299 { "ARM10E", NULL }, /* CPU_CLASS_ARM10E */ 300 }; 301 302 /* 303 * Report the type of the specifed arm processor. This uses the generic and 304 * arm specific information in the cpu structure to identify the processor. 305 * The remaining fields in the cpu structure are filled in appropriately. 306 */ 307 308 static const char *wtnames[] = { 309 "write-through", 310 "write-back", 311 "write-back", 312 "**unknown 3**", 313 "**unknown 4**", 314 "write-back-locking", /* XXX XScale-specific? */ 315 "write-back-locking-A", 316 "write-back-locking-B", 317 "**unknown 8**", 318 "**unknown 9**", 319 "**unknown 10**", 320 "**unknown 11**", 321 "**unknown 12**", 322 "**unknown 13**", 323 "**unknown 14**", 324 "**unknown 15**", 325 }; 326 327 void 328 identify_arm_cpu(struct device *dv, struct cpu_info *ci) 329 { 330 u_int cpuid; 331 enum cpu_class cpu_class; 332 int i; 333 334 cpuid = ci->ci_cpuid; 335 336 if (cpuid == 0) { 337 printf("Processor failed probe - no CPU ID\n"); 338 return; 339 } 340 341 for (i = 0; cpuids[i].cpuid != 0; i++) 342 if (cpuids[i].cpuid == (cpuid & CPU_ID_CPU_MASK)) { 343 cpu_class = cpuids[i].cpu_class; 344 sprintf(cpu_model, "%s %s (%s core)", 345 cpuids[i].cpu_name, 346 cpuids[i].cpu_steppings[cpuid & 347 CPU_ID_REVISION_MASK], 348 cpu_classes[cpu_class].class_name); 349 break; 350 } 351 352 if (cpuids[i].cpuid == 0) 353 sprintf(cpu_model, "unknown CPU (ID = 0x%x)", cpuid); 354 355 printf(": %s\n", cpu_model); 356 357 printf("%s:", dv->dv_xname); 358 359 switch (cpu_class) { 360 case CPU_CLASS_ARM6: 361 case CPU_CLASS_ARM7: 362 case CPU_CLASS_ARM7TDMI: 363 case CPU_CLASS_ARM8: 364 if ((ci->ci_ctrl & CPU_CONTROL_IDC_ENABLE) == 0) 365 printf(" IDC disabled"); 366 else 367 printf(" IDC enabled"); 368 break; 369 case CPU_CLASS_ARM9TDMI: 370 case CPU_CLASS_SA1: 371 case CPU_CLASS_XSCALE: 372 if ((ci->ci_ctrl & CPU_CONTROL_DC_ENABLE) == 0) 373 printf(" DC disabled"); 374 else 375 printf(" DC enabled"); 376 if ((ci->ci_ctrl & CPU_CONTROL_IC_ENABLE) == 0) 377 printf(" IC disabled"); 378 else 379 printf(" IC enabled"); 380 break; 381 default: 382 break; 383 } 384 if ((ci->ci_ctrl & CPU_CONTROL_WBUF_ENABLE) == 0) 385 printf(" WB disabled"); 386 else 387 printf(" WB enabled"); 388 389 if (ci->ci_ctrl & CPU_CONTROL_LABT_ENABLE) 390 printf(" LABT"); 391 else 392 printf(" EABT"); 393 394 if (ci->ci_ctrl & CPU_CONTROL_BPRD_ENABLE) 395 printf(" branch prediction enabled"); 396 397 printf("\n"); 398 399 /* Print cache info. */ 400 if (arm_picache_line_size == 0 && arm_pdcache_line_size == 0) 401 goto skip_pcache; 402 403 if (arm_pcache_unified) { 404 printf("%s: %dKB/%dB %d-way %s unified cache\n", 405 dv->dv_xname, arm_pdcache_size / 1024, 406 arm_pdcache_line_size, arm_pdcache_ways, 407 wtnames[arm_pcache_type]); 408 } else { 409 printf("%s: %dKB/%dB %d-way Instruction cache\n", 410 dv->dv_xname, arm_picache_size / 1024, 411 arm_picache_line_size, arm_picache_ways); 412 printf("%s: %dKB/%dB %d-way %s Data cache\n", 413 dv->dv_xname, arm_pdcache_size / 1024, 414 arm_pdcache_line_size, arm_pdcache_ways, 415 wtnames[arm_pcache_type]); 416 } 417 418 skip_pcache: 419 420 switch (cpu_class) { 421 #ifdef CPU_ARM2 422 case CPU_CLASS_ARM2: 423 #endif 424 #ifdef CPU_ARM250 425 case CPU_CLASS_ARM2AS: 426 #endif 427 #ifdef CPU_ARM3 428 case CPU_CLASS_ARM3: 429 #endif 430 #ifdef CPU_ARM6 431 case CPU_CLASS_ARM6: 432 #endif 433 #ifdef CPU_ARM7 434 case CPU_CLASS_ARM7: 435 #endif 436 #ifdef CPU_ARM7TDMI 437 case CPU_CLASS_ARM7TDMI: 438 #endif 439 #ifdef CPU_ARM8 440 case CPU_CLASS_ARM8: 441 #endif 442 #ifdef CPU_ARM9 443 case CPU_CLASS_ARM9TDMI: 444 #endif 445 #ifdef CPU_SA110 446 case CPU_CLASS_SA1: 447 #endif 448 #ifdef CPU_XSCALE 449 case CPU_CLASS_XSCALE: 450 #endif 451 break; 452 default: 453 if (cpu_classes[cpu_class].class_option != NULL) 454 printf("%s: %s does not fully support this CPU." 455 "\n", dv->dv_xname, ostype); 456 else { 457 printf("%s: This kernel does not fully support " 458 "this CPU.\n", dv->dv_xname); 459 printf("%s: Recompile with \"options %s\" to " 460 "correct this.\n", dv->dv_xname, 461 cpu_classes[cpu_class].class_option); 462 } 463 break; 464 } 465 466 } 467 468 /* End of cpu.c */ 469
Indexes created Tue Sep 23 23:09:58 GMT 2025