cpu.c revision 1.34
1 /* $NetBSD: cpu.c,v 1.34 2002/05/02 22:57:36 rjs Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Mark Brinicombe. 5 * Copyright (c) 1995 Brini. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Brini. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * cpu.c 38 * 39 * Probing and configuration for the master cpu 40 * 41 * Created : 10/10/95 42 */ 43 44 #include "opt_armfpe.h" 45 46 #include <sys/param.h> 47 48 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.34 2002/05/02 22:57:36 rjs Exp $"); 49 50 #include <sys/systm.h> 51 #include <sys/malloc.h> 52 #include <sys/device.h> 53 #include <sys/proc.h> 54 #include <uvm/uvm_extern.h> 55 #include <machine/conf.h> 56 #include <machine/cpu.h> 57 58 #include <arm/cpuconf.h> 59 #include <arm/undefined.h> 60 61 #ifdef ARMFPE 62 #include <machine/bootconfig.h> /* For boot args */ 63 #include <arm/fpe-arm/armfpe.h> 64 #endif 65 66 char cpu_model[256]; 67 68 /* Prototypes */ 69 void identify_arm_cpu(struct device *dv, struct cpu_info *); 70 71 /* 72 * Identify the master (boot) CPU 73 */ 74 75 void 76 cpu_attach(struct device *dv) 77 { 78 int usearmfpe; 79 80 usearmfpe = 1; /* when compiled in, its enabled by default */ 81 82 curcpu()->ci_dev = dv; 83 84 evcnt_attach_dynamic(&curcpu()->ci_arm700bugcount, EVCNT_TYPE_MISC, 85 NULL, dv->dv_xname, "arm700swibug"); 86 87 /* Get the cpu ID from coprocessor 15 */ 88 89 curcpu()->ci_cpuid = cpu_id(); 90 curcpu()->ci_cputype = curcpu()->ci_cpuid & CPU_ID_CPU_MASK; 91 curcpu()->ci_cpurev = curcpu()->ci_cpuid & CPU_ID_REVISION_MASK; 92 93 identify_arm_cpu(dv, curcpu()); 94 95 if (curcpu()->ci_cputype == CPU_ID_SA110 && curcpu()->ci_cpurev < 3) { 96 printf("%s: SA-110 with bugged STM^ instruction\n", 97 dv->dv_xname); 98 } 99 100 #ifdef CPU_ARM8 101 if ((curcpu()->ci_cpuid & CPU_ID_CPU_MASK) == CPU_ID_ARM810) { 102 int clock = arm8_clock_config(0, 0); 103 char *fclk; 104 printf("%s: ARM810 cp15=%02x", dv->dv_xname, clock); 105 printf(" clock:%s", (clock & 1) ? " dynamic" : ""); 106 printf("%s", (clock & 2) ? " sync" : ""); 107 switch ((clock >> 2) & 3) { 108 case 0: 109 fclk = "bus clock"; 110 break; 111 case 1: 112 fclk = "ref clock"; 113 break; 114 case 3: 115 fclk = "pll"; 116 break; 117 default: 118 fclk = "illegal"; 119 break; 120 } 121 printf(" fclk source=%s\n", fclk); 122 } 123 #endif 124 125 #ifdef ARMFPE 126 /* 127 * Ok now we test for an FPA 128 * At this point no floating point emulator has been installed. 129 * This means any FP instruction will cause undefined exception. 130 * We install a temporay coproc 1 handler which will modify 131 * undefined_test if it is called. 132 * We then try to read the FP status register. If undefined_test 133 * has been decremented then the instruction was not handled by 134 * an FPA so we know the FPA is missing. If undefined_test is 135 * still 1 then we know the instruction was handled by an FPA. 136 * We then remove our test handler and look at the 137 * FP status register for identification. 138 */ 139 140 /* 141 * Ok if ARMFPE is defined and the boot options request the 142 * ARM FPE then it will be installed as the FPE. 143 * This is just while I work on integrating the new FPE. 144 * It means the new FPE gets installed if compiled int (ARMFPE 145 * defined) and also gives me a on/off option when I boot in 146 * case the new FPE is causing panics. 147 */ 148 149 150 if (boot_args) 151 get_bootconf_option(boot_args, "armfpe", 152 BOOTOPT_TYPE_BOOLEAN, &usearmfpe); 153 if (usearmfpe) 154 initialise_arm_fpe(); 155 #endif 156 } 157 158 enum cpu_class { 159 CPU_CLASS_NONE, 160 CPU_CLASS_ARM2, 161 CPU_CLASS_ARM2AS, 162 CPU_CLASS_ARM3, 163 CPU_CLASS_ARM6, 164 CPU_CLASS_ARM7, 165 CPU_CLASS_ARM7TDMI, 166 CPU_CLASS_ARM8, 167 CPU_CLASS_ARM9TDMI, 168 CPU_CLASS_ARM9ES, 169 CPU_CLASS_SA1, 170 CPU_CLASS_XSCALE, 171 CPU_CLASS_ARM10E 172 }; 173 174 static const char *generic_steppings[16] = { 175 "rev 0", "rev 1", "rev 2", "rev 3", 176 "rev 4", "rev 5", "rev 6", "rev 7", 177 "rev 8", "rev 9", "rev 10", "rev 11", 178 "rev 12", "rev 13", "rev 14", "rev 15", 179 }; 180 181 static const char *sa110_steppings[16] = { 182 "rev 0", "step J", "step K", "step S", 183 "step T", "rev 5", "rev 6", "rev 7", 184 "rev 8", "rev 9", "rev 10", "rev 11", 185 "rev 12", "rev 13", "rev 14", "rev 15", 186 }; 187 188 static const char *sa1100_steppings[16] = { 189 "rev 0", "step B", "step C", "rev 3", 190 "rev 4", "rev 5", "rev 6", "rev 7", 191 "step D", "step E", "rev 10" "step G", 192 "rev 12", "rev 13", "rev 14", "rev 15", 193 }; 194 195 static const char *sa1110_steppings[16] = { 196 "step A-0", "rev 1", "rev 2", "rev 3", 197 "step B-0", "step B-1", "step B-2", "step B-3", 198 "step B-4", "step B-5", "rev 10", "rev 11", 199 "rev 12", "rev 13", "rev 14", "rev 15", 200 }; 201 202 static const char *xscale_steppings[16] = { 203 "step A-0", "step A-1", "step B-0", "step C-0", 204 "rev 4", "rev 5", "rev 6", "rev 7", 205 "rev 8", "rev 9", "rev 10", "rev 11", 206 "rev 12", "rev 13", "rev 14", "rev 15", 207 }; 208 209 struct cpuidtab { 210 u_int32_t cpuid; 211 enum cpu_class cpu_class; 212 const char *cpu_name; 213 const char **cpu_steppings; 214 }; 215 216 const struct cpuidtab cpuids[] = { 217 { CPU_ID_ARM2, CPU_CLASS_ARM2, "ARM2", 218 generic_steppings }, 219 { CPU_ID_ARM250, CPU_CLASS_ARM2AS, "ARM250", 220 generic_steppings }, 221 222 { CPU_ID_ARM3, CPU_CLASS_ARM3, "ARM3", 223 generic_steppings }, 224 225 { CPU_ID_ARM600, CPU_CLASS_ARM6, "ARM600", 226 generic_steppings }, 227 { CPU_ID_ARM610, CPU_CLASS_ARM6, "ARM610", 228 generic_steppings }, 229 { CPU_ID_ARM620, CPU_CLASS_ARM6, "ARM620", 230 generic_steppings }, 231 232 { CPU_ID_ARM700, CPU_CLASS_ARM7, "ARM700", 233 generic_steppings }, 234 { CPU_ID_ARM710, CPU_CLASS_ARM7, "ARM710", 235 generic_steppings }, 236 { CPU_ID_ARM7500, CPU_CLASS_ARM7, "ARM7500", 237 generic_steppings }, 238 { CPU_ID_ARM710A, CPU_CLASS_ARM7, "ARM710a", 239 generic_steppings }, 240 { CPU_ID_ARM7500FE, CPU_CLASS_ARM7, "ARM7500FE", 241 generic_steppings }, 242 { CPU_ID_ARM710T, CPU_CLASS_ARM7TDMI, "ARM710T", 243 generic_steppings }, 244 { CPU_ID_ARM720T, CPU_CLASS_ARM7TDMI, "ARM720T", 245 generic_steppings }, 246 { CPU_ID_ARM740T8K, CPU_CLASS_ARM7TDMI, "ARM740T (8 KB cache)", 247 generic_steppings }, 248 { CPU_ID_ARM740T4K, CPU_CLASS_ARM7TDMI, "ARM740T (4 KB cache)", 249 generic_steppings }, 250 251 { CPU_ID_ARM810, CPU_CLASS_ARM8, "ARM810", 252 generic_steppings }, 253 254 { CPU_ID_ARM920T, CPU_CLASS_ARM9TDMI, "ARM920T", 255 generic_steppings }, 256 { CPU_ID_ARM922T, CPU_CLASS_ARM9TDMI, "ARM922T", 257 generic_steppings }, 258 { CPU_ID_ARM940T, CPU_CLASS_ARM9TDMI, "ARM940T", 259 generic_steppings }, 260 { CPU_ID_ARM946ES, CPU_CLASS_ARM9ES, "ARM946E-S", 261 generic_steppings }, 262 { CPU_ID_ARM966ES, CPU_CLASS_ARM9ES, "ARM966E-S", 263 generic_steppings }, 264 { CPU_ID_ARM966ESR1, CPU_CLASS_ARM9ES, "ARM966E-S", 265 generic_steppings }, 266 267 { CPU_ID_SA110, CPU_CLASS_SA1, "SA-110", 268 sa110_steppings }, 269 { CPU_ID_SA1100, CPU_CLASS_SA1, "SA-1100", 270 sa1100_steppings }, 271 { CPU_ID_SA1110, CPU_CLASS_SA1, "SA-1110", 272 sa1110_steppings }, 273 274 { CPU_ID_80200, CPU_CLASS_XSCALE, "i80200", 275 xscale_steppings }, 276 277 { CPU_ID_80321, CPU_CLASS_XSCALE, "i80321", 278 xscale_steppings }, 279 280 { CPU_ID_ARM1022ES, CPU_CLASS_ARM10E, "ARM1022ES", 281 generic_steppings }, 282 283 { 0, CPU_CLASS_NONE, NULL, NULL } 284 }; 285 286 struct cpu_classtab { 287 const char *class_name; 288 const char *class_option; 289 }; 290 291 const struct cpu_classtab cpu_classes[] = { 292 { "unknown", NULL }, /* CPU_CLASS_NONE */ 293 { "ARM2", "CPU_ARM2" }, /* CPU_CLASS_ARM2 */ 294 { "ARM2as", "CPU_ARM250" }, /* CPU_CLASS_ARM2AS */ 295 { "ARM3", "CPU_ARM3" }, /* CPU_CLASS_ARM3 */ 296 { "ARM6", "CPU_ARM6" }, /* CPU_CLASS_ARM6 */ 297 { "ARM7", "CPU_ARM7" }, /* CPU_CLASS_ARM7 */ 298 { "ARM7TDMI", "CPU_ARM7TDMI" }, /* CPU_CLASS_ARM7TDMI */ 299 { "ARM8", "CPU_ARM8" }, /* CPU_CLASS_ARM8 */ 300 { "ARM9TDMI", NULL }, /* CPU_CLASS_ARM9TDMI */ 301 { "ARM9E-S", NULL }, /* CPU_CLASS_ARM9ES */ 302 { "SA-1", "CPU_SA110" }, /* CPU_CLASS_SA1 */ 303 { "XScale", "CPU_XSCALE_..." }, /* CPU_CLASS_XSCALE */ 304 { "ARM10E", NULL }, /* CPU_CLASS_ARM10E */ 305 }; 306 307 /* 308 * Report the type of the specifed arm processor. This uses the generic and 309 * arm specific information in the cpu structure to identify the processor. 310 * The remaining fields in the cpu structure are filled in appropriately. 311 */ 312 313 static const char *wtnames[] = { 314 "write-through", 315 "write-back", 316 "write-back", 317 "**unknown 3**", 318 "**unknown 4**", 319 "write-back-locking", /* XXX XScale-specific? */ 320 "write-back-locking-A", 321 "write-back-locking-B", 322 "**unknown 8**", 323 "**unknown 9**", 324 "**unknown 10**", 325 "**unknown 11**", 326 "**unknown 12**", 327 "**unknown 13**", 328 "**unknown 14**", 329 "**unknown 15**", 330 }; 331 332 void 333 identify_arm_cpu(struct device *dv, struct cpu_info *ci) 334 { 335 u_int cpuid; 336 enum cpu_class cpu_class; 337 int i; 338 339 cpuid = ci->ci_cpuid; 340 341 if (cpuid == 0) { 342 printf("Processor failed probe - no CPU ID\n"); 343 return; 344 } 345 346 for (i = 0; cpuids[i].cpuid != 0; i++) 347 if (cpuids[i].cpuid == (cpuid & CPU_ID_CPU_MASK)) { 348 cpu_class = cpuids[i].cpu_class; 349 sprintf(cpu_model, "%s %s (%s core)", 350 cpuids[i].cpu_name, 351 cpuids[i].cpu_steppings[cpuid & 352 CPU_ID_REVISION_MASK], 353 cpu_classes[cpu_class].class_name); 354 break; 355 } 356 357 if (cpuids[i].cpuid == 0) 358 sprintf(cpu_model, "unknown CPU (ID = 0x%x)", cpuid); 359 360 printf(": %s\n", cpu_model); 361 362 printf("%s:", dv->dv_xname); 363 364 switch (cpu_class) { 365 case CPU_CLASS_ARM6: 366 case CPU_CLASS_ARM7: 367 case CPU_CLASS_ARM7TDMI: 368 case CPU_CLASS_ARM8: 369 if ((ci->ci_ctrl & CPU_CONTROL_IDC_ENABLE) == 0) 370 printf(" IDC disabled"); 371 else 372 printf(" IDC enabled"); 373 break; 374 case CPU_CLASS_ARM9TDMI: 375 case CPU_CLASS_SA1: 376 case CPU_CLASS_XSCALE: 377 if ((ci->ci_ctrl & CPU_CONTROL_DC_ENABLE) == 0) 378 printf(" DC disabled"); 379 else 380 printf(" DC enabled"); 381 if ((ci->ci_ctrl & CPU_CONTROL_IC_ENABLE) == 0) 382 printf(" IC disabled"); 383 else 384 printf(" IC enabled"); 385 break; 386 default: 387 break; 388 } 389 if ((ci->ci_ctrl & CPU_CONTROL_WBUF_ENABLE) == 0) 390 printf(" WB disabled"); 391 else 392 printf(" WB enabled"); 393 394 if (ci->ci_ctrl & CPU_CONTROL_LABT_ENABLE) 395 printf(" LABT"); 396 else 397 printf(" EABT"); 398 399 if (ci->ci_ctrl & CPU_CONTROL_BPRD_ENABLE) 400 printf(" branch prediction enabled"); 401 402 printf("\n"); 403 404 /* Print cache info. */ 405 if (arm_picache_line_size == 0 && arm_pdcache_line_size == 0) 406 goto skip_pcache; 407 408 if (arm_pcache_unified) { 409 printf("%s: %dKB/%dB %d-way %s unified cache\n", 410 dv->dv_xname, arm_pdcache_size / 1024, 411 arm_pdcache_line_size, arm_pdcache_ways, 412 wtnames[arm_pcache_type]); 413 } else { 414 printf("%s: %dKB/%dB %d-way Instruction cache\n", 415 dv->dv_xname, arm_picache_size / 1024, 416 arm_picache_line_size, arm_picache_ways); 417 printf("%s: %dKB/%dB %d-way %s Data cache\n", 418 dv->dv_xname, arm_pdcache_size / 1024, 419 arm_pdcache_line_size, arm_pdcache_ways, 420 wtnames[arm_pcache_type]); 421 } 422 423 skip_pcache: 424 425 switch (cpu_class) { 426 #ifdef CPU_ARM2 427 case CPU_CLASS_ARM2: 428 #endif 429 #ifdef CPU_ARM250 430 case CPU_CLASS_ARM2AS: 431 #endif 432 #ifdef CPU_ARM3 433 case CPU_CLASS_ARM3: 434 #endif 435 #ifdef CPU_ARM6 436 case CPU_CLASS_ARM6: 437 #endif 438 #ifdef CPU_ARM7 439 case CPU_CLASS_ARM7: 440 #endif 441 #ifdef CPU_ARM7TDMI 442 case CPU_CLASS_ARM7TDMI: 443 #endif 444 #ifdef CPU_ARM8 445 case CPU_CLASS_ARM8: 446 #endif 447 #ifdef CPU_ARM9 448 case CPU_CLASS_ARM9TDMI: 449 #endif 450 #if defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) 451 case CPU_CLASS_SA1: 452 #endif 453 #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) 454 case CPU_CLASS_XSCALE: 455 #endif 456 break; 457 default: 458 if (cpu_classes[cpu_class].class_option != NULL) 459 printf("%s: %s does not fully support this CPU." 460 "\n", dv->dv_xname, ostype); 461 else { 462 printf("%s: This kernel does not fully support " 463 "this CPU.\n", dv->dv_xname); 464 printf("%s: Recompile with \"options %s\" to " 465 "correct this.\n", dv->dv_xname, 466 cpu_classes[cpu_class].class_option); 467 } 468 break; 469 } 470 471 } 472 473 /* End of cpu.c */ 474
Indexes created Sat Sep 27 14:09:57 GMT 2025