cpu.c revision 1.41
1 /* $NetBSD: cpu.c,v 1.41 2002/09/06 13:18:43 gehenna Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Mark Brinicombe. 5 * Copyright (c) 1995 Brini. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Brini. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * cpu.c 38 * 39 * Probing and configuration for the master cpu 40 * 41 * Created : 10/10/95 42 */ 43 44 #include "opt_armfpe.h" 45 46 #include <sys/param.h> 47 48 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.41 2002/09/06 13:18:43 gehenna Exp $"); 49 50 #include <sys/systm.h> 51 #include <sys/malloc.h> 52 #include <sys/device.h> 53 #include <sys/proc.h> 54 #include <sys/conf.h> 55 #include <uvm/uvm_extern.h> 56 #include <machine/cpu.h> 57 58 #include <arm/cpuconf.h> 59 #include <arm/undefined.h> 60 61 #ifdef ARMFPE 62 #include <machine/bootconfig.h> /* For boot args */ 63 #include <arm/fpe-arm/armfpe.h> 64 #endif 65 66 char cpu_model[256]; 67 68 /* Prototypes */ 69 void identify_arm_cpu(struct device *dv, struct cpu_info *); 70 71 /* 72 * Identify the master (boot) CPU 73 */ 74 75 void 76 cpu_attach(struct device *dv) 77 { 78 int usearmfpe; 79 80 usearmfpe = 1; /* when compiled in, its enabled by default */ 81 82 curcpu()->ci_dev = dv; 83 84 evcnt_attach_dynamic(&curcpu()->ci_arm700bugcount, EVCNT_TYPE_MISC, 85 NULL, dv->dv_xname, "arm700swibug"); 86 87 /* Get the cpu ID from coprocessor 15 */ 88 89 curcpu()->ci_cpuid = cpu_id(); 90 curcpu()->ci_cputype = curcpu()->ci_cpuid & CPU_ID_CPU_MASK; 91 curcpu()->ci_cpurev = curcpu()->ci_cpuid & CPU_ID_REVISION_MASK; 92 93 identify_arm_cpu(dv, curcpu()); 94 95 if (curcpu()->ci_cputype == CPU_ID_SA110 && curcpu()->ci_cpurev < 3) { 96 printf("%s: SA-110 with bugged STM^ instruction\n", 97 dv->dv_xname); 98 } 99 100 #ifdef CPU_ARM8 101 if ((curcpu()->ci_cpuid & CPU_ID_CPU_MASK) == CPU_ID_ARM810) { 102 int clock = arm8_clock_config(0, 0); 103 char *fclk; 104 printf("%s: ARM810 cp15=%02x", dv->dv_xname, clock); 105 printf(" clock:%s", (clock & 1) ? " dynamic" : ""); 106 printf("%s", (clock & 2) ? " sync" : ""); 107 switch ((clock >> 2) & 3) { 108 case 0: 109 fclk = "bus clock"; 110 break; 111 case 1: 112 fclk = "ref clock"; 113 break; 114 case 3: 115 fclk = "pll"; 116 break; 117 default: 118 fclk = "illegal"; 119 break; 120 } 121 printf(" fclk source=%s\n", fclk); 122 } 123 #endif 124 125 #ifdef ARMFPE 126 /* 127 * Ok now we test for an FPA 128 * At this point no floating point emulator has been installed. 129 * This means any FP instruction will cause undefined exception. 130 * We install a temporay coproc 1 handler which will modify 131 * undefined_test if it is called. 132 * We then try to read the FP status register. If undefined_test 133 * has been decremented then the instruction was not handled by 134 * an FPA so we know the FPA is missing. If undefined_test is 135 * still 1 then we know the instruction was handled by an FPA. 136 * We then remove our test handler and look at the 137 * FP status register for identification. 138 */ 139 140 /* 141 * Ok if ARMFPE is defined and the boot options request the 142 * ARM FPE then it will be installed as the FPE. 143 * This is just while I work on integrating the new FPE. 144 * It means the new FPE gets installed if compiled int (ARMFPE 145 * defined) and also gives me a on/off option when I boot in 146 * case the new FPE is causing panics. 147 */ 148 149 150 if (boot_args) 151 get_bootconf_option(boot_args, "armfpe", 152 BOOTOPT_TYPE_BOOLEAN, &usearmfpe); 153 if (usearmfpe) 154 initialise_arm_fpe(); 155 #endif 156 } 157 158 enum cpu_class { 159 CPU_CLASS_NONE, 160 CPU_CLASS_ARM2, 161 CPU_CLASS_ARM2AS, 162 CPU_CLASS_ARM3, 163 CPU_CLASS_ARM6, 164 CPU_CLASS_ARM7, 165 CPU_CLASS_ARM7TDMI, 166 CPU_CLASS_ARM8, 167 CPU_CLASS_ARM9TDMI, 168 CPU_CLASS_ARM9ES, 169 CPU_CLASS_SA1, 170 CPU_CLASS_XSCALE, 171 CPU_CLASS_ARM10E 172 }; 173 174 static const char *generic_steppings[16] = { 175 "rev 0", "rev 1", "rev 2", "rev 3", 176 "rev 4", "rev 5", "rev 6", "rev 7", 177 "rev 8", "rev 9", "rev 10", "rev 11", 178 "rev 12", "rev 13", "rev 14", "rev 15", 179 }; 180 181 static const char *sa110_steppings[16] = { 182 "rev 0", "step J", "step K", "step S", 183 "step T", "rev 5", "rev 6", "rev 7", 184 "rev 8", "rev 9", "rev 10", "rev 11", 185 "rev 12", "rev 13", "rev 14", "rev 15", 186 }; 187 188 static const char *sa1100_steppings[16] = { 189 "rev 0", "step B", "step C", "rev 3", 190 "rev 4", "rev 5", "rev 6", "rev 7", 191 "step D", "step E", "rev 10" "step G", 192 "rev 12", "rev 13", "rev 14", "rev 15", 193 }; 194 195 static const char *sa1110_steppings[16] = { 196 "step A-0", "rev 1", "rev 2", "rev 3", 197 "step B-0", "step B-1", "step B-2", "step B-3", 198 "step B-4", "step B-5", "rev 10", "rev 11", 199 "rev 12", "rev 13", "rev 14", "rev 15", 200 }; 201 202 static const char *ixp12x0_steppings[16] = { 203 "(IXP1200 step A)", "(IXP1200 step B)", 204 "rev 2", "(IXP1200 step C)", 205 "(IXP1200 step D)", "(IXP1240/1250 step A)", 206 "(IXP1240 step B)", "(IXP1250 step B)", 207 "rev 8", "rev 9", "rev 10", "rev 11", 208 "rev 12", "rev 13", "rev 14", "rev 15", 209 }; 210 211 static const char *xscale_steppings[16] = { 212 "step A-0", "step A-1", "step B-0", "step C-0", 213 "step D-0", "rev 5", "rev 6", "rev 7", 214 "rev 8", "rev 9", "rev 10", "rev 11", 215 "rev 12", "rev 13", "rev 14", "rev 15", 216 }; 217 218 static const char *i80321_steppings[16] = { 219 "step A-0", "step B-0", "rev 2", "rev 3", 220 "rev 4", "rev 5", "rev 6", "rev 7", 221 "rev 8", "rev 9", "rev 10", "rev 11", 222 "rev 12", "rev 13", "rev 14", "rev 15", 223 }; 224 225 static const char *pxa2x0_steppings[16] = { 226 "step A-0", "step A-1", "step B-0", "step B-1", 227 "rev 4", "rev 5", "rev 6", "rev 7", 228 "rev 8", "rev 9", "rev 10", "rev 11", 229 "rev 12", "rev 13", "rev 14", "rev 15", 230 }; 231 232 struct cpuidtab { 233 u_int32_t cpuid; 234 enum cpu_class cpu_class; 235 const char *cpu_name; 236 const char **cpu_steppings; 237 }; 238 239 const struct cpuidtab cpuids[] = { 240 { CPU_ID_ARM2, CPU_CLASS_ARM2, "ARM2", 241 generic_steppings }, 242 { CPU_ID_ARM250, CPU_CLASS_ARM2AS, "ARM250", 243 generic_steppings }, 244 245 { CPU_ID_ARM3, CPU_CLASS_ARM3, "ARM3", 246 generic_steppings }, 247 248 { CPU_ID_ARM600, CPU_CLASS_ARM6, "ARM600", 249 generic_steppings }, 250 { CPU_ID_ARM610, CPU_CLASS_ARM6, "ARM610", 251 generic_steppings }, 252 { CPU_ID_ARM620, CPU_CLASS_ARM6, "ARM620", 253 generic_steppings }, 254 255 { CPU_ID_ARM700, CPU_CLASS_ARM7, "ARM700", 256 generic_steppings }, 257 { CPU_ID_ARM710, CPU_CLASS_ARM7, "ARM710", 258 generic_steppings }, 259 { CPU_ID_ARM7500, CPU_CLASS_ARM7, "ARM7500", 260 generic_steppings }, 261 { CPU_ID_ARM710A, CPU_CLASS_ARM7, "ARM710a", 262 generic_steppings }, 263 { CPU_ID_ARM7500FE, CPU_CLASS_ARM7, "ARM7500FE", 264 generic_steppings }, 265 { CPU_ID_ARM710T, CPU_CLASS_ARM7TDMI, "ARM710T", 266 generic_steppings }, 267 { CPU_ID_ARM720T, CPU_CLASS_ARM7TDMI, "ARM720T", 268 generic_steppings }, 269 { CPU_ID_ARM740T8K, CPU_CLASS_ARM7TDMI, "ARM740T (8 KB cache)", 270 generic_steppings }, 271 { CPU_ID_ARM740T4K, CPU_CLASS_ARM7TDMI, "ARM740T (4 KB cache)", 272 generic_steppings }, 273 274 { CPU_ID_ARM810, CPU_CLASS_ARM8, "ARM810", 275 generic_steppings }, 276 277 { CPU_ID_ARM920T, CPU_CLASS_ARM9TDMI, "ARM920T", 278 generic_steppings }, 279 { CPU_ID_ARM922T, CPU_CLASS_ARM9TDMI, "ARM922T", 280 generic_steppings }, 281 { CPU_ID_ARM940T, CPU_CLASS_ARM9TDMI, "ARM940T", 282 generic_steppings }, 283 { CPU_ID_ARM946ES, CPU_CLASS_ARM9ES, "ARM946E-S", 284 generic_steppings }, 285 { CPU_ID_ARM966ES, CPU_CLASS_ARM9ES, "ARM966E-S", 286 generic_steppings }, 287 { CPU_ID_ARM966ESR1, CPU_CLASS_ARM9ES, "ARM966E-S", 288 generic_steppings }, 289 290 { CPU_ID_SA110, CPU_CLASS_SA1, "SA-110", 291 sa110_steppings }, 292 { CPU_ID_SA1100, CPU_CLASS_SA1, "SA-1100", 293 sa1100_steppings }, 294 { CPU_ID_SA1110, CPU_CLASS_SA1, "SA-1110", 295 sa1110_steppings }, 296 297 { CPU_ID_IXP1200, CPU_CLASS_SA1, "IXP1200", 298 ixp12x0_steppings }, 299 300 { CPU_ID_80200, CPU_CLASS_XSCALE, "i80200", 301 xscale_steppings }, 302 303 { CPU_ID_80321_400, CPU_CLASS_XSCALE, "i80321 400MHz", 304 i80321_steppings }, 305 { CPU_ID_80321_600, CPU_CLASS_XSCALE, "i80321 600MHz", 306 i80321_steppings }, 307 { CPU_ID_80321_400_B0, CPU_CLASS_XSCALE, "i80321 400MHz", 308 i80321_steppings }, 309 { CPU_ID_80321_600_B0, CPU_CLASS_XSCALE, "i80321 600MHz", 310 i80321_steppings }, 311 312 { CPU_ID_PXA250A, CPU_CLASS_XSCALE, "PXA250(1st ver core)", 313 pxa2x0_steppings }, 314 { CPU_ID_PXA210A, CPU_CLASS_XSCALE, "PXA210(1st ver core)", 315 pxa2x0_steppings }, 316 { CPU_ID_PXA250B, CPU_CLASS_XSCALE, "PXA250(3rd ver core)", 317 pxa2x0_steppings }, 318 { CPU_ID_PXA210B, CPU_CLASS_XSCALE, "PXA210(3rd ver core)", 319 pxa2x0_steppings }, 320 321 { CPU_ID_ARM1022ES, CPU_CLASS_ARM10E, "ARM1022ES", 322 generic_steppings }, 323 324 { 0, CPU_CLASS_NONE, NULL, NULL } 325 }; 326 327 struct cpu_classtab { 328 const char *class_name; 329 const char *class_option; 330 }; 331 332 const struct cpu_classtab cpu_classes[] = { 333 { "unknown", NULL }, /* CPU_CLASS_NONE */ 334 { "ARM2", "CPU_ARM2" }, /* CPU_CLASS_ARM2 */ 335 { "ARM2as", "CPU_ARM250" }, /* CPU_CLASS_ARM2AS */ 336 { "ARM3", "CPU_ARM3" }, /* CPU_CLASS_ARM3 */ 337 { "ARM6", "CPU_ARM6" }, /* CPU_CLASS_ARM6 */ 338 { "ARM7", "CPU_ARM7" }, /* CPU_CLASS_ARM7 */ 339 { "ARM7TDMI", "CPU_ARM7TDMI" }, /* CPU_CLASS_ARM7TDMI */ 340 { "ARM8", "CPU_ARM8" }, /* CPU_CLASS_ARM8 */ 341 { "ARM9TDMI", NULL }, /* CPU_CLASS_ARM9TDMI */ 342 { "ARM9E-S", NULL }, /* CPU_CLASS_ARM9ES */ 343 { "SA-1", "CPU_SA110" }, /* CPU_CLASS_SA1 */ 344 { "XScale", "CPU_XSCALE_..." }, /* CPU_CLASS_XSCALE */ 345 { "ARM10E", NULL }, /* CPU_CLASS_ARM10E */ 346 }; 347 348 /* 349 * Report the type of the specifed arm processor. This uses the generic and 350 * arm specific information in the cpu structure to identify the processor. 351 * The remaining fields in the cpu structure are filled in appropriately. 352 */ 353 354 static const char *wtnames[] = { 355 "write-through", 356 "write-back", 357 "write-back", 358 "**unknown 3**", 359 "**unknown 4**", 360 "write-back-locking", /* XXX XScale-specific? */ 361 "write-back-locking-A", 362 "write-back-locking-B", 363 "**unknown 8**", 364 "**unknown 9**", 365 "**unknown 10**", 366 "**unknown 11**", 367 "**unknown 12**", 368 "**unknown 13**", 369 "**unknown 14**", 370 "**unknown 15**", 371 }; 372 373 void 374 identify_arm_cpu(struct device *dv, struct cpu_info *ci) 375 { 376 u_int cpuid; 377 enum cpu_class cpu_class; 378 int i; 379 380 cpuid = ci->ci_cpuid; 381 382 if (cpuid == 0) { 383 printf("Processor failed probe - no CPU ID\n"); 384 return; 385 } 386 387 for (i = 0; cpuids[i].cpuid != 0; i++) 388 if (cpuids[i].cpuid == (cpuid & CPU_ID_CPU_MASK)) { 389 cpu_class = cpuids[i].cpu_class; 390 sprintf(cpu_model, "%s %s (%s core)", 391 cpuids[i].cpu_name, 392 cpuids[i].cpu_steppings[cpuid & 393 CPU_ID_REVISION_MASK], 394 cpu_classes[cpu_class].class_name); 395 break; 396 } 397 398 if (cpuids[i].cpuid == 0) 399 sprintf(cpu_model, "unknown CPU (ID = 0x%x)", cpuid); 400 401 printf(": %s\n", cpu_model); 402 403 printf("%s:", dv->dv_xname); 404 405 switch (cpu_class) { 406 case CPU_CLASS_ARM6: 407 case CPU_CLASS_ARM7: 408 case CPU_CLASS_ARM7TDMI: 409 case CPU_CLASS_ARM8: 410 if ((ci->ci_ctrl & CPU_CONTROL_IDC_ENABLE) == 0) 411 printf(" IDC disabled"); 412 else 413 printf(" IDC enabled"); 414 break; 415 case CPU_CLASS_ARM9TDMI: 416 case CPU_CLASS_SA1: 417 case CPU_CLASS_XSCALE: 418 if ((ci->ci_ctrl & CPU_CONTROL_DC_ENABLE) == 0) 419 printf(" DC disabled"); 420 else 421 printf(" DC enabled"); 422 if ((ci->ci_ctrl & CPU_CONTROL_IC_ENABLE) == 0) 423 printf(" IC disabled"); 424 else 425 printf(" IC enabled"); 426 break; 427 default: 428 break; 429 } 430 if ((ci->ci_ctrl & CPU_CONTROL_WBUF_ENABLE) == 0) 431 printf(" WB disabled"); 432 else 433 printf(" WB enabled"); 434 435 if (ci->ci_ctrl & CPU_CONTROL_LABT_ENABLE) 436 printf(" LABT"); 437 else 438 printf(" EABT"); 439 440 if (ci->ci_ctrl & CPU_CONTROL_BPRD_ENABLE) 441 printf(" branch prediction enabled"); 442 443 printf("\n"); 444 445 /* Print cache info. */ 446 if (arm_picache_line_size == 0 && arm_pdcache_line_size == 0) 447 goto skip_pcache; 448 449 if (arm_pcache_unified) { 450 printf("%s: %dKB/%dB %d-way %s unified cache\n", 451 dv->dv_xname, arm_pdcache_size / 1024, 452 arm_pdcache_line_size, arm_pdcache_ways, 453 wtnames[arm_pcache_type]); 454 } else { 455 printf("%s: %dKB/%dB %d-way Instruction cache\n", 456 dv->dv_xname, arm_picache_size / 1024, 457 arm_picache_line_size, arm_picache_ways); 458 printf("%s: %dKB/%dB %d-way %s Data cache\n", 459 dv->dv_xname, arm_pdcache_size / 1024, 460 arm_pdcache_line_size, arm_pdcache_ways, 461 wtnames[arm_pcache_type]); 462 } 463 464 skip_pcache: 465 466 switch (cpu_class) { 467 #ifdef CPU_ARM2 468 case CPU_CLASS_ARM2: 469 #endif 470 #ifdef CPU_ARM250 471 case CPU_CLASS_ARM2AS: 472 #endif 473 #ifdef CPU_ARM3 474 case CPU_CLASS_ARM3: 475 #endif 476 #ifdef CPU_ARM6 477 case CPU_CLASS_ARM6: 478 #endif 479 #ifdef CPU_ARM7 480 case CPU_CLASS_ARM7: 481 #endif 482 #ifdef CPU_ARM7TDMI 483 case CPU_CLASS_ARM7TDMI: 484 #endif 485 #ifdef CPU_ARM8 486 case CPU_CLASS_ARM8: 487 #endif 488 #ifdef CPU_ARM9 489 case CPU_CLASS_ARM9TDMI: 490 #endif 491 #if defined(CPU_SA110) || defined(CPU_SA1100) || \ 492 defined(CPU_SA1110) || defined(CPU_IXP12X0) 493 case CPU_CLASS_SA1: 494 #endif 495 #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 496 defined(CPU_XSCALE_PXA2X0) 497 case CPU_CLASS_XSCALE: 498 #endif 499 break; 500 default: 501 if (cpu_classes[cpu_class].class_option != NULL) 502 printf("%s: %s does not fully support this CPU." 503 "\n", dv->dv_xname, ostype); 504 else { 505 printf("%s: This kernel does not fully support " 506 "this CPU.\n", dv->dv_xname); 507 printf("%s: Recompile with \"options %s\" to " 508 "correct this.\n", dv->dv_xname, 509 cpu_classes[cpu_class].class_option); 510 } 511 break; 512 } 513 514 } 515 516 /* End of cpu.c */ 517
Indexes created Tue Sep 23 14:10:03 GMT 2025