cpu.c revision 1.45.2.1
1 /* $NetBSD: cpu.c,v 1.45.2.1 2002/10/19 15:12:52 bjh21 Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Mark Brinicombe. 5 * Copyright (c) 1995 Brini. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Brini. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * cpu.c 38 * 39 * Probing and configuration for the master cpu 40 * 41 * Created : 10/10/95 42 */ 43 44 #include "opt_armfpe.h" 45 46 #include <sys/param.h> 47 48 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.45.2.1 2002/10/19 15:12:52 bjh21 Exp $"); 49 50 #include <sys/systm.h> 51 #include <sys/malloc.h> 52 #include <sys/device.h> 53 #include <sys/proc.h> 54 #include <sys/conf.h> 55 #include <uvm/uvm_extern.h> 56 #include <machine/cpu.h> 57 58 #include <arm/cpuconf.h> 59 #include <arm/undefined.h> 60 61 #ifdef ARMFPE 62 #include <machine/bootconfig.h> /* For boot args */ 63 #include <arm/fpe-arm/armfpe.h> 64 #endif 65 66 char cpu_model[256]; 67 68 /* Prototypes */ 69 void identify_arm_cpu(struct device *dv, struct cpu_info *); 70 71 /* 72 * Identify the master (boot) CPU 73 */ 74 75 void 76 cpu_attach(struct device *dv) 77 { 78 int usearmfpe; 79 80 usearmfpe = 1; /* when compiled in, its enabled by default */ 81 82 #ifdef MULTIPROCESSOR 83 if (curcpu()->ci_idlepcb == NULL) 84 cpu_alloc_idlepcb(curcpu()); 85 #endif 86 87 curcpu()->ci_dev = dv; 88 89 evcnt_attach_dynamic(&curcpu()->ci_arm700bugcount, EVCNT_TYPE_MISC, 90 NULL, dv->dv_xname, "arm700swibug"); 91 92 /* Get the cpu ID from coprocessor 15 */ 93 94 curcpu()->ci_arm_cpuid = cpu_id(); 95 curcpu()->ci_arm_cputype = curcpu()->ci_arm_cpuid & CPU_ID_CPU_MASK; 96 curcpu()->ci_arm_cpurev = 97 curcpu()->ci_arm_cpuid & CPU_ID_REVISION_MASK; 98 99 identify_arm_cpu(dv, curcpu()); 100 101 if (curcpu()->ci_arm_cputype == CPU_ID_SA110 && 102 curcpu()->ci_arm_cpurev < 3) { 103 printf("%s: SA-110 with bugged STM^ instruction\n", 104 dv->dv_xname); 105 } 106 107 #ifdef CPU_ARM8 108 if ((curcpu()->ci_arm_cpuid & CPU_ID_CPU_MASK) == CPU_ID_ARM810) { 109 int clock = arm8_clock_config(0, 0); 110 char *fclk; 111 printf("%s: ARM810 cp15=%02x", dv->dv_xname, clock); 112 printf(" clock:%s", (clock & 1) ? " dynamic" : ""); 113 printf("%s", (clock & 2) ? " sync" : ""); 114 switch ((clock >> 2) & 3) { 115 case 0: 116 fclk = "bus clock"; 117 break; 118 case 1: 119 fclk = "ref clock"; 120 break; 121 case 3: 122 fclk = "pll"; 123 break; 124 default: 125 fclk = "illegal"; 126 break; 127 } 128 printf(" fclk source=%s\n", fclk); 129 } 130 #endif 131 132 #ifdef ARMFPE 133 /* 134 * Ok now we test for an FPA 135 * At this point no floating point emulator has been installed. 136 * This means any FP instruction will cause undefined exception. 137 * We install a temporay coproc 1 handler which will modify 138 * undefined_test if it is called. 139 * We then try to read the FP status register. If undefined_test 140 * has been decremented then the instruction was not handled by 141 * an FPA so we know the FPA is missing. If undefined_test is 142 * still 1 then we know the instruction was handled by an FPA. 143 * We then remove our test handler and look at the 144 * FP status register for identification. 145 */ 146 147 /* 148 * Ok if ARMFPE is defined and the boot options request the 149 * ARM FPE then it will be installed as the FPE. 150 * This is just while I work on integrating the new FPE. 151 * It means the new FPE gets installed if compiled int (ARMFPE 152 * defined) and also gives me a on/off option when I boot in 153 * case the new FPE is causing panics. 154 */ 155 156 157 if (boot_args) 158 get_bootconf_option(boot_args, "armfpe", 159 BOOTOPT_TYPE_BOOLEAN, &usearmfpe); 160 if (usearmfpe) 161 initialise_arm_fpe(); 162 #endif 163 } 164 165 enum cpu_class { 166 CPU_CLASS_NONE, 167 CPU_CLASS_ARM2, 168 CPU_CLASS_ARM2AS, 169 CPU_CLASS_ARM3, 170 CPU_CLASS_ARM6, 171 CPU_CLASS_ARM7, 172 CPU_CLASS_ARM7TDMI, 173 CPU_CLASS_ARM8, 174 CPU_CLASS_ARM9TDMI, 175 CPU_CLASS_ARM9ES, 176 CPU_CLASS_SA1, 177 CPU_CLASS_XSCALE, 178 CPU_CLASS_ARM10E 179 }; 180 181 static const char * const generic_steppings[16] = { 182 "rev 0", "rev 1", "rev 2", "rev 3", 183 "rev 4", "rev 5", "rev 6", "rev 7", 184 "rev 8", "rev 9", "rev 10", "rev 11", 185 "rev 12", "rev 13", "rev 14", "rev 15", 186 }; 187 188 static const char * const sa110_steppings[16] = { 189 "rev 0", "step J", "step K", "step S", 190 "step T", "rev 5", "rev 6", "rev 7", 191 "rev 8", "rev 9", "rev 10", "rev 11", 192 "rev 12", "rev 13", "rev 14", "rev 15", 193 }; 194 195 static const char * const sa1100_steppings[16] = { 196 "rev 0", "step B", "step C", "rev 3", 197 "rev 4", "rev 5", "rev 6", "rev 7", 198 "step D", "step E", "rev 10" "step G", 199 "rev 12", "rev 13", "rev 14", "rev 15", 200 }; 201 202 static const char * const sa1110_steppings[16] = { 203 "step A-0", "rev 1", "rev 2", "rev 3", 204 "step B-0", "step B-1", "step B-2", "step B-3", 205 "step B-4", "step B-5", "rev 10", "rev 11", 206 "rev 12", "rev 13", "rev 14", "rev 15", 207 }; 208 209 static const char * const ixp12x0_steppings[16] = { 210 "(IXP1200 step A)", "(IXP1200 step B)", 211 "rev 2", "(IXP1200 step C)", 212 "(IXP1200 step D)", "(IXP1240/1250 step A)", 213 "(IXP1240 step B)", "(IXP1250 step B)", 214 "rev 8", "rev 9", "rev 10", "rev 11", 215 "rev 12", "rev 13", "rev 14", "rev 15", 216 }; 217 218 static const char * const xscale_steppings[16] = { 219 "step A-0", "step A-1", "step B-0", "step C-0", 220 "step D-0", "rev 5", "rev 6", "rev 7", 221 "rev 8", "rev 9", "rev 10", "rev 11", 222 "rev 12", "rev 13", "rev 14", "rev 15", 223 }; 224 225 static const char * const i80321_steppings[16] = { 226 "step A-0", "step B-0", "rev 2", "rev 3", 227 "rev 4", "rev 5", "rev 6", "rev 7", 228 "rev 8", "rev 9", "rev 10", "rev 11", 229 "rev 12", "rev 13", "rev 14", "rev 15", 230 }; 231 232 static const char * const pxa2x0_steppings[16] = { 233 "step A-0", "step A-1", "step B-0", "step B-1", 234 "rev 4", "rev 5", "rev 6", "rev 7", 235 "rev 8", "rev 9", "rev 10", "rev 11", 236 "rev 12", "rev 13", "rev 14", "rev 15", 237 }; 238 239 struct cpuidtab { 240 u_int32_t cpuid; 241 enum cpu_class cpu_class; 242 const char *cpu_name; 243 const char * const *cpu_steppings; 244 }; 245 246 const struct cpuidtab cpuids[] = { 247 { CPU_ID_ARM2, CPU_CLASS_ARM2, "ARM2", 248 generic_steppings }, 249 { CPU_ID_ARM250, CPU_CLASS_ARM2AS, "ARM250", 250 generic_steppings }, 251 252 { CPU_ID_ARM3, CPU_CLASS_ARM3, "ARM3", 253 generic_steppings }, 254 255 { CPU_ID_ARM600, CPU_CLASS_ARM6, "ARM600", 256 generic_steppings }, 257 { CPU_ID_ARM610, CPU_CLASS_ARM6, "ARM610", 258 generic_steppings }, 259 { CPU_ID_ARM620, CPU_CLASS_ARM6, "ARM620", 260 generic_steppings }, 261 262 { CPU_ID_ARM700, CPU_CLASS_ARM7, "ARM700", 263 generic_steppings }, 264 { CPU_ID_ARM710, CPU_CLASS_ARM7, "ARM710", 265 generic_steppings }, 266 { CPU_ID_ARM7500, CPU_CLASS_ARM7, "ARM7500", 267 generic_steppings }, 268 { CPU_ID_ARM710A, CPU_CLASS_ARM7, "ARM710a", 269 generic_steppings }, 270 { CPU_ID_ARM7500FE, CPU_CLASS_ARM7, "ARM7500FE", 271 generic_steppings }, 272 { CPU_ID_ARM710T, CPU_CLASS_ARM7TDMI, "ARM710T", 273 generic_steppings }, 274 { CPU_ID_ARM720T, CPU_CLASS_ARM7TDMI, "ARM720T", 275 generic_steppings }, 276 { CPU_ID_ARM740T8K, CPU_CLASS_ARM7TDMI, "ARM740T (8 KB cache)", 277 generic_steppings }, 278 { CPU_ID_ARM740T4K, CPU_CLASS_ARM7TDMI, "ARM740T (4 KB cache)", 279 generic_steppings }, 280 281 { CPU_ID_ARM810, CPU_CLASS_ARM8, "ARM810", 282 generic_steppings }, 283 284 { CPU_ID_ARM920T, CPU_CLASS_ARM9TDMI, "ARM920T", 285 generic_steppings }, 286 { CPU_ID_ARM922T, CPU_CLASS_ARM9TDMI, "ARM922T", 287 generic_steppings }, 288 { CPU_ID_ARM940T, CPU_CLASS_ARM9TDMI, "ARM940T", 289 generic_steppings }, 290 { CPU_ID_ARM946ES, CPU_CLASS_ARM9ES, "ARM946E-S", 291 generic_steppings }, 292 { CPU_ID_ARM966ES, CPU_CLASS_ARM9ES, "ARM966E-S", 293 generic_steppings }, 294 { CPU_ID_ARM966ESR1, CPU_CLASS_ARM9ES, "ARM966E-S", 295 generic_steppings }, 296 297 { CPU_ID_SA110, CPU_CLASS_SA1, "SA-110", 298 sa110_steppings }, 299 { CPU_ID_SA1100, CPU_CLASS_SA1, "SA-1100", 300 sa1100_steppings }, 301 { CPU_ID_SA1110, CPU_CLASS_SA1, "SA-1110", 302 sa1110_steppings }, 303 304 { CPU_ID_IXP1200, CPU_CLASS_SA1, "IXP1200", 305 ixp12x0_steppings }, 306 307 { CPU_ID_80200, CPU_CLASS_XSCALE, "i80200", 308 xscale_steppings }, 309 310 { CPU_ID_80321_400, CPU_CLASS_XSCALE, "i80321 400MHz", 311 i80321_steppings }, 312 { CPU_ID_80321_600, CPU_CLASS_XSCALE, "i80321 600MHz", 313 i80321_steppings }, 314 { CPU_ID_80321_400_B0, CPU_CLASS_XSCALE, "i80321 400MHz", 315 i80321_steppings }, 316 { CPU_ID_80321_600_B0, CPU_CLASS_XSCALE, "i80321 600MHz", 317 i80321_steppings }, 318 319 { CPU_ID_PXA250A, CPU_CLASS_XSCALE, "PXA250(1st ver core)", 320 pxa2x0_steppings }, 321 { CPU_ID_PXA210A, CPU_CLASS_XSCALE, "PXA210(1st ver core)", 322 pxa2x0_steppings }, 323 { CPU_ID_PXA250B, CPU_CLASS_XSCALE, "PXA250(3rd ver core)", 324 pxa2x0_steppings }, 325 { CPU_ID_PXA210B, CPU_CLASS_XSCALE, "PXA210(3rd ver core)", 326 pxa2x0_steppings }, 327 328 { CPU_ID_ARM1022ES, CPU_CLASS_ARM10E, "ARM1022ES", 329 generic_steppings }, 330 331 { 0, CPU_CLASS_NONE, NULL, NULL } 332 }; 333 334 struct cpu_classtab { 335 const char *class_name; 336 const char *class_option; 337 }; 338 339 const struct cpu_classtab cpu_classes[] = { 340 { "unknown", NULL }, /* CPU_CLASS_NONE */ 341 { "ARM2", "CPU_ARM2" }, /* CPU_CLASS_ARM2 */ 342 { "ARM2as", "CPU_ARM250" }, /* CPU_CLASS_ARM2AS */ 343 { "ARM3", "CPU_ARM3" }, /* CPU_CLASS_ARM3 */ 344 { "ARM6", "CPU_ARM6" }, /* CPU_CLASS_ARM6 */ 345 { "ARM7", "CPU_ARM7" }, /* CPU_CLASS_ARM7 */ 346 { "ARM7TDMI", "CPU_ARM7TDMI" }, /* CPU_CLASS_ARM7TDMI */ 347 { "ARM8", "CPU_ARM8" }, /* CPU_CLASS_ARM8 */ 348 { "ARM9TDMI", NULL }, /* CPU_CLASS_ARM9TDMI */ 349 { "ARM9E-S", NULL }, /* CPU_CLASS_ARM9ES */ 350 { "SA-1", "CPU_SA110" }, /* CPU_CLASS_SA1 */ 351 { "XScale", "CPU_XSCALE_..." }, /* CPU_CLASS_XSCALE */ 352 { "ARM10E", NULL }, /* CPU_CLASS_ARM10E */ 353 }; 354 355 /* 356 * Report the type of the specifed arm processor. This uses the generic and 357 * arm specific information in the cpu structure to identify the processor. 358 * The remaining fields in the cpu structure are filled in appropriately. 359 */ 360 361 static const char * const wtnames[] = { 362 "write-through", 363 "write-back", 364 "write-back", 365 "**unknown 3**", 366 "**unknown 4**", 367 "write-back-locking", /* XXX XScale-specific? */ 368 "write-back-locking-A", 369 "write-back-locking-B", 370 "**unknown 8**", 371 "**unknown 9**", 372 "**unknown 10**", 373 "**unknown 11**", 374 "**unknown 12**", 375 "**unknown 13**", 376 "**unknown 14**", 377 "**unknown 15**", 378 }; 379 380 void 381 identify_arm_cpu(struct device *dv, struct cpu_info *ci) 382 { 383 u_int cpuid; 384 enum cpu_class cpu_class; 385 int i; 386 387 cpuid = ci->ci_arm_cpuid; 388 389 if (cpuid == 0) { 390 printf("Processor failed probe - no CPU ID\n"); 391 return; 392 } 393 394 for (i = 0; cpuids[i].cpuid != 0; i++) 395 if (cpuids[i].cpuid == (cpuid & CPU_ID_CPU_MASK)) { 396 cpu_class = cpuids[i].cpu_class; 397 sprintf(cpu_model, "%s %s (%s core)", 398 cpuids[i].cpu_name, 399 cpuids[i].cpu_steppings[cpuid & 400 CPU_ID_REVISION_MASK], 401 cpu_classes[cpu_class].class_name); 402 break; 403 } 404 405 if (cpuids[i].cpuid == 0) 406 sprintf(cpu_model, "unknown CPU (ID = 0x%x)", cpuid); 407 408 printf(": %s\n", cpu_model); 409 410 printf("%s:", dv->dv_xname); 411 412 switch (cpu_class) { 413 case CPU_CLASS_ARM6: 414 case CPU_CLASS_ARM7: 415 case CPU_CLASS_ARM7TDMI: 416 case CPU_CLASS_ARM8: 417 if ((ci->ci_ctrl & CPU_CONTROL_IDC_ENABLE) == 0) 418 printf(" IDC disabled"); 419 else 420 printf(" IDC enabled"); 421 break; 422 case CPU_CLASS_ARM9TDMI: 423 case CPU_CLASS_SA1: 424 case CPU_CLASS_XSCALE: 425 if ((ci->ci_ctrl & CPU_CONTROL_DC_ENABLE) == 0) 426 printf(" DC disabled"); 427 else 428 printf(" DC enabled"); 429 if ((ci->ci_ctrl & CPU_CONTROL_IC_ENABLE) == 0) 430 printf(" IC disabled"); 431 else 432 printf(" IC enabled"); 433 break; 434 default: 435 break; 436 } 437 if ((ci->ci_ctrl & CPU_CONTROL_WBUF_ENABLE) == 0) 438 printf(" WB disabled"); 439 else 440 printf(" WB enabled"); 441 442 if (ci->ci_ctrl & CPU_CONTROL_LABT_ENABLE) 443 printf(" LABT"); 444 else 445 printf(" EABT"); 446 447 if (ci->ci_ctrl & CPU_CONTROL_BPRD_ENABLE) 448 printf(" branch prediction enabled"); 449 450 printf("\n"); 451 452 /* Print cache info. */ 453 if (arm_picache_line_size == 0 && arm_pdcache_line_size == 0) 454 goto skip_pcache; 455 456 if (arm_pcache_unified) { 457 printf("%s: %dKB/%dB %d-way %s unified cache\n", 458 dv->dv_xname, arm_pdcache_size / 1024, 459 arm_pdcache_line_size, arm_pdcache_ways, 460 wtnames[arm_pcache_type]); 461 } else { 462 printf("%s: %dKB/%dB %d-way Instruction cache\n", 463 dv->dv_xname, arm_picache_size / 1024, 464 arm_picache_line_size, arm_picache_ways); 465 printf("%s: %dKB/%dB %d-way %s Data cache\n", 466 dv->dv_xname, arm_pdcache_size / 1024, 467 arm_pdcache_line_size, arm_pdcache_ways, 468 wtnames[arm_pcache_type]); 469 } 470 471 skip_pcache: 472 473 switch (cpu_class) { 474 #ifdef CPU_ARM2 475 case CPU_CLASS_ARM2: 476 #endif 477 #ifdef CPU_ARM250 478 case CPU_CLASS_ARM2AS: 479 #endif 480 #ifdef CPU_ARM3 481 case CPU_CLASS_ARM3: 482 #endif 483 #ifdef CPU_ARM6 484 case CPU_CLASS_ARM6: 485 #endif 486 #ifdef CPU_ARM7 487 case CPU_CLASS_ARM7: 488 #endif 489 #ifdef CPU_ARM7TDMI 490 case CPU_CLASS_ARM7TDMI: 491 #endif 492 #ifdef CPU_ARM8 493 case CPU_CLASS_ARM8: 494 #endif 495 #ifdef CPU_ARM9 496 case CPU_CLASS_ARM9TDMI: 497 #endif 498 #if defined(CPU_SA110) || defined(CPU_SA1100) || \ 499 defined(CPU_SA1110) || defined(CPU_IXP12X0) 500 case CPU_CLASS_SA1: 501 #endif 502 #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 503 defined(CPU_XSCALE_PXA2X0) 504 case CPU_CLASS_XSCALE: 505 #endif 506 break; 507 default: 508 if (cpu_classes[cpu_class].class_option != NULL) 509 printf("%s: %s does not fully support this CPU." 510 "\n", dv->dv_xname, ostype); 511 else { 512 printf("%s: This kernel does not fully support " 513 "this CPU.\n", dv->dv_xname); 514 printf("%s: Recompile with \"options %s\" to " 515 "correct this.\n", dv->dv_xname, 516 cpu_classes[cpu_class].class_option); 517 } 518 break; 519 } 520 521 } 522 #ifdef MULTIPROCESSOR 523 int 524 cpu_alloc_idlepcb(struct cpu_info *ci) 525 { 526 vaddr_t uaddr; 527 struct pcb *pcb; 528 struct trapframe *tf; 529 int error; 530 531 /* 532 * Generate a kernel stack and PCB (in essence, a u-area) for the 533 * new CPU. 534 */ 535 uaddr = uvm_uarea_alloc(); 536 error = uvm_fault_wire(kernel_map, uaddr, uaddr + USPACE, 537 VM_FAULT_WIRE, VM_PROT_READ | VM_PROT_WRITE); 538 if (error) 539 return error; 540 ci->ci_idlepcb = pcb = (struct pcb *)uaddr; 541 542 /* 543 * This code is largely derived from cpu_fork(), with which it 544 * should perhaps be shared. 545 */ 546 547 /* Copy the pcb */ 548 *pcb = proc0.p_addr->u_pcb; 549 550 /* Set up the undefined stack for the process. */ 551 pcb->pcb_un.un_32.pcb32_und_sp = uaddr + USPACE_UNDEF_STACK_TOP; 552 pcb->pcb_un.un_32.pcb32_sp = uaddr + USPACE_SVC_STACK_TOP; 553 554 #ifdef STACKCHECKS 555 /* Fill the undefined stack with a known pattern */ 556 memset(((u_char *)uaddr) + USPACE_UNDEF_STACK_BOTTOM, 0xdd, 557 (USPACE_UNDEF_STACK_TOP - USPACE_UNDEF_STACK_BOTTOM)); 558 /* Fill the kernel stack with a known pattern */ 559 memset(((u_char *)uaddr) + USPACE_SVC_STACK_BOTTOM, 0xdd, 560 (USPACE_SVC_STACK_TOP - USPACE_SVC_STACK_BOTTOM)); 561 #endif /* STACKCHECKS */ 562 563 pcb->pcb_tf = tf = 564 (struct trapframe *)pcb->pcb_un.un_32.pcb32_sp - 1; 565 *tf = *proc0.p_addr->u_pcb.pcb_tf; 566 return 0; 567 } 568 #endif /* MULTIPROCESSOR */ 569 570 /* End of cpu.c */ 571
Indexes created Wed Oct 15 16:09:53 GMT 2025