cpu.c revision 1.48
1 /* $NetBSD: cpu.c,v 1.48 2003/02/14 16:00:33 rjs Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Mark Brinicombe. 5 * Copyright (c) 1995 Brini. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Brini. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * cpu.c 38 * 39 * Probing and configuration for the master cpu 40 * 41 * Created : 10/10/95 42 */ 43 44 #include "opt_armfpe.h" 45 46 #include <sys/param.h> 47 48 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.48 2003/02/14 16:00:33 rjs Exp $"); 49 50 #include <sys/systm.h> 51 #include <sys/malloc.h> 52 #include <sys/device.h> 53 #include <sys/proc.h> 54 #include <sys/conf.h> 55 #include <uvm/uvm_extern.h> 56 #include <machine/cpu.h> 57 58 #include <arm/cpuconf.h> 59 #include <arm/undefined.h> 60 61 #ifdef ARMFPE 62 #include <machine/bootconfig.h> /* For boot args */ 63 #include <arm/fpe-arm/armfpe.h> 64 #endif 65 66 char cpu_model[256]; 67 68 /* Prototypes */ 69 void identify_arm_cpu(struct device *dv, struct cpu_info *); 70 71 /* 72 * Identify the master (boot) CPU 73 */ 74 75 void 76 cpu_attach(struct device *dv) 77 { 78 int usearmfpe; 79 80 usearmfpe = 1; /* when compiled in, its enabled by default */ 81 82 curcpu()->ci_dev = dv; 83 84 evcnt_attach_dynamic(&curcpu()->ci_arm700bugcount, EVCNT_TYPE_MISC, 85 NULL, dv->dv_xname, "arm700swibug"); 86 87 /* Get the cpu ID from coprocessor 15 */ 88 89 curcpu()->ci_arm_cpuid = cpu_id(); 90 curcpu()->ci_arm_cputype = curcpu()->ci_arm_cpuid & CPU_ID_CPU_MASK; 91 curcpu()->ci_arm_cpurev = 92 curcpu()->ci_arm_cpuid & CPU_ID_REVISION_MASK; 93 94 identify_arm_cpu(dv, curcpu()); 95 96 if (curcpu()->ci_arm_cputype == CPU_ID_SA110 && 97 curcpu()->ci_arm_cpurev < 3) { 98 printf("%s: SA-110 with bugged STM^ instruction\n", 99 dv->dv_xname); 100 } 101 102 #ifdef CPU_ARM8 103 if ((curcpu()->ci_arm_cpuid & CPU_ID_CPU_MASK) == CPU_ID_ARM810) { 104 int clock = arm8_clock_config(0, 0); 105 char *fclk; 106 printf("%s: ARM810 cp15=%02x", dv->dv_xname, clock); 107 printf(" clock:%s", (clock & 1) ? " dynamic" : ""); 108 printf("%s", (clock & 2) ? " sync" : ""); 109 switch ((clock >> 2) & 3) { 110 case 0: 111 fclk = "bus clock"; 112 break; 113 case 1: 114 fclk = "ref clock"; 115 break; 116 case 3: 117 fclk = "pll"; 118 break; 119 default: 120 fclk = "illegal"; 121 break; 122 } 123 printf(" fclk source=%s\n", fclk); 124 } 125 #endif 126 127 #ifdef ARMFPE 128 /* 129 * Ok now we test for an FPA 130 * At this point no floating point emulator has been installed. 131 * This means any FP instruction will cause undefined exception. 132 * We install a temporay coproc 1 handler which will modify 133 * undefined_test if it is called. 134 * We then try to read the FP status register. If undefined_test 135 * has been decremented then the instruction was not handled by 136 * an FPA so we know the FPA is missing. If undefined_test is 137 * still 1 then we know the instruction was handled by an FPA. 138 * We then remove our test handler and look at the 139 * FP status register for identification. 140 */ 141 142 /* 143 * Ok if ARMFPE is defined and the boot options request the 144 * ARM FPE then it will be installed as the FPE. 145 * This is just while I work on integrating the new FPE. 146 * It means the new FPE gets installed if compiled int (ARMFPE 147 * defined) and also gives me a on/off option when I boot in 148 * case the new FPE is causing panics. 149 */ 150 151 152 if (boot_args) 153 get_bootconf_option(boot_args, "armfpe", 154 BOOTOPT_TYPE_BOOLEAN, &usearmfpe); 155 if (usearmfpe) 156 initialise_arm_fpe(); 157 #endif 158 } 159 160 enum cpu_class { 161 CPU_CLASS_NONE, 162 CPU_CLASS_ARM2, 163 CPU_CLASS_ARM2AS, 164 CPU_CLASS_ARM3, 165 CPU_CLASS_ARM6, 166 CPU_CLASS_ARM7, 167 CPU_CLASS_ARM7TDMI, 168 CPU_CLASS_ARM8, 169 CPU_CLASS_ARM9TDMI, 170 CPU_CLASS_ARM9ES, 171 CPU_CLASS_SA1, 172 CPU_CLASS_XSCALE, 173 CPU_CLASS_ARM10E 174 }; 175 176 static const char * const generic_steppings[16] = { 177 "rev 0", "rev 1", "rev 2", "rev 3", 178 "rev 4", "rev 5", "rev 6", "rev 7", 179 "rev 8", "rev 9", "rev 10", "rev 11", 180 "rev 12", "rev 13", "rev 14", "rev 15", 181 }; 182 183 static const char * const sa110_steppings[16] = { 184 "rev 0", "step J", "step K", "step S", 185 "step T", "rev 5", "rev 6", "rev 7", 186 "rev 8", "rev 9", "rev 10", "rev 11", 187 "rev 12", "rev 13", "rev 14", "rev 15", 188 }; 189 190 static const char * const sa1100_steppings[16] = { 191 "rev 0", "step B", "step C", "rev 3", 192 "rev 4", "rev 5", "rev 6", "rev 7", 193 "step D", "step E", "rev 10" "step G", 194 "rev 12", "rev 13", "rev 14", "rev 15", 195 }; 196 197 static const char * const sa1110_steppings[16] = { 198 "step A-0", "rev 1", "rev 2", "rev 3", 199 "step B-0", "step B-1", "step B-2", "step B-3", 200 "step B-4", "step B-5", "rev 10", "rev 11", 201 "rev 12", "rev 13", "rev 14", "rev 15", 202 }; 203 204 static const char * const ixp12x0_steppings[16] = { 205 "(IXP1200 step A)", "(IXP1200 step B)", 206 "rev 2", "(IXP1200 step C)", 207 "(IXP1200 step D)", "(IXP1240/1250 step A)", 208 "(IXP1240 step B)", "(IXP1250 step B)", 209 "rev 8", "rev 9", "rev 10", "rev 11", 210 "rev 12", "rev 13", "rev 14", "rev 15", 211 }; 212 213 static const char * const xscale_steppings[16] = { 214 "step A-0", "step A-1", "step B-0", "step C-0", 215 "step D-0", "rev 5", "rev 6", "rev 7", 216 "rev 8", "rev 9", "rev 10", "rev 11", 217 "rev 12", "rev 13", "rev 14", "rev 15", 218 }; 219 220 static const char * const i80321_steppings[16] = { 221 "step A-0", "step B-0", "rev 2", "rev 3", 222 "rev 4", "rev 5", "rev 6", "rev 7", 223 "rev 8", "rev 9", "rev 10", "rev 11", 224 "rev 12", "rev 13", "rev 14", "rev 15", 225 }; 226 227 static const char * const pxa2x0_steppings[16] = { 228 "step A-0", "step A-1", "step B-0", "step B-1", 229 "step B-2", "step C-0", "rev 6", "rev 7", 230 "rev 8", "rev 9", "rev 10", "rev 11", 231 "rev 12", "rev 13", "rev 14", "rev 15", 232 }; 233 234 struct cpuidtab { 235 u_int32_t cpuid; 236 enum cpu_class cpu_class; 237 const char *cpu_name; 238 const char * const *cpu_steppings; 239 }; 240 241 const struct cpuidtab cpuids[] = { 242 { CPU_ID_ARM2, CPU_CLASS_ARM2, "ARM2", 243 generic_steppings }, 244 { CPU_ID_ARM250, CPU_CLASS_ARM2AS, "ARM250", 245 generic_steppings }, 246 247 { CPU_ID_ARM3, CPU_CLASS_ARM3, "ARM3", 248 generic_steppings }, 249 250 { CPU_ID_ARM600, CPU_CLASS_ARM6, "ARM600", 251 generic_steppings }, 252 { CPU_ID_ARM610, CPU_CLASS_ARM6, "ARM610", 253 generic_steppings }, 254 { CPU_ID_ARM620, CPU_CLASS_ARM6, "ARM620", 255 generic_steppings }, 256 257 { CPU_ID_ARM700, CPU_CLASS_ARM7, "ARM700", 258 generic_steppings }, 259 { CPU_ID_ARM710, CPU_CLASS_ARM7, "ARM710", 260 generic_steppings }, 261 { CPU_ID_ARM7500, CPU_CLASS_ARM7, "ARM7500", 262 generic_steppings }, 263 { CPU_ID_ARM710A, CPU_CLASS_ARM7, "ARM710a", 264 generic_steppings }, 265 { CPU_ID_ARM7500FE, CPU_CLASS_ARM7, "ARM7500FE", 266 generic_steppings }, 267 { CPU_ID_ARM710T, CPU_CLASS_ARM7TDMI, "ARM710T", 268 generic_steppings }, 269 { CPU_ID_ARM720T, CPU_CLASS_ARM7TDMI, "ARM720T", 270 generic_steppings }, 271 { CPU_ID_ARM740T8K, CPU_CLASS_ARM7TDMI, "ARM740T (8 KB cache)", 272 generic_steppings }, 273 { CPU_ID_ARM740T4K, CPU_CLASS_ARM7TDMI, "ARM740T (4 KB cache)", 274 generic_steppings }, 275 276 { CPU_ID_ARM810, CPU_CLASS_ARM8, "ARM810", 277 generic_steppings }, 278 279 { CPU_ID_ARM920T, CPU_CLASS_ARM9TDMI, "ARM920T", 280 generic_steppings }, 281 { CPU_ID_ARM922T, CPU_CLASS_ARM9TDMI, "ARM922T", 282 generic_steppings }, 283 { CPU_ID_ARM940T, CPU_CLASS_ARM9TDMI, "ARM940T", 284 generic_steppings }, 285 { CPU_ID_ARM946ES, CPU_CLASS_ARM9ES, "ARM946E-S", 286 generic_steppings }, 287 { CPU_ID_ARM966ES, CPU_CLASS_ARM9ES, "ARM966E-S", 288 generic_steppings }, 289 { CPU_ID_ARM966ESR1, CPU_CLASS_ARM9ES, "ARM966E-S", 290 generic_steppings }, 291 292 { CPU_ID_SA110, CPU_CLASS_SA1, "SA-110", 293 sa110_steppings }, 294 { CPU_ID_SA1100, CPU_CLASS_SA1, "SA-1100", 295 sa1100_steppings }, 296 { CPU_ID_SA1110, CPU_CLASS_SA1, "SA-1110", 297 sa1110_steppings }, 298 299 { CPU_ID_IXP1200, CPU_CLASS_SA1, "IXP1200", 300 ixp12x0_steppings }, 301 302 { CPU_ID_80200, CPU_CLASS_XSCALE, "i80200", 303 xscale_steppings }, 304 305 { CPU_ID_80321_400, CPU_CLASS_XSCALE, "i80321 400MHz", 306 i80321_steppings }, 307 { CPU_ID_80321_600, CPU_CLASS_XSCALE, "i80321 600MHz", 308 i80321_steppings }, 309 { CPU_ID_80321_400_B0, CPU_CLASS_XSCALE, "i80321 400MHz", 310 i80321_steppings }, 311 { CPU_ID_80321_600_B0, CPU_CLASS_XSCALE, "i80321 600MHz", 312 i80321_steppings }, 313 314 { CPU_ID_PXA250A, CPU_CLASS_XSCALE, "PXA250", 315 pxa2x0_steppings }, 316 { CPU_ID_PXA210A, CPU_CLASS_XSCALE, "PXA210", 317 pxa2x0_steppings }, 318 { CPU_ID_PXA250B, CPU_CLASS_XSCALE, "PXA250", 319 pxa2x0_steppings }, 320 { CPU_ID_PXA210B, CPU_CLASS_XSCALE, "PXA210", 321 pxa2x0_steppings }, 322 { CPU_ID_PXA250C, CPU_CLASS_XSCALE, "PXA250", 323 pxa2x0_steppings }, 324 { CPU_ID_PXA210C, CPU_CLASS_XSCALE, "PXA210", 325 pxa2x0_steppings }, 326 327 { CPU_ID_ARM1022ES, CPU_CLASS_ARM10E, "ARM1022ES", 328 generic_steppings }, 329 330 { 0, CPU_CLASS_NONE, NULL, NULL } 331 }; 332 333 struct cpu_classtab { 334 const char *class_name; 335 const char *class_option; 336 }; 337 338 const struct cpu_classtab cpu_classes[] = { 339 { "unknown", NULL }, /* CPU_CLASS_NONE */ 340 { "ARM2", "CPU_ARM2" }, /* CPU_CLASS_ARM2 */ 341 { "ARM2as", "CPU_ARM250" }, /* CPU_CLASS_ARM2AS */ 342 { "ARM3", "CPU_ARM3" }, /* CPU_CLASS_ARM3 */ 343 { "ARM6", "CPU_ARM6" }, /* CPU_CLASS_ARM6 */ 344 { "ARM7", "CPU_ARM7" }, /* CPU_CLASS_ARM7 */ 345 { "ARM7TDMI", "CPU_ARM7TDMI" }, /* CPU_CLASS_ARM7TDMI */ 346 { "ARM8", "CPU_ARM8" }, /* CPU_CLASS_ARM8 */ 347 { "ARM9TDMI", NULL }, /* CPU_CLASS_ARM9TDMI */ 348 { "ARM9E-S", NULL }, /* CPU_CLASS_ARM9ES */ 349 { "SA-1", "CPU_SA110" }, /* CPU_CLASS_SA1 */ 350 { "XScale", "CPU_XSCALE_..." }, /* CPU_CLASS_XSCALE */ 351 { "ARM10E", NULL }, /* CPU_CLASS_ARM10E */ 352 }; 353 354 /* 355 * Report the type of the specified arm processor. This uses the generic and 356 * arm specific information in the cpu structure to identify the processor. 357 * The remaining fields in the cpu structure are filled in appropriately. 358 */ 359 360 static const char * const wtnames[] = { 361 "write-through", 362 "write-back", 363 "write-back", 364 "**unknown 3**", 365 "**unknown 4**", 366 "write-back-locking", /* XXX XScale-specific? */ 367 "write-back-locking-A", 368 "write-back-locking-B", 369 "**unknown 8**", 370 "**unknown 9**", 371 "**unknown 10**", 372 "**unknown 11**", 373 "**unknown 12**", 374 "**unknown 13**", 375 "**unknown 14**", 376 "**unknown 15**", 377 }; 378 379 void 380 identify_arm_cpu(struct device *dv, struct cpu_info *ci) 381 { 382 u_int cpuid; 383 enum cpu_class cpu_class; 384 int i; 385 386 cpuid = ci->ci_arm_cpuid; 387 388 if (cpuid == 0) { 389 printf("Processor failed probe - no CPU ID\n"); 390 return; 391 } 392 393 for (i = 0; cpuids[i].cpuid != 0; i++) 394 if (cpuids[i].cpuid == (cpuid & CPU_ID_CPU_MASK)) { 395 cpu_class = cpuids[i].cpu_class; 396 sprintf(cpu_model, "%s %s (%s core)", 397 cpuids[i].cpu_name, 398 cpuids[i].cpu_steppings[cpuid & 399 CPU_ID_REVISION_MASK], 400 cpu_classes[cpu_class].class_name); 401 break; 402 } 403 404 if (cpuids[i].cpuid == 0) 405 sprintf(cpu_model, "unknown CPU (ID = 0x%x)", cpuid); 406 407 printf(": %s\n", cpu_model); 408 409 printf("%s:", dv->dv_xname); 410 411 switch (cpu_class) { 412 case CPU_CLASS_ARM6: 413 case CPU_CLASS_ARM7: 414 case CPU_CLASS_ARM7TDMI: 415 case CPU_CLASS_ARM8: 416 if ((ci->ci_ctrl & CPU_CONTROL_IDC_ENABLE) == 0) 417 printf(" IDC disabled"); 418 else 419 printf(" IDC enabled"); 420 break; 421 case CPU_CLASS_ARM9TDMI: 422 case CPU_CLASS_SA1: 423 case CPU_CLASS_XSCALE: 424 if ((ci->ci_ctrl & CPU_CONTROL_DC_ENABLE) == 0) 425 printf(" DC disabled"); 426 else 427 printf(" DC enabled"); 428 if ((ci->ci_ctrl & CPU_CONTROL_IC_ENABLE) == 0) 429 printf(" IC disabled"); 430 else 431 printf(" IC enabled"); 432 break; 433 default: 434 break; 435 } 436 if ((ci->ci_ctrl & CPU_CONTROL_WBUF_ENABLE) == 0) 437 printf(" WB disabled"); 438 else 439 printf(" WB enabled"); 440 441 if (ci->ci_ctrl & CPU_CONTROL_LABT_ENABLE) 442 printf(" LABT"); 443 else 444 printf(" EABT"); 445 446 if (ci->ci_ctrl & CPU_CONTROL_BPRD_ENABLE) 447 printf(" branch prediction enabled"); 448 449 printf("\n"); 450 451 /* Print cache info. */ 452 if (arm_picache_line_size == 0 && arm_pdcache_line_size == 0) 453 goto skip_pcache; 454 455 if (arm_pcache_unified) { 456 printf("%s: %dKB/%dB %d-way %s unified cache\n", 457 dv->dv_xname, arm_pdcache_size / 1024, 458 arm_pdcache_line_size, arm_pdcache_ways, 459 wtnames[arm_pcache_type]); 460 } else { 461 printf("%s: %dKB/%dB %d-way Instruction cache\n", 462 dv->dv_xname, arm_picache_size / 1024, 463 arm_picache_line_size, arm_picache_ways); 464 printf("%s: %dKB/%dB %d-way %s Data cache\n", 465 dv->dv_xname, arm_pdcache_size / 1024, 466 arm_pdcache_line_size, arm_pdcache_ways, 467 wtnames[arm_pcache_type]); 468 } 469 470 skip_pcache: 471 472 switch (cpu_class) { 473 #ifdef CPU_ARM2 474 case CPU_CLASS_ARM2: 475 #endif 476 #ifdef CPU_ARM250 477 case CPU_CLASS_ARM2AS: 478 #endif 479 #ifdef CPU_ARM3 480 case CPU_CLASS_ARM3: 481 #endif 482 #ifdef CPU_ARM6 483 case CPU_CLASS_ARM6: 484 #endif 485 #ifdef CPU_ARM7 486 case CPU_CLASS_ARM7: 487 #endif 488 #ifdef CPU_ARM7TDMI 489 case CPU_CLASS_ARM7TDMI: 490 #endif 491 #ifdef CPU_ARM8 492 case CPU_CLASS_ARM8: 493 #endif 494 #ifdef CPU_ARM9 495 case CPU_CLASS_ARM9TDMI: 496 #endif 497 #if defined(CPU_SA110) || defined(CPU_SA1100) || \ 498 defined(CPU_SA1110) || defined(CPU_IXP12X0) 499 case CPU_CLASS_SA1: 500 #endif 501 #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 502 defined(CPU_XSCALE_PXA2X0) 503 case CPU_CLASS_XSCALE: 504 #endif 505 break; 506 default: 507 if (cpu_classes[cpu_class].class_option != NULL) 508 printf("%s: %s does not fully support this CPU." 509 "\n", dv->dv_xname, ostype); 510 else { 511 printf("%s: This kernel does not fully support " 512 "this CPU.\n", dv->dv_xname); 513 printf("%s: Recompile with \"options %s\" to " 514 "correct this.\n", dv->dv_xname, 515 cpu_classes[cpu_class].class_option); 516 } 517 break; 518 } 519 520 } 521 #ifdef MULTIPROCESSOR 522 int 523 cpu_alloc_idlepcb(struct cpu_info *ci) 524 { 525 vaddr_t uaddr; 526 struct pcb *pcb; 527 struct trapframe *tf; 528 int error; 529 530 /* 531 * Generate a kernel stack and PCB (in essence, a u-area) for the 532 * new CPU. 533 */ 534 if (uvm_uarea_alloc(&uaddr)) { 535 error = uvm_fault_wire(kernel_map, uaddr, uaddr + USPACE, 536 VM_FAULT_WIRE, VM_PROT_READ | VM_PROT_WRITE); 537 if (error) 538 return error; 539 } 540 ci->ci_idlepcb = pcb = (struct pcb *)uaddr; 541 542 /* 543 * This code is largely derived from cpu_fork(), with which it 544 * should perhaps be shared. 545 */ 546 547 /* Copy the pcb */ 548 *pcb = proc0.p_addr->u_pcb; 549 550 /* Set up the undefined stack for the process. */ 551 pcb->pcb_un.un_32.pcb32_und_sp = uaddr + USPACE_UNDEF_STACK_TOP; 552 pcb->pcb_un.un_32.pcb32_sp = uaddr + USPACE_SVC_STACK_TOP; 553 554 #ifdef STACKCHECKS 555 /* Fill the undefined stack with a known pattern */ 556 memset(((u_char *)uaddr) + USPACE_UNDEF_STACK_BOTTOM, 0xdd, 557 (USPACE_UNDEF_STACK_TOP - USPACE_UNDEF_STACK_BOTTOM)); 558 /* Fill the kernel stack with a known pattern */ 559 memset(((u_char *)uaddr) + USPACE_SVC_STACK_BOTTOM, 0xdd, 560 (USPACE_SVC_STACK_TOP - USPACE_SVC_STACK_BOTTOM)); 561 #endif /* STACKCHECKS */ 562 563 pcb->pcb_tf = tf = 564 (struct trapframe *)pcb->pcb_un.un_32.pcb32_sp - 1; 565 *tf = *proc0.p_addr->u_pcb.pcb_tf; 566 return 0; 567 } 568 #endif /* MULTIPROCESSOR */ 569 570 /* End of cpu.c */ 571
Indexes created Fri Sep 26 08:10:20 GMT 2025