cpu.c revision 1.50
1 /* $NetBSD: cpu.c,v 1.50 2003/05/23 00:57:24 ichiro Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Mark Brinicombe. 5 * Copyright (c) 1995 Brini. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Brini. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * cpu.c 38 * 39 * Probing and configuration for the master cpu 40 * 41 * Created : 10/10/95 42 */ 43 44 #include "opt_armfpe.h" 45 46 #include <sys/param.h> 47 48 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.50 2003/05/23 00:57:24 ichiro Exp $"); 49 50 #include <sys/systm.h> 51 #include <sys/malloc.h> 52 #include <sys/device.h> 53 #include <sys/proc.h> 54 #include <sys/conf.h> 55 #include <uvm/uvm_extern.h> 56 #include <machine/cpu.h> 57 58 #include <arm/cpuconf.h> 59 #include <arm/undefined.h> 60 61 #ifdef ARMFPE 62 #include <machine/bootconfig.h> /* For boot args */ 63 #include <arm/fpe-arm/armfpe.h> 64 #endif 65 66 char cpu_model[256]; 67 68 /* Prototypes */ 69 void identify_arm_cpu(struct device *dv, struct cpu_info *); 70 71 /* 72 * Identify the master (boot) CPU 73 */ 74 75 void 76 cpu_attach(struct device *dv) 77 { 78 int usearmfpe; 79 80 usearmfpe = 1; /* when compiled in, its enabled by default */ 81 82 curcpu()->ci_dev = dv; 83 84 evcnt_attach_dynamic(&curcpu()->ci_arm700bugcount, EVCNT_TYPE_MISC, 85 NULL, dv->dv_xname, "arm700swibug"); 86 87 /* Get the cpu ID from coprocessor 15 */ 88 89 curcpu()->ci_arm_cpuid = cpu_id(); 90 curcpu()->ci_arm_cputype = curcpu()->ci_arm_cpuid & CPU_ID_CPU_MASK; 91 curcpu()->ci_arm_cpurev = 92 curcpu()->ci_arm_cpuid & CPU_ID_REVISION_MASK; 93 94 identify_arm_cpu(dv, curcpu()); 95 96 if (curcpu()->ci_arm_cputype == CPU_ID_SA110 && 97 curcpu()->ci_arm_cpurev < 3) { 98 aprint_normal("%s: SA-110 with bugged STM^ instruction\n", 99 dv->dv_xname); 100 } 101 102 #ifdef CPU_ARM8 103 if ((curcpu()->ci_arm_cpuid & CPU_ID_CPU_MASK) == CPU_ID_ARM810) { 104 int clock = arm8_clock_config(0, 0); 105 char *fclk; 106 aprint_normal("%s: ARM810 cp15=%02x", dv->dv_xname, clock); 107 aprint_normal(" clock:%s", (clock & 1) ? " dynamic" : ""); 108 aprint_normal("%s", (clock & 2) ? " sync" : ""); 109 switch ((clock >> 2) & 3) { 110 case 0: 111 fclk = "bus clock"; 112 break; 113 case 1: 114 fclk = "ref clock"; 115 break; 116 case 3: 117 fclk = "pll"; 118 break; 119 default: 120 fclk = "illegal"; 121 break; 122 } 123 aprint_normal(" fclk source=%s\n", fclk); 124 } 125 #endif 126 127 #ifdef ARMFPE 128 /* 129 * Ok now we test for an FPA 130 * At this point no floating point emulator has been installed. 131 * This means any FP instruction will cause undefined exception. 132 * We install a temporay coproc 1 handler which will modify 133 * undefined_test if it is called. 134 * We then try to read the FP status register. If undefined_test 135 * has been decremented then the instruction was not handled by 136 * an FPA so we know the FPA is missing. If undefined_test is 137 * still 1 then we know the instruction was handled by an FPA. 138 * We then remove our test handler and look at the 139 * FP status register for identification. 140 */ 141 142 /* 143 * Ok if ARMFPE is defined and the boot options request the 144 * ARM FPE then it will be installed as the FPE. 145 * This is just while I work on integrating the new FPE. 146 * It means the new FPE gets installed if compiled int (ARMFPE 147 * defined) and also gives me a on/off option when I boot in 148 * case the new FPE is causing panics. 149 */ 150 151 152 if (boot_args) 153 get_bootconf_option(boot_args, "armfpe", 154 BOOTOPT_TYPE_BOOLEAN, &usearmfpe); 155 if (usearmfpe) 156 initialise_arm_fpe(); 157 #endif 158 } 159 160 enum cpu_class { 161 CPU_CLASS_NONE, 162 CPU_CLASS_ARM2, 163 CPU_CLASS_ARM2AS, 164 CPU_CLASS_ARM3, 165 CPU_CLASS_ARM6, 166 CPU_CLASS_ARM7, 167 CPU_CLASS_ARM7TDMI, 168 CPU_CLASS_ARM8, 169 CPU_CLASS_ARM9TDMI, 170 CPU_CLASS_ARM9ES, 171 CPU_CLASS_SA1, 172 CPU_CLASS_XSCALE, 173 CPU_CLASS_ARM10E 174 }; 175 176 static const char * const generic_steppings[16] = { 177 "rev 0", "rev 1", "rev 2", "rev 3", 178 "rev 4", "rev 5", "rev 6", "rev 7", 179 "rev 8", "rev 9", "rev 10", "rev 11", 180 "rev 12", "rev 13", "rev 14", "rev 15", 181 }; 182 183 static const char * const sa110_steppings[16] = { 184 "rev 0", "step J", "step K", "step S", 185 "step T", "rev 5", "rev 6", "rev 7", 186 "rev 8", "rev 9", "rev 10", "rev 11", 187 "rev 12", "rev 13", "rev 14", "rev 15", 188 }; 189 190 static const char * const sa1100_steppings[16] = { 191 "rev 0", "step B", "step C", "rev 3", 192 "rev 4", "rev 5", "rev 6", "rev 7", 193 "step D", "step E", "rev 10" "step G", 194 "rev 12", "rev 13", "rev 14", "rev 15", 195 }; 196 197 static const char * const sa1110_steppings[16] = { 198 "step A-0", "rev 1", "rev 2", "rev 3", 199 "step B-0", "step B-1", "step B-2", "step B-3", 200 "step B-4", "step B-5", "rev 10", "rev 11", 201 "rev 12", "rev 13", "rev 14", "rev 15", 202 }; 203 204 static const char * const ixp12x0_steppings[16] = { 205 "(IXP1200 step A)", "(IXP1200 step B)", 206 "rev 2", "(IXP1200 step C)", 207 "(IXP1200 step D)", "(IXP1240/1250 step A)", 208 "(IXP1240 step B)", "(IXP1250 step B)", 209 "rev 8", "rev 9", "rev 10", "rev 11", 210 "rev 12", "rev 13", "rev 14", "rev 15", 211 }; 212 213 static const char * const xscale_steppings[16] = { 214 "step A-0", "step A-1", "step B-0", "step C-0", 215 "step D-0", "rev 5", "rev 6", "rev 7", 216 "rev 8", "rev 9", "rev 10", "rev 11", 217 "rev 12", "rev 13", "rev 14", "rev 15", 218 }; 219 220 static const char * const i80321_steppings[16] = { 221 "step A-0", "step B-0", "rev 2", "rev 3", 222 "rev 4", "rev 5", "rev 6", "rev 7", 223 "rev 8", "rev 9", "rev 10", "rev 11", 224 "rev 12", "rev 13", "rev 14", "rev 15", 225 }; 226 227 static const char * const pxa2x0_steppings[16] = { 228 "step A-0", "step A-1", "step B-0", "step B-1", 229 "step B-2", "step C-0", "rev 6", "rev 7", 230 "rev 8", "rev 9", "rev 10", "rev 11", 231 "rev 12", "rev 13", "rev 14", "rev 15", 232 }; 233 234 static const char * const ixp425_steppings[16] = { 235 "step 0", "rev 1", "rev 2", "rev 3", 236 "rev 4", "rev 5", "rev 6", "rev 7", 237 "rev 8", "rev 9", "rev 10", "rev 11", 238 "rev 12", "rev 13", "rev 14", "rev 15", 239 }; 240 241 struct cpuidtab { 242 u_int32_t cpuid; 243 enum cpu_class cpu_class; 244 const char *cpu_name; 245 const char * const *cpu_steppings; 246 }; 247 248 const struct cpuidtab cpuids[] = { 249 { CPU_ID_ARM2, CPU_CLASS_ARM2, "ARM2", 250 generic_steppings }, 251 { CPU_ID_ARM250, CPU_CLASS_ARM2AS, "ARM250", 252 generic_steppings }, 253 254 { CPU_ID_ARM3, CPU_CLASS_ARM3, "ARM3", 255 generic_steppings }, 256 257 { CPU_ID_ARM600, CPU_CLASS_ARM6, "ARM600", 258 generic_steppings }, 259 { CPU_ID_ARM610, CPU_CLASS_ARM6, "ARM610", 260 generic_steppings }, 261 { CPU_ID_ARM620, CPU_CLASS_ARM6, "ARM620", 262 generic_steppings }, 263 264 { CPU_ID_ARM700, CPU_CLASS_ARM7, "ARM700", 265 generic_steppings }, 266 { CPU_ID_ARM710, CPU_CLASS_ARM7, "ARM710", 267 generic_steppings }, 268 { CPU_ID_ARM7500, CPU_CLASS_ARM7, "ARM7500", 269 generic_steppings }, 270 { CPU_ID_ARM710A, CPU_CLASS_ARM7, "ARM710a", 271 generic_steppings }, 272 { CPU_ID_ARM7500FE, CPU_CLASS_ARM7, "ARM7500FE", 273 generic_steppings }, 274 { CPU_ID_ARM710T, CPU_CLASS_ARM7TDMI, "ARM710T", 275 generic_steppings }, 276 { CPU_ID_ARM720T, CPU_CLASS_ARM7TDMI, "ARM720T", 277 generic_steppings }, 278 { CPU_ID_ARM740T8K, CPU_CLASS_ARM7TDMI, "ARM740T (8 KB cache)", 279 generic_steppings }, 280 { CPU_ID_ARM740T4K, CPU_CLASS_ARM7TDMI, "ARM740T (4 KB cache)", 281 generic_steppings }, 282 283 { CPU_ID_ARM810, CPU_CLASS_ARM8, "ARM810", 284 generic_steppings }, 285 286 { CPU_ID_ARM920T, CPU_CLASS_ARM9TDMI, "ARM920T", 287 generic_steppings }, 288 { CPU_ID_ARM922T, CPU_CLASS_ARM9TDMI, "ARM922T", 289 generic_steppings }, 290 { CPU_ID_ARM940T, CPU_CLASS_ARM9TDMI, "ARM940T", 291 generic_steppings }, 292 { CPU_ID_ARM946ES, CPU_CLASS_ARM9ES, "ARM946E-S", 293 generic_steppings }, 294 { CPU_ID_ARM966ES, CPU_CLASS_ARM9ES, "ARM966E-S", 295 generic_steppings }, 296 { CPU_ID_ARM966ESR1, CPU_CLASS_ARM9ES, "ARM966E-S", 297 generic_steppings }, 298 299 { CPU_ID_SA110, CPU_CLASS_SA1, "SA-110", 300 sa110_steppings }, 301 { CPU_ID_SA1100, CPU_CLASS_SA1, "SA-1100", 302 sa1100_steppings }, 303 { CPU_ID_SA1110, CPU_CLASS_SA1, "SA-1110", 304 sa1110_steppings }, 305 306 { CPU_ID_IXP1200, CPU_CLASS_SA1, "IXP1200", 307 ixp12x0_steppings }, 308 309 { CPU_ID_80200, CPU_CLASS_XSCALE, "i80200", 310 xscale_steppings }, 311 312 { CPU_ID_80321_400, CPU_CLASS_XSCALE, "i80321 400MHz", 313 i80321_steppings }, 314 { CPU_ID_80321_600, CPU_CLASS_XSCALE, "i80321 600MHz", 315 i80321_steppings }, 316 { CPU_ID_80321_400_B0, CPU_CLASS_XSCALE, "i80321 400MHz", 317 i80321_steppings }, 318 { CPU_ID_80321_600_B0, CPU_CLASS_XSCALE, "i80321 600MHz", 319 i80321_steppings }, 320 321 { CPU_ID_PXA250A, CPU_CLASS_XSCALE, "PXA250", 322 pxa2x0_steppings }, 323 { CPU_ID_PXA210A, CPU_CLASS_XSCALE, "PXA210", 324 pxa2x0_steppings }, 325 { CPU_ID_PXA250B, CPU_CLASS_XSCALE, "PXA250", 326 pxa2x0_steppings }, 327 { CPU_ID_PXA210B, CPU_CLASS_XSCALE, "PXA210", 328 pxa2x0_steppings }, 329 { CPU_ID_PXA250C, CPU_CLASS_XSCALE, "PXA250", 330 pxa2x0_steppings }, 331 { CPU_ID_PXA210C, CPU_CLASS_XSCALE, "PXA210", 332 pxa2x0_steppings }, 333 334 { CPU_ID_IXP425_533, CPU_CLASS_XSCALE, "IXP425 533MHz", 335 ixp425_steppings }, 336 { CPU_ID_IXP425_400, CPU_CLASS_XSCALE, "IXP425 400MHz", 337 ixp425_steppings }, 338 { CPU_ID_IXP425_266, CPU_CLASS_XSCALE, "IXP425 266MHz", 339 ixp425_steppings }, 340 341 { CPU_ID_ARM1022ES, CPU_CLASS_ARM10E, "ARM1022ES", 342 generic_steppings }, 343 344 { 0, CPU_CLASS_NONE, NULL, NULL } 345 }; 346 347 struct cpu_classtab { 348 const char *class_name; 349 const char *class_option; 350 }; 351 352 const struct cpu_classtab cpu_classes[] = { 353 { "unknown", NULL }, /* CPU_CLASS_NONE */ 354 { "ARM2", "CPU_ARM2" }, /* CPU_CLASS_ARM2 */ 355 { "ARM2as", "CPU_ARM250" }, /* CPU_CLASS_ARM2AS */ 356 { "ARM3", "CPU_ARM3" }, /* CPU_CLASS_ARM3 */ 357 { "ARM6", "CPU_ARM6" }, /* CPU_CLASS_ARM6 */ 358 { "ARM7", "CPU_ARM7" }, /* CPU_CLASS_ARM7 */ 359 { "ARM7TDMI", "CPU_ARM7TDMI" }, /* CPU_CLASS_ARM7TDMI */ 360 { "ARM8", "CPU_ARM8" }, /* CPU_CLASS_ARM8 */ 361 { "ARM9TDMI", NULL }, /* CPU_CLASS_ARM9TDMI */ 362 { "ARM9E-S", NULL }, /* CPU_CLASS_ARM9ES */ 363 { "SA-1", "CPU_SA110" }, /* CPU_CLASS_SA1 */ 364 { "XScale", "CPU_XSCALE_..." }, /* CPU_CLASS_XSCALE */ 365 { "ARM10E", NULL }, /* CPU_CLASS_ARM10E */ 366 }; 367 368 /* 369 * Report the type of the specified arm processor. This uses the generic and 370 * arm specific information in the cpu structure to identify the processor. 371 * The remaining fields in the cpu structure are filled in appropriately. 372 */ 373 374 static const char * const wtnames[] = { 375 "write-through", 376 "write-back", 377 "write-back", 378 "**unknown 3**", 379 "**unknown 4**", 380 "write-back-locking", /* XXX XScale-specific? */ 381 "write-back-locking-A", 382 "write-back-locking-B", 383 "**unknown 8**", 384 "**unknown 9**", 385 "**unknown 10**", 386 "**unknown 11**", 387 "**unknown 12**", 388 "**unknown 13**", 389 "**unknown 14**", 390 "**unknown 15**", 391 }; 392 393 void 394 identify_arm_cpu(struct device *dv, struct cpu_info *ci) 395 { 396 u_int cpuid; 397 enum cpu_class cpu_class; 398 int i; 399 400 cpuid = ci->ci_arm_cpuid; 401 402 if (cpuid == 0) { 403 aprint_error("Processor failed probe - no CPU ID\n"); 404 return; 405 } 406 407 for (i = 0; cpuids[i].cpuid != 0; i++) 408 if (cpuids[i].cpuid == (cpuid & CPU_ID_CPU_MASK)) { 409 cpu_class = cpuids[i].cpu_class; 410 sprintf(cpu_model, "%s %s (%s core)", 411 cpuids[i].cpu_name, 412 cpuids[i].cpu_steppings[cpuid & 413 CPU_ID_REVISION_MASK], 414 cpu_classes[cpu_class].class_name); 415 break; 416 } 417 418 if (cpuids[i].cpuid == 0) 419 sprintf(cpu_model, "unknown CPU (ID = 0x%x)", cpuid); 420 421 aprint_naive(": %s\n", cpu_model); 422 aprint_normal(": %s\n", cpu_model); 423 424 aprint_normal("%s:", dv->dv_xname); 425 426 switch (cpu_class) { 427 case CPU_CLASS_ARM6: 428 case CPU_CLASS_ARM7: 429 case CPU_CLASS_ARM7TDMI: 430 case CPU_CLASS_ARM8: 431 if ((ci->ci_ctrl & CPU_CONTROL_IDC_ENABLE) == 0) 432 aprint_normal(" IDC disabled"); 433 else 434 aprint_normal(" IDC enabled"); 435 break; 436 case CPU_CLASS_ARM9TDMI: 437 case CPU_CLASS_SA1: 438 case CPU_CLASS_XSCALE: 439 if ((ci->ci_ctrl & CPU_CONTROL_DC_ENABLE) == 0) 440 aprint_normal(" DC disabled"); 441 else 442 aprint_normal(" DC enabled"); 443 if ((ci->ci_ctrl & CPU_CONTROL_IC_ENABLE) == 0) 444 aprint_normal(" IC disabled"); 445 else 446 aprint_normal(" IC enabled"); 447 break; 448 default: 449 break; 450 } 451 if ((ci->ci_ctrl & CPU_CONTROL_WBUF_ENABLE) == 0) 452 aprint_normal(" WB disabled"); 453 else 454 aprint_normal(" WB enabled"); 455 456 if (ci->ci_ctrl & CPU_CONTROL_LABT_ENABLE) 457 aprint_normal(" LABT"); 458 else 459 aprint_normal(" EABT"); 460 461 if (ci->ci_ctrl & CPU_CONTROL_BPRD_ENABLE) 462 aprint_normal(" branch prediction enabled"); 463 464 aprint_normal("\n"); 465 466 /* Print cache info. */ 467 if (arm_picache_line_size == 0 && arm_pdcache_line_size == 0) 468 goto skip_pcache; 469 470 if (arm_pcache_unified) { 471 aprint_normal("%s: %dKB/%dB %d-way %s unified cache\n", 472 dv->dv_xname, arm_pdcache_size / 1024, 473 arm_pdcache_line_size, arm_pdcache_ways, 474 wtnames[arm_pcache_type]); 475 } else { 476 aprint_normal("%s: %dKB/%dB %d-way Instruction cache\n", 477 dv->dv_xname, arm_picache_size / 1024, 478 arm_picache_line_size, arm_picache_ways); 479 aprint_normal("%s: %dKB/%dB %d-way %s Data cache\n", 480 dv->dv_xname, arm_pdcache_size / 1024, 481 arm_pdcache_line_size, arm_pdcache_ways, 482 wtnames[arm_pcache_type]); 483 } 484 485 skip_pcache: 486 487 switch (cpu_class) { 488 #ifdef CPU_ARM2 489 case CPU_CLASS_ARM2: 490 #endif 491 #ifdef CPU_ARM250 492 case CPU_CLASS_ARM2AS: 493 #endif 494 #ifdef CPU_ARM3 495 case CPU_CLASS_ARM3: 496 #endif 497 #ifdef CPU_ARM6 498 case CPU_CLASS_ARM6: 499 #endif 500 #ifdef CPU_ARM7 501 case CPU_CLASS_ARM7: 502 #endif 503 #ifdef CPU_ARM7TDMI 504 case CPU_CLASS_ARM7TDMI: 505 #endif 506 #ifdef CPU_ARM8 507 case CPU_CLASS_ARM8: 508 #endif 509 #ifdef CPU_ARM9 510 case CPU_CLASS_ARM9TDMI: 511 #endif 512 #if defined(CPU_SA110) || defined(CPU_SA1100) || \ 513 defined(CPU_SA1110) || defined(CPU_IXP12X0) 514 case CPU_CLASS_SA1: 515 #endif 516 #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 517 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) 518 case CPU_CLASS_XSCALE: 519 #endif 520 break; 521 default: 522 if (cpu_classes[cpu_class].class_option != NULL) 523 aprint_error("%s: %s does not fully support this CPU." 524 "\n", dv->dv_xname, ostype); 525 else { 526 aprint_error("%s: This kernel does not fully support " 527 "this CPU.\n", dv->dv_xname); 528 aprint_normal("%s: Recompile with \"options %s\" to " 529 "correct this.\n", dv->dv_xname, 530 cpu_classes[cpu_class].class_option); 531 } 532 break; 533 } 534 535 } 536 #ifdef MULTIPROCESSOR 537 int 538 cpu_alloc_idlepcb(struct cpu_info *ci) 539 { 540 vaddr_t uaddr; 541 struct pcb *pcb; 542 struct trapframe *tf; 543 int error; 544 545 /* 546 * Generate a kernel stack and PCB (in essence, a u-area) for the 547 * new CPU. 548 */ 549 if (uvm_uarea_alloc(&uaddr)) { 550 error = uvm_fault_wire(kernel_map, uaddr, uaddr + USPACE, 551 VM_FAULT_WIRE, VM_PROT_READ | VM_PROT_WRITE); 552 if (error) 553 return error; 554 } 555 ci->ci_idlepcb = pcb = (struct pcb *)uaddr; 556 557 /* 558 * This code is largely derived from cpu_fork(), with which it 559 * should perhaps be shared. 560 */ 561 562 /* Copy the pcb */ 563 *pcb = proc0.p_addr->u_pcb; 564 565 /* Set up the undefined stack for the process. */ 566 pcb->pcb_un.un_32.pcb32_und_sp = uaddr + USPACE_UNDEF_STACK_TOP; 567 pcb->pcb_un.un_32.pcb32_sp = uaddr + USPACE_SVC_STACK_TOP; 568 569 #ifdef STACKCHECKS 570 /* Fill the undefined stack with a known pattern */ 571 memset(((u_char *)uaddr) + USPACE_UNDEF_STACK_BOTTOM, 0xdd, 572 (USPACE_UNDEF_STACK_TOP - USPACE_UNDEF_STACK_BOTTOM)); 573 /* Fill the kernel stack with a known pattern */ 574 memset(((u_char *)uaddr) + USPACE_SVC_STACK_BOTTOM, 0xdd, 575 (USPACE_SVC_STACK_TOP - USPACE_SVC_STACK_BOTTOM)); 576 #endif /* STACKCHECKS */ 577 578 pcb->pcb_tf = tf = 579 (struct trapframe *)pcb->pcb_un.un_32.pcb32_sp - 1; 580 *tf = *proc0.p_addr->u_pcb.pcb_tf; 581 return 0; 582 } 583 #endif /* MULTIPROCESSOR */ 584 585 /* End of cpu.c */ 586
Indexes created Fri Sep 26 20:09:58 GMT 2025