cpu.c revision 1.59
1 /* $NetBSD: cpu.c,v 1.59 2005/07/04 00:42:37 bsh Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Mark Brinicombe. 5 * Copyright (c) 1995 Brini. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Brini. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * cpu.c 38 * 39 * Probing and configuration for the master CPU 40 * 41 * Created : 10/10/95 42 */ 43 44 #include "opt_armfpe.h" 45 #include "opt_multiprocessor.h" 46 47 #include <sys/param.h> 48 49 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.59 2005/07/04 00:42:37 bsh Exp $"); 50 51 #include <sys/systm.h> 52 #include <sys/malloc.h> 53 #include <sys/device.h> 54 #include <sys/proc.h> 55 #include <sys/conf.h> 56 #include <uvm/uvm_extern.h> 57 #include <machine/cpu.h> 58 59 #include <arm/cpuconf.h> 60 #include <arm/undefined.h> 61 62 #ifdef ARMFPE 63 #include <machine/bootconfig.h> /* For boot args */ 64 #include <arm/fpe-arm/armfpe.h> 65 #endif 66 67 char cpu_model[256]; 68 69 /* Prototypes */ 70 void identify_arm_cpu(struct device *dv, struct cpu_info *); 71 72 /* 73 * Identify the master (boot) CPU 74 */ 75 76 void 77 cpu_attach(struct device *dv) 78 { 79 int usearmfpe; 80 81 usearmfpe = 1; /* when compiled in, its enabled by default */ 82 83 curcpu()->ci_dev = dv; 84 85 evcnt_attach_dynamic(&curcpu()->ci_arm700bugcount, EVCNT_TYPE_MISC, 86 NULL, dv->dv_xname, "arm700swibug"); 87 88 /* Get the CPU ID from coprocessor 15 */ 89 90 curcpu()->ci_arm_cpuid = cpu_id(); 91 curcpu()->ci_arm_cputype = curcpu()->ci_arm_cpuid & CPU_ID_CPU_MASK; 92 curcpu()->ci_arm_cpurev = 93 curcpu()->ci_arm_cpuid & CPU_ID_REVISION_MASK; 94 95 identify_arm_cpu(dv, curcpu()); 96 97 if (curcpu()->ci_arm_cputype == CPU_ID_SA110 && 98 curcpu()->ci_arm_cpurev < 3) { 99 aprint_normal("%s: SA-110 with bugged STM^ instruction\n", 100 dv->dv_xname); 101 } 102 103 #ifdef CPU_ARM8 104 if ((curcpu()->ci_arm_cpuid & CPU_ID_CPU_MASK) == CPU_ID_ARM810) { 105 int clock = arm8_clock_config(0, 0); 106 char *fclk; 107 aprint_normal("%s: ARM810 cp15=%02x", dv->dv_xname, clock); 108 aprint_normal(" clock:%s", (clock & 1) ? " dynamic" : ""); 109 aprint_normal("%s", (clock & 2) ? " sync" : ""); 110 switch ((clock >> 2) & 3) { 111 case 0: 112 fclk = "bus clock"; 113 break; 114 case 1: 115 fclk = "ref clock"; 116 break; 117 case 3: 118 fclk = "pll"; 119 break; 120 default: 121 fclk = "illegal"; 122 break; 123 } 124 aprint_normal(" fclk source=%s\n", fclk); 125 } 126 #endif 127 128 #ifdef ARMFPE 129 /* 130 * Ok now we test for an FPA 131 * At this point no floating point emulator has been installed. 132 * This means any FP instruction will cause undefined exception. 133 * We install a temporay coproc 1 handler which will modify 134 * undefined_test if it is called. 135 * We then try to read the FP status register. If undefined_test 136 * has been decremented then the instruction was not handled by 137 * an FPA so we know the FPA is missing. If undefined_test is 138 * still 1 then we know the instruction was handled by an FPA. 139 * We then remove our test handler and look at the 140 * FP status register for identification. 141 */ 142 143 /* 144 * Ok if ARMFPE is defined and the boot options request the 145 * ARM FPE then it will be installed as the FPE. 146 * This is just while I work on integrating the new FPE. 147 * It means the new FPE gets installed if compiled int (ARMFPE 148 * defined) and also gives me a on/off option when I boot in 149 * case the new FPE is causing panics. 150 */ 151 152 153 if (boot_args) 154 get_bootconf_option(boot_args, "armfpe", 155 BOOTOPT_TYPE_BOOLEAN, &usearmfpe); 156 if (usearmfpe) 157 initialise_arm_fpe(); 158 #endif 159 } 160 161 enum cpu_class { 162 CPU_CLASS_NONE, 163 CPU_CLASS_ARM2, 164 CPU_CLASS_ARM2AS, 165 CPU_CLASS_ARM3, 166 CPU_CLASS_ARM6, 167 CPU_CLASS_ARM7, 168 CPU_CLASS_ARM7TDMI, 169 CPU_CLASS_ARM8, 170 CPU_CLASS_ARM9TDMI, 171 CPU_CLASS_ARM9ES, 172 CPU_CLASS_ARM10E, 173 CPU_CLASS_ARM10EJ, 174 CPU_CLASS_SA1, 175 CPU_CLASS_XSCALE, 176 CPU_CLASS_ARM11J 177 }; 178 179 static const char * const generic_steppings[16] = { 180 "rev 0", "rev 1", "rev 2", "rev 3", 181 "rev 4", "rev 5", "rev 6", "rev 7", 182 "rev 8", "rev 9", "rev 10", "rev 11", 183 "rev 12", "rev 13", "rev 14", "rev 15", 184 }; 185 186 static const char * const sa110_steppings[16] = { 187 "rev 0", "step J", "step K", "step S", 188 "step T", "rev 5", "rev 6", "rev 7", 189 "rev 8", "rev 9", "rev 10", "rev 11", 190 "rev 12", "rev 13", "rev 14", "rev 15", 191 }; 192 193 static const char * const sa1100_steppings[16] = { 194 "rev 0", "step B", "step C", "rev 3", 195 "rev 4", "rev 5", "rev 6", "rev 7", 196 "step D", "step E", "rev 10" "step G", 197 "rev 12", "rev 13", "rev 14", "rev 15", 198 }; 199 200 static const char * const sa1110_steppings[16] = { 201 "step A-0", "rev 1", "rev 2", "rev 3", 202 "step B-0", "step B-1", "step B-2", "step B-3", 203 "step B-4", "step B-5", "rev 10", "rev 11", 204 "rev 12", "rev 13", "rev 14", "rev 15", 205 }; 206 207 static const char * const ixp12x0_steppings[16] = { 208 "(IXP1200 step A)", "(IXP1200 step B)", 209 "rev 2", "(IXP1200 step C)", 210 "(IXP1200 step D)", "(IXP1240/1250 step A)", 211 "(IXP1240 step B)", "(IXP1250 step B)", 212 "rev 8", "rev 9", "rev 10", "rev 11", 213 "rev 12", "rev 13", "rev 14", "rev 15", 214 }; 215 216 static const char * const xscale_steppings[16] = { 217 "step A-0", "step A-1", "step B-0", "step C-0", 218 "step D-0", "rev 5", "rev 6", "rev 7", 219 "rev 8", "rev 9", "rev 10", "rev 11", 220 "rev 12", "rev 13", "rev 14", "rev 15", 221 }; 222 223 static const char * const i80321_steppings[16] = { 224 "step A-0", "step B-0", "rev 2", "rev 3", 225 "rev 4", "rev 5", "rev 6", "rev 7", 226 "rev 8", "rev 9", "rev 10", "rev 11", 227 "rev 12", "rev 13", "rev 14", "rev 15", 228 }; 229 230 /* Steppings for PXA2[15]0 */ 231 static const char * const pxa2x0_steppings[16] = { 232 "step A-0", "step A-1", "step B-0", "step B-1", 233 "step B-2", "step C-0", "rev 6", "rev 7", 234 "rev 8", "rev 9", "rev 10", "rev 11", 235 "rev 12", "rev 13", "rev 14", "rev 15", 236 }; 237 238 /* Steppings for PXA255/26x. 239 * rev 5: PXA26x B0, rev 6: PXA255 A0 240 */ 241 static const char * const pxa255_steppings[16] = { 242 "rev 0", "rev 1", "rev 2", "step A-0", 243 "rev 4", "step B-0", "step A-0", "rev 7", 244 "rev 8", "rev 9", "rev 10", "rev 11", 245 "rev 12", "rev 13", "rev 14", "rev 15", 246 }; 247 248 /* Stepping for PXA27x */ 249 static const char * const pxa27x_steppings[16] = { 250 "step A-0", "step A-1", "step B-0", "step B-1", 251 "step C-0", "rev 5", "rev 6", "rev 7", 252 "rev 8", "rev 9", "rev 10", "rev 11", 253 "rev 12", "rev 13", "rev 14", "rev 15", 254 }; 255 256 static const char * const ixp425_steppings[16] = { 257 "step 0", "rev 1", "rev 2", "rev 3", 258 "rev 4", "rev 5", "rev 6", "rev 7", 259 "rev 8", "rev 9", "rev 10", "rev 11", 260 "rev 12", "rev 13", "rev 14", "rev 15", 261 }; 262 263 struct cpuidtab { 264 u_int32_t cpuid; 265 enum cpu_class cpu_class; 266 const char *cpu_name; 267 const char * const *cpu_steppings; 268 }; 269 270 const struct cpuidtab cpuids[] = { 271 { CPU_ID_ARM2, CPU_CLASS_ARM2, "ARM2", 272 generic_steppings }, 273 { CPU_ID_ARM250, CPU_CLASS_ARM2AS, "ARM250", 274 generic_steppings }, 275 276 { CPU_ID_ARM3, CPU_CLASS_ARM3, "ARM3", 277 generic_steppings }, 278 279 { CPU_ID_ARM600, CPU_CLASS_ARM6, "ARM600", 280 generic_steppings }, 281 { CPU_ID_ARM610, CPU_CLASS_ARM6, "ARM610", 282 generic_steppings }, 283 { CPU_ID_ARM620, CPU_CLASS_ARM6, "ARM620", 284 generic_steppings }, 285 286 { CPU_ID_ARM700, CPU_CLASS_ARM7, "ARM700", 287 generic_steppings }, 288 { CPU_ID_ARM710, CPU_CLASS_ARM7, "ARM710", 289 generic_steppings }, 290 { CPU_ID_ARM7500, CPU_CLASS_ARM7, "ARM7500", 291 generic_steppings }, 292 { CPU_ID_ARM710A, CPU_CLASS_ARM7, "ARM710a", 293 generic_steppings }, 294 { CPU_ID_ARM7500FE, CPU_CLASS_ARM7, "ARM7500FE", 295 generic_steppings }, 296 { CPU_ID_ARM710T, CPU_CLASS_ARM7TDMI, "ARM710T", 297 generic_steppings }, 298 { CPU_ID_ARM720T, CPU_CLASS_ARM7TDMI, "ARM720T", 299 generic_steppings }, 300 { CPU_ID_ARM740T8K, CPU_CLASS_ARM7TDMI, "ARM740T (8 KB cache)", 301 generic_steppings }, 302 { CPU_ID_ARM740T4K, CPU_CLASS_ARM7TDMI, "ARM740T (4 KB cache)", 303 generic_steppings }, 304 305 { CPU_ID_ARM810, CPU_CLASS_ARM8, "ARM810", 306 generic_steppings }, 307 308 { CPU_ID_ARM920T, CPU_CLASS_ARM9TDMI, "ARM920T", 309 generic_steppings }, 310 { CPU_ID_ARM922T, CPU_CLASS_ARM9TDMI, "ARM922T", 311 generic_steppings }, 312 { CPU_ID_ARM940T, CPU_CLASS_ARM9TDMI, "ARM940T", 313 generic_steppings }, 314 { CPU_ID_ARM946ES, CPU_CLASS_ARM9ES, "ARM946E-S", 315 generic_steppings }, 316 { CPU_ID_ARM966ES, CPU_CLASS_ARM9ES, "ARM966E-S", 317 generic_steppings }, 318 { CPU_ID_ARM966ESR1, CPU_CLASS_ARM9ES, "ARM966E-S", 319 generic_steppings }, 320 { CPU_ID_TI925T, CPU_CLASS_ARM9TDMI, "TI ARM925T", 321 generic_steppings }, 322 323 { CPU_ID_ARM1020E, CPU_CLASS_ARM10E, "ARM1020E", 324 generic_steppings }, 325 { CPU_ID_ARM1022ES, CPU_CLASS_ARM10E, "ARM1022E-S", 326 generic_steppings }, 327 { CPU_ID_ARM1026EJS, CPU_CLASS_ARM10EJ, "ARM1026EJ-S", 328 generic_steppings }, 329 330 { CPU_ID_SA110, CPU_CLASS_SA1, "SA-110", 331 sa110_steppings }, 332 { CPU_ID_SA1100, CPU_CLASS_SA1, "SA-1100", 333 sa1100_steppings }, 334 { CPU_ID_SA1110, CPU_CLASS_SA1, "SA-1110", 335 sa1110_steppings }, 336 337 { CPU_ID_IXP1200, CPU_CLASS_SA1, "IXP1200", 338 ixp12x0_steppings }, 339 340 { CPU_ID_80200, CPU_CLASS_XSCALE, "i80200", 341 xscale_steppings }, 342 343 { CPU_ID_80321_400, CPU_CLASS_XSCALE, "i80321 400MHz", 344 i80321_steppings }, 345 { CPU_ID_80321_600, CPU_CLASS_XSCALE, "i80321 600MHz", 346 i80321_steppings }, 347 { CPU_ID_80321_400_B0, CPU_CLASS_XSCALE, "i80321 400MHz", 348 i80321_steppings }, 349 { CPU_ID_80321_600_B0, CPU_CLASS_XSCALE, "i80321 600MHz", 350 i80321_steppings }, 351 352 { CPU_ID_PXA27X, CPU_CLASS_XSCALE, "PXA27x", 353 pxa27x_steppings }, 354 { CPU_ID_PXA250A, CPU_CLASS_XSCALE, "PXA250", 355 pxa2x0_steppings }, 356 { CPU_ID_PXA210A, CPU_CLASS_XSCALE, "PXA210", 357 pxa2x0_steppings }, 358 { CPU_ID_PXA250B, CPU_CLASS_XSCALE, "PXA250", 359 pxa2x0_steppings }, 360 { CPU_ID_PXA210B, CPU_CLASS_XSCALE, "PXA210", 361 pxa2x0_steppings }, 362 { CPU_ID_PXA250C, CPU_CLASS_XSCALE, "PXA255/26x", 363 pxa255_steppings }, 364 { CPU_ID_PXA210C, CPU_CLASS_XSCALE, "PXA210", 365 pxa2x0_steppings }, 366 367 { CPU_ID_IXP425_533, CPU_CLASS_XSCALE, "IXP425 533MHz", 368 ixp425_steppings }, 369 { CPU_ID_IXP425_400, CPU_CLASS_XSCALE, "IXP425 400MHz", 370 ixp425_steppings }, 371 { CPU_ID_IXP425_266, CPU_CLASS_XSCALE, "IXP425 266MHz", 372 ixp425_steppings }, 373 374 { CPU_ID_ARM1136JS, CPU_CLASS_ARM11J, "ARM1136J-S", 375 generic_steppings }, 376 { CPU_ID_ARM1136JSR1, CPU_CLASS_ARM11J, "ARM1136J-S R1", 377 generic_steppings }, 378 379 { 0, CPU_CLASS_NONE, NULL, NULL } 380 }; 381 382 struct cpu_classtab { 383 const char *class_name; 384 const char *class_option; 385 }; 386 387 const struct cpu_classtab cpu_classes[] = { 388 { "unknown", NULL }, /* CPU_CLASS_NONE */ 389 { "ARM2", "CPU_ARM2" }, /* CPU_CLASS_ARM2 */ 390 { "ARM2as", "CPU_ARM250" }, /* CPU_CLASS_ARM2AS */ 391 { "ARM3", "CPU_ARM3" }, /* CPU_CLASS_ARM3 */ 392 { "ARM6", "CPU_ARM6" }, /* CPU_CLASS_ARM6 */ 393 { "ARM7", "CPU_ARM7" }, /* CPU_CLASS_ARM7 */ 394 { "ARM7TDMI", "CPU_ARM7TDMI" }, /* CPU_CLASS_ARM7TDMI */ 395 { "ARM8", "CPU_ARM8" }, /* CPU_CLASS_ARM8 */ 396 { "ARM9TDMI", NULL }, /* CPU_CLASS_ARM9TDMI */ 397 { "ARM9E-S", NULL }, /* CPU_CLASS_ARM9ES */ 398 { "ARM10E", "CPU_ARM10" }, /* CPU_CLASS_ARM10E */ 399 { "ARM10EJ", "CPU_ARM10" }, /* CPU_CLASS_ARM10EJ */ 400 { "SA-1", "CPU_SA110" }, /* CPU_CLASS_SA1 */ 401 { "XScale", "CPU_XSCALE_..." }, /* CPU_CLASS_XSCALE */ 402 { "ARM11J", "CPU_ARM11" }, /* CPU_CLASS_ARM11J */ 403 }; 404 405 /* 406 * Report the type of the specified arm processor. This uses the generic and 407 * arm specific information in the CPU structure to identify the processor. 408 * The remaining fields in the CPU structure are filled in appropriately. 409 */ 410 411 static const char * const wtnames[] = { 412 "write-through", 413 "write-back", 414 "write-back", 415 "**unknown 3**", 416 "**unknown 4**", 417 "write-back-locking", /* XXX XScale-specific? */ 418 "write-back-locking-A", 419 "write-back-locking-B", 420 "**unknown 8**", 421 "**unknown 9**", 422 "**unknown 10**", 423 "**unknown 11**", 424 "**unknown 12**", 425 "**unknown 13**", 426 "write-back-locking-C", 427 "**unknown 15**", 428 }; 429 430 void 431 identify_arm_cpu(struct device *dv, struct cpu_info *ci) 432 { 433 u_int cpuid; 434 enum cpu_class cpu_class = CPU_CLASS_NONE; 435 int i; 436 437 cpuid = ci->ci_arm_cpuid; 438 439 if (cpuid == 0) { 440 aprint_error("Processor failed probe - no CPU ID\n"); 441 return; 442 } 443 444 for (i = 0; cpuids[i].cpuid != 0; i++) 445 if (cpuids[i].cpuid == (cpuid & CPU_ID_CPU_MASK)) { 446 cpu_class = cpuids[i].cpu_class; 447 sprintf(cpu_model, "%s %s (%s core)", 448 cpuids[i].cpu_name, 449 cpuids[i].cpu_steppings[cpuid & 450 CPU_ID_REVISION_MASK], 451 cpu_classes[cpu_class].class_name); 452 break; 453 } 454 455 if (cpuids[i].cpuid == 0) 456 sprintf(cpu_model, "unknown CPU (ID = 0x%x)", cpuid); 457 458 aprint_naive(": %s\n", cpu_model); 459 aprint_normal(": %s\n", cpu_model); 460 461 aprint_normal("%s:", dv->dv_xname); 462 463 switch (cpu_class) { 464 case CPU_CLASS_ARM6: 465 case CPU_CLASS_ARM7: 466 case CPU_CLASS_ARM7TDMI: 467 case CPU_CLASS_ARM8: 468 if ((ci->ci_ctrl & CPU_CONTROL_IDC_ENABLE) == 0) 469 aprint_normal(" IDC disabled"); 470 else 471 aprint_normal(" IDC enabled"); 472 break; 473 case CPU_CLASS_ARM9TDMI: 474 case CPU_CLASS_ARM10E: 475 case CPU_CLASS_ARM10EJ: 476 case CPU_CLASS_SA1: 477 case CPU_CLASS_XSCALE: 478 case CPU_CLASS_ARM11J: 479 if ((ci->ci_ctrl & CPU_CONTROL_DC_ENABLE) == 0) 480 aprint_normal(" DC disabled"); 481 else 482 aprint_normal(" DC enabled"); 483 if ((ci->ci_ctrl & CPU_CONTROL_IC_ENABLE) == 0) 484 aprint_normal(" IC disabled"); 485 else 486 aprint_normal(" IC enabled"); 487 break; 488 default: 489 break; 490 } 491 if ((ci->ci_ctrl & CPU_CONTROL_WBUF_ENABLE) == 0) 492 aprint_normal(" WB disabled"); 493 else 494 aprint_normal(" WB enabled"); 495 496 if (ci->ci_ctrl & CPU_CONTROL_LABT_ENABLE) 497 aprint_normal(" LABT"); 498 else 499 aprint_normal(" EABT"); 500 501 if (ci->ci_ctrl & CPU_CONTROL_BPRD_ENABLE) 502 aprint_normal(" branch prediction enabled"); 503 504 aprint_normal("\n"); 505 506 /* Print cache info. */ 507 if (arm_picache_line_size == 0 && arm_pdcache_line_size == 0) 508 goto skip_pcache; 509 510 if (arm_pcache_unified) { 511 aprint_normal("%s: %dKB/%dB %d-way %s unified cache\n", 512 dv->dv_xname, arm_pdcache_size / 1024, 513 arm_pdcache_line_size, arm_pdcache_ways, 514 wtnames[arm_pcache_type]); 515 } else { 516 aprint_normal("%s: %dKB/%dB %d-way Instruction cache\n", 517 dv->dv_xname, arm_picache_size / 1024, 518 arm_picache_line_size, arm_picache_ways); 519 aprint_normal("%s: %dKB/%dB %d-way %s Data cache\n", 520 dv->dv_xname, arm_pdcache_size / 1024, 521 arm_pdcache_line_size, arm_pdcache_ways, 522 wtnames[arm_pcache_type]); 523 } 524 525 skip_pcache: 526 527 switch (cpu_class) { 528 #ifdef CPU_ARM2 529 case CPU_CLASS_ARM2: 530 #endif 531 #ifdef CPU_ARM250 532 case CPU_CLASS_ARM2AS: 533 #endif 534 #ifdef CPU_ARM3 535 case CPU_CLASS_ARM3: 536 #endif 537 #ifdef CPU_ARM6 538 case CPU_CLASS_ARM6: 539 #endif 540 #ifdef CPU_ARM7 541 case CPU_CLASS_ARM7: 542 #endif 543 #ifdef CPU_ARM7TDMI 544 case CPU_CLASS_ARM7TDMI: 545 #endif 546 #ifdef CPU_ARM8 547 case CPU_CLASS_ARM8: 548 #endif 549 #ifdef CPU_ARM9 550 case CPU_CLASS_ARM9TDMI: 551 #endif 552 #ifdef CPU_ARM10 553 case CPU_CLASS_ARM10E: 554 case CPU_CLASS_ARM10EJ: 555 #endif 556 #if defined(CPU_SA110) || defined(CPU_SA1100) || \ 557 defined(CPU_SA1110) || defined(CPU_IXP12X0) 558 case CPU_CLASS_SA1: 559 #endif 560 #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 561 defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425) 562 case CPU_CLASS_XSCALE: 563 #endif 564 #ifdef CPU_ARM11 565 case CPU_CLASS_ARM11J: 566 #endif 567 break; 568 default: 569 if (cpu_classes[cpu_class].class_option != NULL) 570 aprint_error("%s: %s does not fully support this CPU." 571 "\n", dv->dv_xname, ostype); 572 else { 573 aprint_error("%s: This kernel does not fully support " 574 "this CPU.\n", dv->dv_xname); 575 aprint_normal("%s: Recompile with \"options %s\" to " 576 "correct this.\n", dv->dv_xname, 577 cpu_classes[cpu_class].class_option); 578 } 579 break; 580 } 581 582 } 583 #ifdef MULTIPROCESSOR 584 int 585 cpu_alloc_idlepcb(struct cpu_info *ci) 586 { 587 vaddr_t uaddr; 588 struct pcb *pcb; 589 struct trapframe *tf; 590 int error; 591 592 /* 593 * Generate a kernel stack and PCB (in essence, a u-area) for the 594 * new CPU. 595 */ 596 if (uvm_uarea_alloc(&uaddr)) { 597 error = uvm_fault_wire(kernel_map, uaddr, uaddr + USPACE, 598 VM_FAULT_WIRE, VM_PROT_READ | VM_PROT_WRITE); 599 if (error) 600 return error; 601 } 602 ci->ci_idlepcb = pcb = (struct pcb *)uaddr; 603 604 /* 605 * This code is largely derived from cpu_fork(), with which it 606 * should perhaps be shared. 607 */ 608 609 /* Copy the pcb */ 610 *pcb = proc0.p_addr->u_pcb; 611 612 /* Set up the undefined stack for the process. */ 613 pcb->pcb_un.un_32.pcb32_und_sp = uaddr + USPACE_UNDEF_STACK_TOP; 614 pcb->pcb_un.un_32.pcb32_sp = uaddr + USPACE_SVC_STACK_TOP; 615 616 #ifdef STACKCHECKS 617 /* Fill the undefined stack with a known pattern */ 618 memset(((u_char *)uaddr) + USPACE_UNDEF_STACK_BOTTOM, 0xdd, 619 (USPACE_UNDEF_STACK_TOP - USPACE_UNDEF_STACK_BOTTOM)); 620 /* Fill the kernel stack with a known pattern */ 621 memset(((u_char *)uaddr) + USPACE_SVC_STACK_BOTTOM, 0xdd, 622 (USPACE_SVC_STACK_TOP - USPACE_SVC_STACK_BOTTOM)); 623 #endif /* STACKCHECKS */ 624 625 pcb->pcb_tf = tf = 626 (struct trapframe *)pcb->pcb_un.un_32.pcb32_sp - 1; 627 *tf = *proc0.p_addr->u_pcb.pcb_tf; 628 return 0; 629 } 630 #endif /* MULTIPROCESSOR */ 631 632 /* End of cpu.c */ 633
Indexes created Wed Oct 22 13:09:56 GMT 2025