cpu.c revision 1.62
1 /* $NetBSD: cpu.c,v 1.62 2006/03/15 18:31:11 drochner Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Mark Brinicombe. 5 * Copyright (c) 1995 Brini. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Brini. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * cpu.c 38 * 39 * Probing and configuration for the master CPU 40 * 41 * Created : 10/10/95 42 */ 43 44 #include "opt_armfpe.h" 45 #include "opt_multiprocessor.h" 46 47 #include <sys/param.h> 48 49 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.62 2006/03/15 18:31:11 drochner Exp $"); 50 51 #include <sys/systm.h> 52 #include <sys/malloc.h> 53 #include <sys/device.h> 54 #include <sys/proc.h> 55 #include <sys/conf.h> 56 #include <uvm/uvm_extern.h> 57 #include <machine/cpu.h> 58 59 #include <arm/cpuconf.h> 60 #include <arm/undefined.h> 61 62 #ifdef ARMFPE 63 #include <machine/bootconfig.h> /* For boot args */ 64 #include <arm/fpe-arm/armfpe.h> 65 #endif 66 67 char cpu_model[256]; 68 69 /* Prototypes */ 70 void identify_arm_cpu(struct device *dv, struct cpu_info *); 71 72 /* 73 * Identify the master (boot) CPU 74 */ 75 76 void 77 cpu_attach(struct device *dv) 78 { 79 int usearmfpe; 80 81 usearmfpe = 1; /* when compiled in, its enabled by default */ 82 83 curcpu()->ci_dev = dv; 84 85 evcnt_attach_dynamic(&curcpu()->ci_arm700bugcount, EVCNT_TYPE_MISC, 86 NULL, dv->dv_xname, "arm700swibug"); 87 88 /* Get the CPU ID from coprocessor 15 */ 89 90 curcpu()->ci_arm_cpuid = cpu_id(); 91 curcpu()->ci_arm_cputype = curcpu()->ci_arm_cpuid & CPU_ID_CPU_MASK; 92 curcpu()->ci_arm_cpurev = 93 curcpu()->ci_arm_cpuid & CPU_ID_REVISION_MASK; 94 95 identify_arm_cpu(dv, curcpu()); 96 97 if (curcpu()->ci_arm_cputype == CPU_ID_SA110 && 98 curcpu()->ci_arm_cpurev < 3) { 99 aprint_normal("%s: SA-110 with bugged STM^ instruction\n", 100 dv->dv_xname); 101 } 102 103 #ifdef CPU_ARM8 104 if ((curcpu()->ci_arm_cpuid & CPU_ID_CPU_MASK) == CPU_ID_ARM810) { 105 int clock = arm8_clock_config(0, 0); 106 char *fclk; 107 aprint_normal("%s: ARM810 cp15=%02x", dv->dv_xname, clock); 108 aprint_normal(" clock:%s", (clock & 1) ? " dynamic" : ""); 109 aprint_normal("%s", (clock & 2) ? " sync" : ""); 110 switch ((clock >> 2) & 3) { 111 case 0: 112 fclk = "bus clock"; 113 break; 114 case 1: 115 fclk = "ref clock"; 116 break; 117 case 3: 118 fclk = "pll"; 119 break; 120 default: 121 fclk = "illegal"; 122 break; 123 } 124 aprint_normal(" fclk source=%s\n", fclk); 125 } 126 #endif 127 128 #ifdef ARMFPE 129 /* 130 * Ok now we test for an FPA 131 * At this point no floating point emulator has been installed. 132 * This means any FP instruction will cause undefined exception. 133 * We install a temporay coproc 1 handler which will modify 134 * undefined_test if it is called. 135 * We then try to read the FP status register. If undefined_test 136 * has been decremented then the instruction was not handled by 137 * an FPA so we know the FPA is missing. If undefined_test is 138 * still 1 then we know the instruction was handled by an FPA. 139 * We then remove our test handler and look at the 140 * FP status register for identification. 141 */ 142 143 /* 144 * Ok if ARMFPE is defined and the boot options request the 145 * ARM FPE then it will be installed as the FPE. 146 * This is just while I work on integrating the new FPE. 147 * It means the new FPE gets installed if compiled int (ARMFPE 148 * defined) and also gives me a on/off option when I boot in 149 * case the new FPE is causing panics. 150 */ 151 152 153 if (boot_args) 154 get_bootconf_option(boot_args, "armfpe", 155 BOOTOPT_TYPE_BOOLEAN, &usearmfpe); 156 if (usearmfpe) 157 initialise_arm_fpe(); 158 #endif 159 } 160 161 enum cpu_class { 162 CPU_CLASS_NONE, 163 CPU_CLASS_ARM2, 164 CPU_CLASS_ARM2AS, 165 CPU_CLASS_ARM3, 166 CPU_CLASS_ARM6, 167 CPU_CLASS_ARM7, 168 CPU_CLASS_ARM7TDMI, 169 CPU_CLASS_ARM8, 170 CPU_CLASS_ARM9TDMI, 171 CPU_CLASS_ARM9ES, 172 CPU_CLASS_ARM10E, 173 CPU_CLASS_ARM10EJ, 174 CPU_CLASS_SA1, 175 CPU_CLASS_XSCALE, 176 CPU_CLASS_ARM11J 177 }; 178 179 static const char * const generic_steppings[16] = { 180 "rev 0", "rev 1", "rev 2", "rev 3", 181 "rev 4", "rev 5", "rev 6", "rev 7", 182 "rev 8", "rev 9", "rev 10", "rev 11", 183 "rev 12", "rev 13", "rev 14", "rev 15", 184 }; 185 186 static const char * const sa110_steppings[16] = { 187 "rev 0", "step J", "step K", "step S", 188 "step T", "rev 5", "rev 6", "rev 7", 189 "rev 8", "rev 9", "rev 10", "rev 11", 190 "rev 12", "rev 13", "rev 14", "rev 15", 191 }; 192 193 static const char * const sa1100_steppings[16] = { 194 "rev 0", "step B", "step C", "rev 3", 195 "rev 4", "rev 5", "rev 6", "rev 7", 196 "step D", "step E", "rev 10" "step G", 197 "rev 12", "rev 13", "rev 14", "rev 15", 198 }; 199 200 static const char * const sa1110_steppings[16] = { 201 "step A-0", "rev 1", "rev 2", "rev 3", 202 "step B-0", "step B-1", "step B-2", "step B-3", 203 "step B-4", "step B-5", "rev 10", "rev 11", 204 "rev 12", "rev 13", "rev 14", "rev 15", 205 }; 206 207 static const char * const ixp12x0_steppings[16] = { 208 "(IXP1200 step A)", "(IXP1200 step B)", 209 "rev 2", "(IXP1200 step C)", 210 "(IXP1200 step D)", "(IXP1240/1250 step A)", 211 "(IXP1240 step B)", "(IXP1250 step B)", 212 "rev 8", "rev 9", "rev 10", "rev 11", 213 "rev 12", "rev 13", "rev 14", "rev 15", 214 }; 215 216 static const char * const xscale_steppings[16] = { 217 "step A-0", "step A-1", "step B-0", "step C-0", 218 "step D-0", "rev 5", "rev 6", "rev 7", 219 "rev 8", "rev 9", "rev 10", "rev 11", 220 "rev 12", "rev 13", "rev 14", "rev 15", 221 }; 222 223 static const char * const i80321_steppings[16] = { 224 "step A-0", "step B-0", "rev 2", "rev 3", 225 "rev 4", "rev 5", "rev 6", "rev 7", 226 "rev 8", "rev 9", "rev 10", "rev 11", 227 "rev 12", "rev 13", "rev 14", "rev 15", 228 }; 229 230 static const char * const i80219_steppings[16] = { 231 "step A-0", "rev 1", "rev 2", "rev 3", 232 "rev 4", "rev 5", "rev 6", "rev 7", 233 "rev 8", "rev 9", "rev 10", "rev 11", 234 "rev 12", "rev 13", "rev 14", "rev 15", 235 }; 236 237 /* Steppings for PXA2[15]0 */ 238 static const char * const pxa2x0_steppings[16] = { 239 "step A-0", "step A-1", "step B-0", "step B-1", 240 "step B-2", "step C-0", "rev 6", "rev 7", 241 "rev 8", "rev 9", "rev 10", "rev 11", 242 "rev 12", "rev 13", "rev 14", "rev 15", 243 }; 244 245 /* Steppings for PXA255/26x. 246 * rev 5: PXA26x B0, rev 6: PXA255 A0 247 */ 248 static const char * const pxa255_steppings[16] = { 249 "rev 0", "rev 1", "rev 2", "step A-0", 250 "rev 4", "step B-0", "step A-0", "rev 7", 251 "rev 8", "rev 9", "rev 10", "rev 11", 252 "rev 12", "rev 13", "rev 14", "rev 15", 253 }; 254 255 /* Stepping for PXA27x */ 256 static const char * const pxa27x_steppings[16] = { 257 "step A-0", "step A-1", "step B-0", "step B-1", 258 "step C-0", "rev 5", "rev 6", "rev 7", 259 "rev 8", "rev 9", "rev 10", "rev 11", 260 "rev 12", "rev 13", "rev 14", "rev 15", 261 }; 262 263 static const char * const ixp425_steppings[16] = { 264 "step 0", "rev 1", "rev 2", "rev 3", 265 "rev 4", "rev 5", "rev 6", "rev 7", 266 "rev 8", "rev 9", "rev 10", "rev 11", 267 "rev 12", "rev 13", "rev 14", "rev 15", 268 }; 269 270 struct cpuidtab { 271 u_int32_t cpuid; 272 enum cpu_class cpu_class; 273 const char *cpu_name; 274 const char * const *cpu_steppings; 275 }; 276 277 const struct cpuidtab cpuids[] = { 278 { CPU_ID_ARM2, CPU_CLASS_ARM2, "ARM2", 279 generic_steppings }, 280 { CPU_ID_ARM250, CPU_CLASS_ARM2AS, "ARM250", 281 generic_steppings }, 282 283 { CPU_ID_ARM3, CPU_CLASS_ARM3, "ARM3", 284 generic_steppings }, 285 286 { CPU_ID_ARM600, CPU_CLASS_ARM6, "ARM600", 287 generic_steppings }, 288 { CPU_ID_ARM610, CPU_CLASS_ARM6, "ARM610", 289 generic_steppings }, 290 { CPU_ID_ARM620, CPU_CLASS_ARM6, "ARM620", 291 generic_steppings }, 292 293 { CPU_ID_ARM700, CPU_CLASS_ARM7, "ARM700", 294 generic_steppings }, 295 { CPU_ID_ARM710, CPU_CLASS_ARM7, "ARM710", 296 generic_steppings }, 297 { CPU_ID_ARM7500, CPU_CLASS_ARM7, "ARM7500", 298 generic_steppings }, 299 { CPU_ID_ARM710A, CPU_CLASS_ARM7, "ARM710a", 300 generic_steppings }, 301 { CPU_ID_ARM7500FE, CPU_CLASS_ARM7, "ARM7500FE", 302 generic_steppings }, 303 { CPU_ID_ARM710T, CPU_CLASS_ARM7TDMI, "ARM710T", 304 generic_steppings }, 305 { CPU_ID_ARM720T, CPU_CLASS_ARM7TDMI, "ARM720T", 306 generic_steppings }, 307 { CPU_ID_ARM740T8K, CPU_CLASS_ARM7TDMI, "ARM740T (8 KB cache)", 308 generic_steppings }, 309 { CPU_ID_ARM740T4K, CPU_CLASS_ARM7TDMI, "ARM740T (4 KB cache)", 310 generic_steppings }, 311 312 { CPU_ID_ARM810, CPU_CLASS_ARM8, "ARM810", 313 generic_steppings }, 314 315 { CPU_ID_ARM920T, CPU_CLASS_ARM9TDMI, "ARM920T", 316 generic_steppings }, 317 { CPU_ID_ARM922T, CPU_CLASS_ARM9TDMI, "ARM922T", 318 generic_steppings }, 319 { CPU_ID_ARM940T, CPU_CLASS_ARM9TDMI, "ARM940T", 320 generic_steppings }, 321 { CPU_ID_ARM946ES, CPU_CLASS_ARM9ES, "ARM946E-S", 322 generic_steppings }, 323 { CPU_ID_ARM966ES, CPU_CLASS_ARM9ES, "ARM966E-S", 324 generic_steppings }, 325 { CPU_ID_ARM966ESR1, CPU_CLASS_ARM9ES, "ARM966E-S", 326 generic_steppings }, 327 { CPU_ID_TI925T, CPU_CLASS_ARM9TDMI, "TI ARM925T", 328 generic_steppings }, 329 330 { CPU_ID_ARM1020E, CPU_CLASS_ARM10E, "ARM1020E", 331 generic_steppings }, 332 { CPU_ID_ARM1022ES, CPU_CLASS_ARM10E, "ARM1022E-S", 333 generic_steppings }, 334 { CPU_ID_ARM1026EJS, CPU_CLASS_ARM10EJ, "ARM1026EJ-S", 335 generic_steppings }, 336 337 { CPU_ID_SA110, CPU_CLASS_SA1, "SA-110", 338 sa110_steppings }, 339 { CPU_ID_SA1100, CPU_CLASS_SA1, "SA-1100", 340 sa1100_steppings }, 341 { CPU_ID_SA1110, CPU_CLASS_SA1, "SA-1110", 342 sa1110_steppings }, 343 344 { CPU_ID_IXP1200, CPU_CLASS_SA1, "IXP1200", 345 ixp12x0_steppings }, 346 347 { CPU_ID_80200, CPU_CLASS_XSCALE, "i80200", 348 xscale_steppings }, 349 350 { CPU_ID_80321_400, CPU_CLASS_XSCALE, "i80321 400MHz", 351 i80321_steppings }, 352 { CPU_ID_80321_600, CPU_CLASS_XSCALE, "i80321 600MHz", 353 i80321_steppings }, 354 { CPU_ID_80321_400_B0, CPU_CLASS_XSCALE, "i80321 400MHz", 355 i80321_steppings }, 356 { CPU_ID_80321_600_B0, CPU_CLASS_XSCALE, "i80321 600MHz", 357 i80321_steppings }, 358 359 { CPU_ID_80219_400, CPU_CLASS_XSCALE, "i80219 400MHz", 360 i80219_steppings }, 361 { CPU_ID_80219_600, CPU_CLASS_XSCALE, "i80219 600MHz", 362 i80219_steppings }, 363 364 { CPU_ID_PXA27X, CPU_CLASS_XSCALE, "PXA27x", 365 pxa27x_steppings }, 366 { CPU_ID_PXA250A, CPU_CLASS_XSCALE, "PXA250", 367 pxa2x0_steppings }, 368 { CPU_ID_PXA210A, CPU_CLASS_XSCALE, "PXA210", 369 pxa2x0_steppings }, 370 { CPU_ID_PXA250B, CPU_CLASS_XSCALE, "PXA250", 371 pxa2x0_steppings }, 372 { CPU_ID_PXA210B, CPU_CLASS_XSCALE, "PXA210", 373 pxa2x0_steppings }, 374 { CPU_ID_PXA250C, CPU_CLASS_XSCALE, "PXA255/26x", 375 pxa255_steppings }, 376 { CPU_ID_PXA210C, CPU_CLASS_XSCALE, "PXA210", 377 pxa2x0_steppings }, 378 379 { CPU_ID_IXP425_533, CPU_CLASS_XSCALE, "IXP425 533MHz", 380 ixp425_steppings }, 381 { CPU_ID_IXP425_400, CPU_CLASS_XSCALE, "IXP425 400MHz", 382 ixp425_steppings }, 383 { CPU_ID_IXP425_266, CPU_CLASS_XSCALE, "IXP425 266MHz", 384 ixp425_steppings }, 385 386 { CPU_ID_ARM1136JS, CPU_CLASS_ARM11J, "ARM1136J-S", 387 generic_steppings }, 388 { CPU_ID_ARM1136JSR1, CPU_CLASS_ARM11J, "ARM1136J-S R1", 389 generic_steppings }, 390 391 { 0, CPU_CLASS_NONE, NULL, NULL } 392 }; 393 394 struct cpu_classtab { 395 const char *class_name; 396 const char *class_option; 397 }; 398 399 const struct cpu_classtab cpu_classes[] = { 400 { "unknown", NULL }, /* CPU_CLASS_NONE */ 401 { "ARM2", "CPU_ARM2" }, /* CPU_CLASS_ARM2 */ 402 { "ARM2as", "CPU_ARM250" }, /* CPU_CLASS_ARM2AS */ 403 { "ARM3", "CPU_ARM3" }, /* CPU_CLASS_ARM3 */ 404 { "ARM6", "CPU_ARM6" }, /* CPU_CLASS_ARM6 */ 405 { "ARM7", "CPU_ARM7" }, /* CPU_CLASS_ARM7 */ 406 { "ARM7TDMI", "CPU_ARM7TDMI" }, /* CPU_CLASS_ARM7TDMI */ 407 { "ARM8", "CPU_ARM8" }, /* CPU_CLASS_ARM8 */ 408 { "ARM9TDMI", NULL }, /* CPU_CLASS_ARM9TDMI */ 409 { "ARM9E-S", NULL }, /* CPU_CLASS_ARM9ES */ 410 { "ARM10E", "CPU_ARM10" }, /* CPU_CLASS_ARM10E */ 411 { "ARM10EJ", "CPU_ARM10" }, /* CPU_CLASS_ARM10EJ */ 412 { "SA-1", "CPU_SA110" }, /* CPU_CLASS_SA1 */ 413 { "XScale", "CPU_XSCALE_..." }, /* CPU_CLASS_XSCALE */ 414 { "ARM11J", "CPU_ARM11" }, /* CPU_CLASS_ARM11J */ 415 }; 416 417 /* 418 * Report the type of the specified arm processor. This uses the generic and 419 * arm specific information in the CPU structure to identify the processor. 420 * The remaining fields in the CPU structure are filled in appropriately. 421 */ 422 423 static const char * const wtnames[] = { 424 "write-through", 425 "write-back", 426 "write-back", 427 "**unknown 3**", 428 "**unknown 4**", 429 "write-back-locking", /* XXX XScale-specific? */ 430 "write-back-locking-A", 431 "write-back-locking-B", 432 "**unknown 8**", 433 "**unknown 9**", 434 "**unknown 10**", 435 "**unknown 11**", 436 "**unknown 12**", 437 "**unknown 13**", 438 "write-back-locking-C", 439 "**unknown 15**", 440 }; 441 442 void 443 identify_arm_cpu(struct device *dv, struct cpu_info *ci) 444 { 445 u_int cpuid; 446 enum cpu_class cpu_class = CPU_CLASS_NONE; 447 int i; 448 449 cpuid = ci->ci_arm_cpuid; 450 451 if (cpuid == 0) { 452 aprint_error("Processor failed probe - no CPU ID\n"); 453 return; 454 } 455 456 for (i = 0; cpuids[i].cpuid != 0; i++) 457 if (cpuids[i].cpuid == (cpuid & CPU_ID_CPU_MASK)) { 458 cpu_class = cpuids[i].cpu_class; 459 sprintf(cpu_model, "%s %s (%s core)", 460 cpuids[i].cpu_name, 461 cpuids[i].cpu_steppings[cpuid & 462 CPU_ID_REVISION_MASK], 463 cpu_classes[cpu_class].class_name); 464 break; 465 } 466 467 if (cpuids[i].cpuid == 0) 468 sprintf(cpu_model, "unknown CPU (ID = 0x%x)", cpuid); 469 470 aprint_naive(": %s\n", cpu_model); 471 aprint_normal(": %s\n", cpu_model); 472 473 aprint_normal("%s:", dv->dv_xname); 474 475 switch (cpu_class) { 476 case CPU_CLASS_ARM6: 477 case CPU_CLASS_ARM7: 478 case CPU_CLASS_ARM7TDMI: 479 case CPU_CLASS_ARM8: 480 if ((ci->ci_ctrl & CPU_CONTROL_IDC_ENABLE) == 0) 481 aprint_normal(" IDC disabled"); 482 else 483 aprint_normal(" IDC enabled"); 484 break; 485 case CPU_CLASS_ARM9TDMI: 486 case CPU_CLASS_ARM10E: 487 case CPU_CLASS_ARM10EJ: 488 case CPU_CLASS_SA1: 489 case CPU_CLASS_XSCALE: 490 case CPU_CLASS_ARM11J: 491 if ((ci->ci_ctrl & CPU_CONTROL_DC_ENABLE) == 0) 492 aprint_normal(" DC disabled"); 493 else 494 aprint_normal(" DC enabled"); 495 if ((ci->ci_ctrl & CPU_CONTROL_IC_ENABLE) == 0) 496 aprint_normal(" IC disabled"); 497 else 498 aprint_normal(" IC enabled"); 499 break; 500 default: 501 break; 502 } 503 if ((ci->ci_ctrl & CPU_CONTROL_WBUF_ENABLE) == 0) 504 aprint_normal(" WB disabled"); 505 else 506 aprint_normal(" WB enabled"); 507 508 if (ci->ci_ctrl & CPU_CONTROL_LABT_ENABLE) 509 aprint_normal(" LABT"); 510 else 511 aprint_normal(" EABT"); 512 513 if (ci->ci_ctrl & CPU_CONTROL_BPRD_ENABLE) 514 aprint_normal(" branch prediction enabled"); 515 516 aprint_normal("\n"); 517 518 /* Print cache info. */ 519 if (arm_picache_line_size == 0 && arm_pdcache_line_size == 0) 520 goto skip_pcache; 521 522 if (arm_pcache_unified) { 523 aprint_normal("%s: %dKB/%dB %d-way %s unified cache\n", 524 dv->dv_xname, arm_pdcache_size / 1024, 525 arm_pdcache_line_size, arm_pdcache_ways, 526 wtnames[arm_pcache_type]); 527 } else { 528 aprint_normal("%s: %dKB/%dB %d-way Instruction cache\n", 529 dv->dv_xname, arm_picache_size / 1024, 530 arm_picache_line_size, arm_picache_ways); 531 aprint_normal("%s: %dKB/%dB %d-way %s Data cache\n", 532 dv->dv_xname, arm_pdcache_size / 1024, 533 arm_pdcache_line_size, arm_pdcache_ways, 534 wtnames[arm_pcache_type]); 535 } 536 537 skip_pcache: 538 539 switch (cpu_class) { 540 #ifdef CPU_ARM2 541 case CPU_CLASS_ARM2: 542 #endif 543 #ifdef CPU_ARM250 544 case CPU_CLASS_ARM2AS: 545 #endif 546 #ifdef CPU_ARM3 547 case CPU_CLASS_ARM3: 548 #endif 549 #ifdef CPU_ARM6 550 case CPU_CLASS_ARM6: 551 #endif 552 #ifdef CPU_ARM7 553 case CPU_CLASS_ARM7: 554 #endif 555 #ifdef CPU_ARM7TDMI 556 case CPU_CLASS_ARM7TDMI: 557 #endif 558 #ifdef CPU_ARM8 559 case CPU_CLASS_ARM8: 560 #endif 561 #ifdef CPU_ARM9 562 case CPU_CLASS_ARM9TDMI: 563 #endif 564 #ifdef CPU_ARM10 565 case CPU_CLASS_ARM10E: 566 case CPU_CLASS_ARM10EJ: 567 #endif 568 #if defined(CPU_SA110) || defined(CPU_SA1100) || \ 569 defined(CPU_SA1110) || defined(CPU_IXP12X0) 570 case CPU_CLASS_SA1: 571 #endif 572 #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 573 defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425) 574 case CPU_CLASS_XSCALE: 575 #endif 576 #ifdef CPU_ARM11 577 case CPU_CLASS_ARM11J: 578 #endif 579 break; 580 default: 581 if (cpu_classes[cpu_class].class_option != NULL) 582 aprint_error("%s: %s does not fully support this CPU." 583 "\n", dv->dv_xname, ostype); 584 else { 585 aprint_error("%s: This kernel does not fully support " 586 "this CPU.\n", dv->dv_xname); 587 aprint_normal("%s: Recompile with \"options %s\" to " 588 "correct this.\n", dv->dv_xname, 589 cpu_classes[cpu_class].class_option); 590 } 591 break; 592 } 593 594 } 595 #ifdef MULTIPROCESSOR 596 int 597 cpu_alloc_idlepcb(struct cpu_info *ci) 598 { 599 vaddr_t uaddr; 600 struct pcb *pcb; 601 struct trapframe *tf; 602 603 /* 604 * Generate a kernel stack and PCB (in essence, a u-area) for the 605 * new CPU. 606 */ 607 uaddr = uvm_km_alloc(kernel_map, USPACE, 0, UVM_KMF_WIRED); 608 if (!uaddr) 609 return ENOMEM; 610 ci->ci_idlepcb = pcb = (struct pcb *)uaddr; 611 612 /* 613 * This code is largely derived from cpu_fork(), with which it 614 * should perhaps be shared. 615 */ 616 617 /* Copy the pcb */ 618 *pcb = proc0.p_addr->u_pcb; 619 620 /* Set up the undefined stack for the process. */ 621 pcb->pcb_un.un_32.pcb32_und_sp = uaddr + USPACE_UNDEF_STACK_TOP; 622 pcb->pcb_un.un_32.pcb32_sp = uaddr + USPACE_SVC_STACK_TOP; 623 624 #ifdef STACKCHECKS 625 /* Fill the undefined stack with a known pattern */ 626 memset(((u_char *)uaddr) + USPACE_UNDEF_STACK_BOTTOM, 0xdd, 627 (USPACE_UNDEF_STACK_TOP - USPACE_UNDEF_STACK_BOTTOM)); 628 /* Fill the kernel stack with a known pattern */ 629 memset(((u_char *)uaddr) + USPACE_SVC_STACK_BOTTOM, 0xdd, 630 (USPACE_SVC_STACK_TOP - USPACE_SVC_STACK_BOTTOM)); 631 #endif /* STACKCHECKS */ 632 633 pcb->pcb_tf = tf = 634 (struct trapframe *)pcb->pcb_un.un_32.pcb32_sp - 1; 635 *tf = *proc0.p_addr->u_pcb.pcb_tf; 636 return 0; 637 } 638 #endif /* MULTIPROCESSOR */ 639 640 /* End of cpu.c */ 641
Indexes created Wed Sep 24 15:09:51 GMT 2025