cpu.c revision 1.64
1 /* $NetBSD: cpu.c,v 1.64 2007/01/06 00:50:54 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Mark Brinicombe. 5 * Copyright (c) 1995 Brini. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Brini. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * cpu.c 38 * 39 * Probing and configuration for the master CPU 40 * 41 * Created : 10/10/95 42 */ 43 44 #include "opt_armfpe.h" 45 #include "opt_multiprocessor.h" 46 47 #include <sys/param.h> 48 49 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.64 2007/01/06 00:50:54 christos Exp $"); 50 51 #include <sys/systm.h> 52 #include <sys/malloc.h> 53 #include <sys/device.h> 54 #include <sys/proc.h> 55 #include <sys/conf.h> 56 #include <uvm/uvm_extern.h> 57 #include <machine/cpu.h> 58 59 #include <arm/cpuconf.h> 60 #include <arm/undefined.h> 61 62 #ifdef ARMFPE 63 #include <machine/bootconfig.h> /* For boot args */ 64 #include <arm/fpe-arm/armfpe.h> 65 #endif 66 67 char cpu_model[256]; 68 69 /* Prototypes */ 70 void identify_arm_cpu(struct device *dv, struct cpu_info *); 71 72 /* 73 * Identify the master (boot) CPU 74 */ 75 76 void 77 cpu_attach(struct device *dv) 78 { 79 int usearmfpe; 80 81 usearmfpe = 1; /* when compiled in, its enabled by default */ 82 83 curcpu()->ci_dev = dv; 84 85 evcnt_attach_dynamic(&curcpu()->ci_arm700bugcount, EVCNT_TYPE_MISC, 86 NULL, dv->dv_xname, "arm700swibug"); 87 88 /* Get the CPU ID from coprocessor 15 */ 89 90 curcpu()->ci_arm_cpuid = cpu_id(); 91 curcpu()->ci_arm_cputype = curcpu()->ci_arm_cpuid & CPU_ID_CPU_MASK; 92 curcpu()->ci_arm_cpurev = 93 curcpu()->ci_arm_cpuid & CPU_ID_REVISION_MASK; 94 95 identify_arm_cpu(dv, curcpu()); 96 97 if (curcpu()->ci_arm_cputype == CPU_ID_SA110 && 98 curcpu()->ci_arm_cpurev < 3) { 99 aprint_normal("%s: SA-110 with bugged STM^ instruction\n", 100 dv->dv_xname); 101 } 102 103 #ifdef CPU_ARM8 104 if ((curcpu()->ci_arm_cpuid & CPU_ID_CPU_MASK) == CPU_ID_ARM810) { 105 int clock = arm8_clock_config(0, 0); 106 char *fclk; 107 aprint_normal("%s: ARM810 cp15=%02x", dv->dv_xname, clock); 108 aprint_normal(" clock:%s", (clock & 1) ? " dynamic" : ""); 109 aprint_normal("%s", (clock & 2) ? " sync" : ""); 110 switch ((clock >> 2) & 3) { 111 case 0: 112 fclk = "bus clock"; 113 break; 114 case 1: 115 fclk = "ref clock"; 116 break; 117 case 3: 118 fclk = "pll"; 119 break; 120 default: 121 fclk = "illegal"; 122 break; 123 } 124 aprint_normal(" fclk source=%s\n", fclk); 125 } 126 #endif 127 128 #ifdef ARMFPE 129 /* 130 * Ok now we test for an FPA 131 * At this point no floating point emulator has been installed. 132 * This means any FP instruction will cause undefined exception. 133 * We install a temporay coproc 1 handler which will modify 134 * undefined_test if it is called. 135 * We then try to read the FP status register. If undefined_test 136 * has been decremented then the instruction was not handled by 137 * an FPA so we know the FPA is missing. If undefined_test is 138 * still 1 then we know the instruction was handled by an FPA. 139 * We then remove our test handler and look at the 140 * FP status register for identification. 141 */ 142 143 /* 144 * Ok if ARMFPE is defined and the boot options request the 145 * ARM FPE then it will be installed as the FPE. 146 * This is just while I work on integrating the new FPE. 147 * It means the new FPE gets installed if compiled int (ARMFPE 148 * defined) and also gives me a on/off option when I boot in 149 * case the new FPE is causing panics. 150 */ 151 152 153 if (boot_args) 154 get_bootconf_option(boot_args, "armfpe", 155 BOOTOPT_TYPE_BOOLEAN, &usearmfpe); 156 if (usearmfpe) 157 initialise_arm_fpe(); 158 #endif 159 } 160 161 enum cpu_class { 162 CPU_CLASS_NONE, 163 CPU_CLASS_ARM2, 164 CPU_CLASS_ARM2AS, 165 CPU_CLASS_ARM3, 166 CPU_CLASS_ARM6, 167 CPU_CLASS_ARM7, 168 CPU_CLASS_ARM7TDMI, 169 CPU_CLASS_ARM8, 170 CPU_CLASS_ARM9TDMI, 171 CPU_CLASS_ARM9ES, 172 CPU_CLASS_ARM9EJS, 173 CPU_CLASS_ARM10E, 174 CPU_CLASS_ARM10EJ, 175 CPU_CLASS_SA1, 176 CPU_CLASS_XSCALE, 177 CPU_CLASS_ARM11J 178 }; 179 180 static const char * const generic_steppings[16] = { 181 "rev 0", "rev 1", "rev 2", "rev 3", 182 "rev 4", "rev 5", "rev 6", "rev 7", 183 "rev 8", "rev 9", "rev 10", "rev 11", 184 "rev 12", "rev 13", "rev 14", "rev 15", 185 }; 186 187 static const char * const sa110_steppings[16] = { 188 "rev 0", "step J", "step K", "step S", 189 "step T", "rev 5", "rev 6", "rev 7", 190 "rev 8", "rev 9", "rev 10", "rev 11", 191 "rev 12", "rev 13", "rev 14", "rev 15", 192 }; 193 194 static const char * const sa1100_steppings[16] = { 195 "rev 0", "step B", "step C", "rev 3", 196 "rev 4", "rev 5", "rev 6", "rev 7", 197 "step D", "step E", "rev 10" "step G", 198 "rev 12", "rev 13", "rev 14", "rev 15", 199 }; 200 201 static const char * const sa1110_steppings[16] = { 202 "step A-0", "rev 1", "rev 2", "rev 3", 203 "step B-0", "step B-1", "step B-2", "step B-3", 204 "step B-4", "step B-5", "rev 10", "rev 11", 205 "rev 12", "rev 13", "rev 14", "rev 15", 206 }; 207 208 static const char * const ixp12x0_steppings[16] = { 209 "(IXP1200 step A)", "(IXP1200 step B)", 210 "rev 2", "(IXP1200 step C)", 211 "(IXP1200 step D)", "(IXP1240/1250 step A)", 212 "(IXP1240 step B)", "(IXP1250 step B)", 213 "rev 8", "rev 9", "rev 10", "rev 11", 214 "rev 12", "rev 13", "rev 14", "rev 15", 215 }; 216 217 static const char * const xscale_steppings[16] = { 218 "step A-0", "step A-1", "step B-0", "step C-0", 219 "step D-0", "rev 5", "rev 6", "rev 7", 220 "rev 8", "rev 9", "rev 10", "rev 11", 221 "rev 12", "rev 13", "rev 14", "rev 15", 222 }; 223 224 static const char * const i80321_steppings[16] = { 225 "step A-0", "step B-0", "rev 2", "rev 3", 226 "rev 4", "rev 5", "rev 6", "rev 7", 227 "rev 8", "rev 9", "rev 10", "rev 11", 228 "rev 12", "rev 13", "rev 14", "rev 15", 229 }; 230 231 static const char * const i80219_steppings[16] = { 232 "step A-0", "rev 1", "rev 2", "rev 3", 233 "rev 4", "rev 5", "rev 6", "rev 7", 234 "rev 8", "rev 9", "rev 10", "rev 11", 235 "rev 12", "rev 13", "rev 14", "rev 15", 236 }; 237 238 /* Steppings for PXA2[15]0 */ 239 static const char * const pxa2x0_steppings[16] = { 240 "step A-0", "step A-1", "step B-0", "step B-1", 241 "step B-2", "step C-0", "rev 6", "rev 7", 242 "rev 8", "rev 9", "rev 10", "rev 11", 243 "rev 12", "rev 13", "rev 14", "rev 15", 244 }; 245 246 /* Steppings for PXA255/26x. 247 * rev 5: PXA26x B0, rev 6: PXA255 A0 248 */ 249 static const char * const pxa255_steppings[16] = { 250 "rev 0", "rev 1", "rev 2", "step A-0", 251 "rev 4", "step B-0", "step A-0", "rev 7", 252 "rev 8", "rev 9", "rev 10", "rev 11", 253 "rev 12", "rev 13", "rev 14", "rev 15", 254 }; 255 256 /* Stepping for PXA27x */ 257 static const char * const pxa27x_steppings[16] = { 258 "step A-0", "step A-1", "step B-0", "step B-1", 259 "step C-0", "rev 5", "rev 6", "rev 7", 260 "rev 8", "rev 9", "rev 10", "rev 11", 261 "rev 12", "rev 13", "rev 14", "rev 15", 262 }; 263 264 static const char * const ixp425_steppings[16] = { 265 "step 0", "rev 1", "rev 2", "rev 3", 266 "rev 4", "rev 5", "rev 6", "rev 7", 267 "rev 8", "rev 9", "rev 10", "rev 11", 268 "rev 12", "rev 13", "rev 14", "rev 15", 269 }; 270 271 struct cpuidtab { 272 u_int32_t cpuid; 273 enum cpu_class cpu_class; 274 const char *cpu_name; 275 const char * const *cpu_steppings; 276 }; 277 278 const struct cpuidtab cpuids[] = { 279 { CPU_ID_ARM2, CPU_CLASS_ARM2, "ARM2", 280 generic_steppings }, 281 { CPU_ID_ARM250, CPU_CLASS_ARM2AS, "ARM250", 282 generic_steppings }, 283 284 { CPU_ID_ARM3, CPU_CLASS_ARM3, "ARM3", 285 generic_steppings }, 286 287 { CPU_ID_ARM600, CPU_CLASS_ARM6, "ARM600", 288 generic_steppings }, 289 { CPU_ID_ARM610, CPU_CLASS_ARM6, "ARM610", 290 generic_steppings }, 291 { CPU_ID_ARM620, CPU_CLASS_ARM6, "ARM620", 292 generic_steppings }, 293 294 { CPU_ID_ARM700, CPU_CLASS_ARM7, "ARM700", 295 generic_steppings }, 296 { CPU_ID_ARM710, CPU_CLASS_ARM7, "ARM710", 297 generic_steppings }, 298 { CPU_ID_ARM7500, CPU_CLASS_ARM7, "ARM7500", 299 generic_steppings }, 300 { CPU_ID_ARM710A, CPU_CLASS_ARM7, "ARM710a", 301 generic_steppings }, 302 { CPU_ID_ARM7500FE, CPU_CLASS_ARM7, "ARM7500FE", 303 generic_steppings }, 304 { CPU_ID_ARM710T, CPU_CLASS_ARM7TDMI, "ARM710T", 305 generic_steppings }, 306 { CPU_ID_ARM720T, CPU_CLASS_ARM7TDMI, "ARM720T", 307 generic_steppings }, 308 { CPU_ID_ARM740T8K, CPU_CLASS_ARM7TDMI, "ARM740T (8 KB cache)", 309 generic_steppings }, 310 { CPU_ID_ARM740T4K, CPU_CLASS_ARM7TDMI, "ARM740T (4 KB cache)", 311 generic_steppings }, 312 313 { CPU_ID_ARM810, CPU_CLASS_ARM8, "ARM810", 314 generic_steppings }, 315 316 { CPU_ID_ARM920T, CPU_CLASS_ARM9TDMI, "ARM920T", 317 generic_steppings }, 318 { CPU_ID_ARM922T, CPU_CLASS_ARM9TDMI, "ARM922T", 319 generic_steppings }, 320 { CPU_ID_ARM926EJS, CPU_CLASS_ARM9EJS, "ARM926EJ-S", 321 generic_steppings }, 322 { CPU_ID_ARM940T, CPU_CLASS_ARM9TDMI, "ARM940T", 323 generic_steppings }, 324 { CPU_ID_ARM946ES, CPU_CLASS_ARM9ES, "ARM946E-S", 325 generic_steppings }, 326 { CPU_ID_ARM966ES, CPU_CLASS_ARM9ES, "ARM966E-S", 327 generic_steppings }, 328 { CPU_ID_ARM966ESR1, CPU_CLASS_ARM9ES, "ARM966E-S", 329 generic_steppings }, 330 { CPU_ID_TI925T, CPU_CLASS_ARM9TDMI, "TI ARM925T", 331 generic_steppings }, 332 333 { CPU_ID_ARM1020E, CPU_CLASS_ARM10E, "ARM1020E", 334 generic_steppings }, 335 { CPU_ID_ARM1022ES, CPU_CLASS_ARM10E, "ARM1022E-S", 336 generic_steppings }, 337 { CPU_ID_ARM1026EJS, CPU_CLASS_ARM10EJ, "ARM1026EJ-S", 338 generic_steppings }, 339 340 { CPU_ID_SA110, CPU_CLASS_SA1, "SA-110", 341 sa110_steppings }, 342 { CPU_ID_SA1100, CPU_CLASS_SA1, "SA-1100", 343 sa1100_steppings }, 344 { CPU_ID_SA1110, CPU_CLASS_SA1, "SA-1110", 345 sa1110_steppings }, 346 347 { CPU_ID_IXP1200, CPU_CLASS_SA1, "IXP1200", 348 ixp12x0_steppings }, 349 350 { CPU_ID_80200, CPU_CLASS_XSCALE, "i80200", 351 xscale_steppings }, 352 353 { CPU_ID_80321_400, CPU_CLASS_XSCALE, "i80321 400MHz", 354 i80321_steppings }, 355 { CPU_ID_80321_600, CPU_CLASS_XSCALE, "i80321 600MHz", 356 i80321_steppings }, 357 { CPU_ID_80321_400_B0, CPU_CLASS_XSCALE, "i80321 400MHz", 358 i80321_steppings }, 359 { CPU_ID_80321_600_B0, CPU_CLASS_XSCALE, "i80321 600MHz", 360 i80321_steppings }, 361 362 { CPU_ID_80219_400, CPU_CLASS_XSCALE, "i80219 400MHz", 363 i80219_steppings }, 364 { CPU_ID_80219_600, CPU_CLASS_XSCALE, "i80219 600MHz", 365 i80219_steppings }, 366 367 { CPU_ID_PXA27X, CPU_CLASS_XSCALE, "PXA27x", 368 pxa27x_steppings }, 369 { CPU_ID_PXA250A, CPU_CLASS_XSCALE, "PXA250", 370 pxa2x0_steppings }, 371 { CPU_ID_PXA210A, CPU_CLASS_XSCALE, "PXA210", 372 pxa2x0_steppings }, 373 { CPU_ID_PXA250B, CPU_CLASS_XSCALE, "PXA250", 374 pxa2x0_steppings }, 375 { CPU_ID_PXA210B, CPU_CLASS_XSCALE, "PXA210", 376 pxa2x0_steppings }, 377 { CPU_ID_PXA250C, CPU_CLASS_XSCALE, "PXA255/26x", 378 pxa255_steppings }, 379 { CPU_ID_PXA210C, CPU_CLASS_XSCALE, "PXA210", 380 pxa2x0_steppings }, 381 382 { CPU_ID_IXP425_533, CPU_CLASS_XSCALE, "IXP425 533MHz", 383 ixp425_steppings }, 384 { CPU_ID_IXP425_400, CPU_CLASS_XSCALE, "IXP425 400MHz", 385 ixp425_steppings }, 386 { CPU_ID_IXP425_266, CPU_CLASS_XSCALE, "IXP425 266MHz", 387 ixp425_steppings }, 388 389 { CPU_ID_ARM1136JS, CPU_CLASS_ARM11J, "ARM1136J-S", 390 generic_steppings }, 391 { CPU_ID_ARM1136JSR1, CPU_CLASS_ARM11J, "ARM1136J-S R1", 392 generic_steppings }, 393 394 { 0, CPU_CLASS_NONE, NULL, NULL } 395 }; 396 397 struct cpu_classtab { 398 const char *class_name; 399 const char *class_option; 400 }; 401 402 const struct cpu_classtab cpu_classes[] = { 403 { "unknown", NULL }, /* CPU_CLASS_NONE */ 404 { "ARM2", "CPU_ARM2" }, /* CPU_CLASS_ARM2 */ 405 { "ARM2as", "CPU_ARM250" }, /* CPU_CLASS_ARM2AS */ 406 { "ARM3", "CPU_ARM3" }, /* CPU_CLASS_ARM3 */ 407 { "ARM6", "CPU_ARM6" }, /* CPU_CLASS_ARM6 */ 408 { "ARM7", "CPU_ARM7" }, /* CPU_CLASS_ARM7 */ 409 { "ARM7TDMI", "CPU_ARM7TDMI" }, /* CPU_CLASS_ARM7TDMI */ 410 { "ARM8", "CPU_ARM8" }, /* CPU_CLASS_ARM8 */ 411 { "ARM9TDMI", NULL }, /* CPU_CLASS_ARM9TDMI */ 412 { "ARM9E-S", "CPU_ARM9E" }, /* CPU_CLASS_ARM9ES */ 413 { "ARM9EJ-S", "CPU_ARM9E" }, /* CPU_CLASS_ARM9EJS */ 414 { "ARM10E", "CPU_ARM10" }, /* CPU_CLASS_ARM10E */ 415 { "ARM10EJ", "CPU_ARM10" }, /* CPU_CLASS_ARM10EJ */ 416 { "SA-1", "CPU_SA110" }, /* CPU_CLASS_SA1 */ 417 { "XScale", "CPU_XSCALE_..." }, /* CPU_CLASS_XSCALE */ 418 { "ARM11J", "CPU_ARM11" }, /* CPU_CLASS_ARM11J */ 419 }; 420 421 /* 422 * Report the type of the specified arm processor. This uses the generic and 423 * arm specific information in the CPU structure to identify the processor. 424 * The remaining fields in the CPU structure are filled in appropriately. 425 */ 426 427 static const char * const wtnames[] = { 428 "write-through", 429 "write-back", 430 "write-back", 431 "**unknown 3**", 432 "**unknown 4**", 433 "write-back-locking", /* XXX XScale-specific? */ 434 "write-back-locking-A", 435 "write-back-locking-B", 436 "**unknown 8**", 437 "**unknown 9**", 438 "**unknown 10**", 439 "**unknown 11**", 440 "**unknown 12**", 441 "**unknown 13**", 442 "write-back-locking-C", 443 "**unknown 15**", 444 }; 445 446 void 447 identify_arm_cpu(struct device *dv, struct cpu_info *ci) 448 { 449 u_int cpuid; 450 enum cpu_class cpu_class = CPU_CLASS_NONE; 451 int i; 452 453 cpuid = ci->ci_arm_cpuid; 454 455 if (cpuid == 0) { 456 aprint_error("Processor failed probe - no CPU ID\n"); 457 return; 458 } 459 460 for (i = 0; cpuids[i].cpuid != 0; i++) 461 if (cpuids[i].cpuid == (cpuid & CPU_ID_CPU_MASK)) { 462 cpu_class = cpuids[i].cpu_class; 463 sprintf(cpu_model, "%s %s (%s core)", 464 cpuids[i].cpu_name, 465 cpuids[i].cpu_steppings[cpuid & 466 CPU_ID_REVISION_MASK], 467 cpu_classes[cpu_class].class_name); 468 break; 469 } 470 471 if (cpuids[i].cpuid == 0) 472 sprintf(cpu_model, "unknown CPU (ID = 0x%x)", cpuid); 473 474 aprint_naive(": %s\n", cpu_model); 475 aprint_normal(": %s\n", cpu_model); 476 477 aprint_normal("%s:", dv->dv_xname); 478 479 switch (cpu_class) { 480 case CPU_CLASS_ARM6: 481 case CPU_CLASS_ARM7: 482 case CPU_CLASS_ARM7TDMI: 483 case CPU_CLASS_ARM8: 484 if ((ci->ci_ctrl & CPU_CONTROL_IDC_ENABLE) == 0) 485 aprint_normal(" IDC disabled"); 486 else 487 aprint_normal(" IDC enabled"); 488 break; 489 case CPU_CLASS_ARM9TDMI: 490 case CPU_CLASS_ARM9ES: 491 case CPU_CLASS_ARM9EJS: 492 case CPU_CLASS_ARM10E: 493 case CPU_CLASS_ARM10EJ: 494 case CPU_CLASS_SA1: 495 case CPU_CLASS_XSCALE: 496 case CPU_CLASS_ARM11J: 497 if ((ci->ci_ctrl & CPU_CONTROL_DC_ENABLE) == 0) 498 aprint_normal(" DC disabled"); 499 else 500 aprint_normal(" DC enabled"); 501 if ((ci->ci_ctrl & CPU_CONTROL_IC_ENABLE) == 0) 502 aprint_normal(" IC disabled"); 503 else 504 aprint_normal(" IC enabled"); 505 break; 506 default: 507 break; 508 } 509 if ((ci->ci_ctrl & CPU_CONTROL_WBUF_ENABLE) == 0) 510 aprint_normal(" WB disabled"); 511 else 512 aprint_normal(" WB enabled"); 513 514 if (ci->ci_ctrl & CPU_CONTROL_LABT_ENABLE) 515 aprint_normal(" LABT"); 516 else 517 aprint_normal(" EABT"); 518 519 if (ci->ci_ctrl & CPU_CONTROL_BPRD_ENABLE) 520 aprint_normal(" branch prediction enabled"); 521 522 aprint_normal("\n"); 523 524 /* Print cache info. */ 525 if (arm_picache_line_size == 0 && arm_pdcache_line_size == 0) 526 goto skip_pcache; 527 528 if (arm_pcache_unified) { 529 aprint_normal("%s: %dKB/%dB %d-way %s unified cache\n", 530 dv->dv_xname, arm_pdcache_size / 1024, 531 arm_pdcache_line_size, arm_pdcache_ways, 532 wtnames[arm_pcache_type]); 533 } else { 534 aprint_normal("%s: %dKB/%dB %d-way Instruction cache\n", 535 dv->dv_xname, arm_picache_size / 1024, 536 arm_picache_line_size, arm_picache_ways); 537 aprint_normal("%s: %dKB/%dB %d-way %s Data cache\n", 538 dv->dv_xname, arm_pdcache_size / 1024, 539 arm_pdcache_line_size, arm_pdcache_ways, 540 wtnames[arm_pcache_type]); 541 } 542 543 skip_pcache: 544 545 switch (cpu_class) { 546 #ifdef CPU_ARM2 547 case CPU_CLASS_ARM2: 548 #endif 549 #ifdef CPU_ARM250 550 case CPU_CLASS_ARM2AS: 551 #endif 552 #ifdef CPU_ARM3 553 case CPU_CLASS_ARM3: 554 #endif 555 #ifdef CPU_ARM6 556 case CPU_CLASS_ARM6: 557 #endif 558 #ifdef CPU_ARM7 559 case CPU_CLASS_ARM7: 560 #endif 561 #ifdef CPU_ARM7TDMI 562 case CPU_CLASS_ARM7TDMI: 563 #endif 564 #ifdef CPU_ARM8 565 case CPU_CLASS_ARM8: 566 #endif 567 #ifdef CPU_ARM9 568 case CPU_CLASS_ARM9TDMI: 569 #endif 570 #ifdef CPU_ARM9E 571 case CPU_CLASS_ARM9ES: 572 case CPU_CLASS_ARM9EJS: 573 #endif 574 #ifdef CPU_ARM10 575 case CPU_CLASS_ARM10E: 576 case CPU_CLASS_ARM10EJ: 577 #endif 578 #if defined(CPU_SA110) || defined(CPU_SA1100) || \ 579 defined(CPU_SA1110) || defined(CPU_IXP12X0) 580 case CPU_CLASS_SA1: 581 #endif 582 #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 583 defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425) 584 case CPU_CLASS_XSCALE: 585 #endif 586 #ifdef CPU_ARM11 587 case CPU_CLASS_ARM11J: 588 #endif 589 break; 590 default: 591 if (cpu_classes[cpu_class].class_option == NULL) 592 aprint_error("%s: %s does not fully support this CPU." 593 "\n", dv->dv_xname, ostype); 594 else { 595 aprint_error("%s: This kernel does not fully support " 596 "this CPU.\n", dv->dv_xname); 597 aprint_normal("%s: Recompile with \"options %s\" to " 598 "correct this.\n", dv->dv_xname, 599 cpu_classes[cpu_class].class_option); 600 } 601 break; 602 } 603 604 } 605 #ifdef MULTIPROCESSOR 606 int 607 cpu_alloc_idlepcb(struct cpu_info *ci) 608 { 609 vaddr_t uaddr; 610 struct pcb *pcb; 611 struct trapframe *tf; 612 613 /* 614 * Generate a kernel stack and PCB (in essence, a u-area) for the 615 * new CPU. 616 */ 617 uaddr = uvm_km_alloc(kernel_map, USPACE, 0, UVM_KMF_WIRED); 618 if (!uaddr) 619 return ENOMEM; 620 ci->ci_idlepcb = pcb = (struct pcb *)uaddr; 621 622 /* 623 * This code is largely derived from cpu_fork(), with which it 624 * should perhaps be shared. 625 */ 626 627 /* Copy the pcb */ 628 *pcb = proc0.p_addr->u_pcb; 629 630 /* Set up the undefined stack for the process. */ 631 pcb->pcb_un.un_32.pcb32_und_sp = uaddr + USPACE_UNDEF_STACK_TOP; 632 pcb->pcb_un.un_32.pcb32_sp = uaddr + USPACE_SVC_STACK_TOP; 633 634 #ifdef STACKCHECKS 635 /* Fill the undefined stack with a known pattern */ 636 memset(((u_char *)uaddr) + USPACE_UNDEF_STACK_BOTTOM, 0xdd, 637 (USPACE_UNDEF_STACK_TOP - USPACE_UNDEF_STACK_BOTTOM)); 638 /* Fill the kernel stack with a known pattern */ 639 memset(((u_char *)uaddr) + USPACE_SVC_STACK_BOTTOM, 0xdd, 640 (USPACE_SVC_STACK_TOP - USPACE_SVC_STACK_BOTTOM)); 641 #endif /* STACKCHECKS */ 642 643 pcb->pcb_tf = tf = 644 (struct trapframe *)pcb->pcb_un.un_32.pcb32_sp - 1; 645 *tf = *proc0.p_addr->u_pcb.pcb_tf; 646 return 0; 647 } 648 #endif /* MULTIPROCESSOR */ 649 650 /* End of cpu.c */ 651
Indexes created Wed Sep 24 05:09:52 GMT 2025