cpu.c revision 1.67
1 /* $NetBSD: cpu.c,v 1.67 2008/03/15 10:19:40 rearnsha Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Mark Brinicombe. 5 * Copyright (c) 1995 Brini. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Brini. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * cpu.c 38 * 39 * Probing and configuration for the master CPU 40 * 41 * Created : 10/10/95 42 */ 43 44 #include "opt_armfpe.h" 45 #include "opt_multiprocessor.h" 46 47 #include <sys/param.h> 48 49 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.67 2008/03/15 10:19:40 rearnsha Exp $"); 50 51 #include <sys/systm.h> 52 #include <sys/malloc.h> 53 #include <sys/device.h> 54 #include <sys/proc.h> 55 #include <sys/conf.h> 56 #include <uvm/uvm_extern.h> 57 #include <machine/cpu.h> 58 59 #include <arm/cpuconf.h> 60 #include <arm/undefined.h> 61 62 #ifdef ARMFPE 63 #include <machine/bootconfig.h> /* For boot args */ 64 #include <arm/fpe-arm/armfpe.h> 65 #endif 66 67 #ifdef FPU_VFP 68 #include <arm/vfpvar.h> 69 #endif 70 71 char cpu_model[256]; 72 73 /* Prototypes */ 74 void identify_arm_cpu(struct device *dv, struct cpu_info *); 75 76 /* 77 * Identify the master (boot) CPU 78 */ 79 80 void 81 cpu_attach(struct device *dv) 82 { 83 int usearmfpe; 84 85 usearmfpe = 1; /* when compiled in, its enabled by default */ 86 87 curcpu()->ci_dev = dv; 88 89 evcnt_attach_dynamic(&curcpu()->ci_arm700bugcount, EVCNT_TYPE_MISC, 90 NULL, dv->dv_xname, "arm700swibug"); 91 92 /* Get the CPU ID from coprocessor 15 */ 93 94 curcpu()->ci_arm_cpuid = cpu_id(); 95 curcpu()->ci_arm_cputype = curcpu()->ci_arm_cpuid & CPU_ID_CPU_MASK; 96 curcpu()->ci_arm_cpurev = 97 curcpu()->ci_arm_cpuid & CPU_ID_REVISION_MASK; 98 99 identify_arm_cpu(dv, curcpu()); 100 101 if (curcpu()->ci_arm_cputype == CPU_ID_SA110 && 102 curcpu()->ci_arm_cpurev < 3) { 103 aprint_normal("%s: SA-110 with bugged STM^ instruction\n", 104 dv->dv_xname); 105 } 106 107 #ifdef CPU_ARM8 108 if ((curcpu()->ci_arm_cpuid & CPU_ID_CPU_MASK) == CPU_ID_ARM810) { 109 int clock = arm8_clock_config(0, 0); 110 char *fclk; 111 aprint_normal("%s: ARM810 cp15=%02x", dv->dv_xname, clock); 112 aprint_normal(" clock:%s", (clock & 1) ? " dynamic" : ""); 113 aprint_normal("%s", (clock & 2) ? " sync" : ""); 114 switch ((clock >> 2) & 3) { 115 case 0: 116 fclk = "bus clock"; 117 break; 118 case 1: 119 fclk = "ref clock"; 120 break; 121 case 3: 122 fclk = "pll"; 123 break; 124 default: 125 fclk = "illegal"; 126 break; 127 } 128 aprint_normal(" fclk source=%s\n", fclk); 129 } 130 #endif 131 132 #ifdef ARMFPE 133 /* 134 * Ok now we test for an FPA 135 * At this point no floating point emulator has been installed. 136 * This means any FP instruction will cause undefined exception. 137 * We install a temporay coproc 1 handler which will modify 138 * undefined_test if it is called. 139 * We then try to read the FP status register. If undefined_test 140 * has been decremented then the instruction was not handled by 141 * an FPA so we know the FPA is missing. If undefined_test is 142 * still 1 then we know the instruction was handled by an FPA. 143 * We then remove our test handler and look at the 144 * FP status register for identification. 145 */ 146 147 /* 148 * Ok if ARMFPE is defined and the boot options request the 149 * ARM FPE then it will be installed as the FPE. 150 * This is just while I work on integrating the new FPE. 151 * It means the new FPE gets installed if compiled int (ARMFPE 152 * defined) and also gives me a on/off option when I boot in 153 * case the new FPE is causing panics. 154 */ 155 156 157 if (boot_args) 158 get_bootconf_option(boot_args, "armfpe", 159 BOOTOPT_TYPE_BOOLEAN, &usearmfpe); 160 if (usearmfpe) 161 initialise_arm_fpe(); 162 #endif 163 164 #ifdef FPU_VFP 165 vfp_attach(); 166 #endif 167 } 168 169 enum cpu_class { 170 CPU_CLASS_NONE, 171 CPU_CLASS_ARM2, 172 CPU_CLASS_ARM2AS, 173 CPU_CLASS_ARM3, 174 CPU_CLASS_ARM6, 175 CPU_CLASS_ARM7, 176 CPU_CLASS_ARM7TDMI, 177 CPU_CLASS_ARM8, 178 CPU_CLASS_ARM9TDMI, 179 CPU_CLASS_ARM9ES, 180 CPU_CLASS_ARM9EJS, 181 CPU_CLASS_ARM10E, 182 CPU_CLASS_ARM10EJ, 183 CPU_CLASS_SA1, 184 CPU_CLASS_XSCALE, 185 CPU_CLASS_ARM11J 186 }; 187 188 static const char * const generic_steppings[16] = { 189 "rev 0", "rev 1", "rev 2", "rev 3", 190 "rev 4", "rev 5", "rev 6", "rev 7", 191 "rev 8", "rev 9", "rev 10", "rev 11", 192 "rev 12", "rev 13", "rev 14", "rev 15", 193 }; 194 195 static const char * const sa110_steppings[16] = { 196 "rev 0", "step J", "step K", "step S", 197 "step T", "rev 5", "rev 6", "rev 7", 198 "rev 8", "rev 9", "rev 10", "rev 11", 199 "rev 12", "rev 13", "rev 14", "rev 15", 200 }; 201 202 static const char * const sa1100_steppings[16] = { 203 "rev 0", "step B", "step C", "rev 3", 204 "rev 4", "rev 5", "rev 6", "rev 7", 205 "step D", "step E", "rev 10" "step G", 206 "rev 12", "rev 13", "rev 14", "rev 15", 207 }; 208 209 static const char * const sa1110_steppings[16] = { 210 "step A-0", "rev 1", "rev 2", "rev 3", 211 "step B-0", "step B-1", "step B-2", "step B-3", 212 "step B-4", "step B-5", "rev 10", "rev 11", 213 "rev 12", "rev 13", "rev 14", "rev 15", 214 }; 215 216 static const char * const ixp12x0_steppings[16] = { 217 "(IXP1200 step A)", "(IXP1200 step B)", 218 "rev 2", "(IXP1200 step C)", 219 "(IXP1200 step D)", "(IXP1240/1250 step A)", 220 "(IXP1240 step B)", "(IXP1250 step B)", 221 "rev 8", "rev 9", "rev 10", "rev 11", 222 "rev 12", "rev 13", "rev 14", "rev 15", 223 }; 224 225 static const char * const xscale_steppings[16] = { 226 "step A-0", "step A-1", "step B-0", "step C-0", 227 "step D-0", "rev 5", "rev 6", "rev 7", 228 "rev 8", "rev 9", "rev 10", "rev 11", 229 "rev 12", "rev 13", "rev 14", "rev 15", 230 }; 231 232 static const char * const i80321_steppings[16] = { 233 "step A-0", "step B-0", "rev 2", "rev 3", 234 "rev 4", "rev 5", "rev 6", "rev 7", 235 "rev 8", "rev 9", "rev 10", "rev 11", 236 "rev 12", "rev 13", "rev 14", "rev 15", 237 }; 238 239 static const char * const i80219_steppings[16] = { 240 "step A-0", "rev 1", "rev 2", "rev 3", 241 "rev 4", "rev 5", "rev 6", "rev 7", 242 "rev 8", "rev 9", "rev 10", "rev 11", 243 "rev 12", "rev 13", "rev 14", "rev 15", 244 }; 245 246 /* Steppings for PXA2[15]0 */ 247 static const char * const pxa2x0_steppings[16] = { 248 "step A-0", "step A-1", "step B-0", "step B-1", 249 "step B-2", "step C-0", "rev 6", "rev 7", 250 "rev 8", "rev 9", "rev 10", "rev 11", 251 "rev 12", "rev 13", "rev 14", "rev 15", 252 }; 253 254 /* Steppings for PXA255/26x. 255 * rev 5: PXA26x B0, rev 6: PXA255 A0 256 */ 257 static const char * const pxa255_steppings[16] = { 258 "rev 0", "rev 1", "rev 2", "step A-0", 259 "rev 4", "step B-0", "step A-0", "rev 7", 260 "rev 8", "rev 9", "rev 10", "rev 11", 261 "rev 12", "rev 13", "rev 14", "rev 15", 262 }; 263 264 /* Stepping for PXA27x */ 265 static const char * const pxa27x_steppings[16] = { 266 "step A-0", "step A-1", "step B-0", "step B-1", 267 "step C-0", "rev 5", "rev 6", "rev 7", 268 "rev 8", "rev 9", "rev 10", "rev 11", 269 "rev 12", "rev 13", "rev 14", "rev 15", 270 }; 271 272 static const char * const ixp425_steppings[16] = { 273 "step 0", "rev 1", "rev 2", "rev 3", 274 "rev 4", "rev 5", "rev 6", "rev 7", 275 "rev 8", "rev 9", "rev 10", "rev 11", 276 "rev 12", "rev 13", "rev 14", "rev 15", 277 }; 278 279 struct cpuidtab { 280 u_int32_t cpuid; 281 enum cpu_class cpu_class; 282 const char *cpu_name; 283 const char * const *cpu_steppings; 284 }; 285 286 const struct cpuidtab cpuids[] = { 287 { CPU_ID_ARM2, CPU_CLASS_ARM2, "ARM2", 288 generic_steppings }, 289 { CPU_ID_ARM250, CPU_CLASS_ARM2AS, "ARM250", 290 generic_steppings }, 291 292 { CPU_ID_ARM3, CPU_CLASS_ARM3, "ARM3", 293 generic_steppings }, 294 295 { CPU_ID_ARM600, CPU_CLASS_ARM6, "ARM600", 296 generic_steppings }, 297 { CPU_ID_ARM610, CPU_CLASS_ARM6, "ARM610", 298 generic_steppings }, 299 { CPU_ID_ARM620, CPU_CLASS_ARM6, "ARM620", 300 generic_steppings }, 301 302 { CPU_ID_ARM700, CPU_CLASS_ARM7, "ARM700", 303 generic_steppings }, 304 { CPU_ID_ARM710, CPU_CLASS_ARM7, "ARM710", 305 generic_steppings }, 306 { CPU_ID_ARM7500, CPU_CLASS_ARM7, "ARM7500", 307 generic_steppings }, 308 { CPU_ID_ARM710A, CPU_CLASS_ARM7, "ARM710a", 309 generic_steppings }, 310 { CPU_ID_ARM7500FE, CPU_CLASS_ARM7, "ARM7500FE", 311 generic_steppings }, 312 { CPU_ID_ARM710T, CPU_CLASS_ARM7TDMI, "ARM710T", 313 generic_steppings }, 314 { CPU_ID_ARM720T, CPU_CLASS_ARM7TDMI, "ARM720T", 315 generic_steppings }, 316 { CPU_ID_ARM740T8K, CPU_CLASS_ARM7TDMI, "ARM740T (8 KB cache)", 317 generic_steppings }, 318 { CPU_ID_ARM740T4K, CPU_CLASS_ARM7TDMI, "ARM740T (4 KB cache)", 319 generic_steppings }, 320 321 { CPU_ID_ARM810, CPU_CLASS_ARM8, "ARM810", 322 generic_steppings }, 323 324 { CPU_ID_ARM920T, CPU_CLASS_ARM9TDMI, "ARM920T", 325 generic_steppings }, 326 { CPU_ID_ARM922T, CPU_CLASS_ARM9TDMI, "ARM922T", 327 generic_steppings }, 328 { CPU_ID_ARM926EJS, CPU_CLASS_ARM9EJS, "ARM926EJ-S", 329 generic_steppings }, 330 { CPU_ID_ARM940T, CPU_CLASS_ARM9TDMI, "ARM940T", 331 generic_steppings }, 332 { CPU_ID_ARM946ES, CPU_CLASS_ARM9ES, "ARM946E-S", 333 generic_steppings }, 334 { CPU_ID_ARM966ES, CPU_CLASS_ARM9ES, "ARM966E-S", 335 generic_steppings }, 336 { CPU_ID_ARM966ESR1, CPU_CLASS_ARM9ES, "ARM966E-S", 337 generic_steppings }, 338 { CPU_ID_TI925T, CPU_CLASS_ARM9TDMI, "TI ARM925T", 339 generic_steppings }, 340 341 { CPU_ID_ARM1020E, CPU_CLASS_ARM10E, "ARM1020E", 342 generic_steppings }, 343 { CPU_ID_ARM1022ES, CPU_CLASS_ARM10E, "ARM1022E-S", 344 generic_steppings }, 345 { CPU_ID_ARM1026EJS, CPU_CLASS_ARM10EJ, "ARM1026EJ-S", 346 generic_steppings }, 347 348 { CPU_ID_SA110, CPU_CLASS_SA1, "SA-110", 349 sa110_steppings }, 350 { CPU_ID_SA1100, CPU_CLASS_SA1, "SA-1100", 351 sa1100_steppings }, 352 { CPU_ID_SA1110, CPU_CLASS_SA1, "SA-1110", 353 sa1110_steppings }, 354 355 { CPU_ID_IXP1200, CPU_CLASS_SA1, "IXP1200", 356 ixp12x0_steppings }, 357 358 { CPU_ID_80200, CPU_CLASS_XSCALE, "i80200", 359 xscale_steppings }, 360 361 { CPU_ID_80321_400, CPU_CLASS_XSCALE, "i80321 400MHz", 362 i80321_steppings }, 363 { CPU_ID_80321_600, CPU_CLASS_XSCALE, "i80321 600MHz", 364 i80321_steppings }, 365 { CPU_ID_80321_400_B0, CPU_CLASS_XSCALE, "i80321 400MHz", 366 i80321_steppings }, 367 { CPU_ID_80321_600_B0, CPU_CLASS_XSCALE, "i80321 600MHz", 368 i80321_steppings }, 369 370 { CPU_ID_80219_400, CPU_CLASS_XSCALE, "i80219 400MHz", 371 i80219_steppings }, 372 { CPU_ID_80219_600, CPU_CLASS_XSCALE, "i80219 600MHz", 373 i80219_steppings }, 374 375 { CPU_ID_PXA27X, CPU_CLASS_XSCALE, "PXA27x", 376 pxa27x_steppings }, 377 { CPU_ID_PXA250A, CPU_CLASS_XSCALE, "PXA250", 378 pxa2x0_steppings }, 379 { CPU_ID_PXA210A, CPU_CLASS_XSCALE, "PXA210", 380 pxa2x0_steppings }, 381 { CPU_ID_PXA250B, CPU_CLASS_XSCALE, "PXA250", 382 pxa2x0_steppings }, 383 { CPU_ID_PXA210B, CPU_CLASS_XSCALE, "PXA210", 384 pxa2x0_steppings }, 385 { CPU_ID_PXA250C, CPU_CLASS_XSCALE, "PXA255/26x", 386 pxa255_steppings }, 387 { CPU_ID_PXA210C, CPU_CLASS_XSCALE, "PXA210", 388 pxa2x0_steppings }, 389 390 { CPU_ID_IXP425_533, CPU_CLASS_XSCALE, "IXP425 533MHz", 391 ixp425_steppings }, 392 { CPU_ID_IXP425_400, CPU_CLASS_XSCALE, "IXP425 400MHz", 393 ixp425_steppings }, 394 { CPU_ID_IXP425_266, CPU_CLASS_XSCALE, "IXP425 266MHz", 395 ixp425_steppings }, 396 397 { CPU_ID_ARM1136JS, CPU_CLASS_ARM11J, "ARM1136J-S", 398 generic_steppings }, 399 { CPU_ID_ARM1136JSR1, CPU_CLASS_ARM11J, "ARM1136J-S R1", 400 generic_steppings }, 401 402 { 0, CPU_CLASS_NONE, NULL, NULL } 403 }; 404 405 struct cpu_classtab { 406 const char *class_name; 407 const char *class_option; 408 }; 409 410 const struct cpu_classtab cpu_classes[] = { 411 { "unknown", NULL }, /* CPU_CLASS_NONE */ 412 { "ARM2", "CPU_ARM2" }, /* CPU_CLASS_ARM2 */ 413 { "ARM2as", "CPU_ARM250" }, /* CPU_CLASS_ARM2AS */ 414 { "ARM3", "CPU_ARM3" }, /* CPU_CLASS_ARM3 */ 415 { "ARM6", "CPU_ARM6" }, /* CPU_CLASS_ARM6 */ 416 { "ARM7", "CPU_ARM7" }, /* CPU_CLASS_ARM7 */ 417 { "ARM7TDMI", "CPU_ARM7TDMI" }, /* CPU_CLASS_ARM7TDMI */ 418 { "ARM8", "CPU_ARM8" }, /* CPU_CLASS_ARM8 */ 419 { "ARM9TDMI", NULL }, /* CPU_CLASS_ARM9TDMI */ 420 { "ARM9E-S", "CPU_ARM9E" }, /* CPU_CLASS_ARM9ES */ 421 { "ARM9EJ-S", "CPU_ARM9E" }, /* CPU_CLASS_ARM9EJS */ 422 { "ARM10E", "CPU_ARM10" }, /* CPU_CLASS_ARM10E */ 423 { "ARM10EJ", "CPU_ARM10" }, /* CPU_CLASS_ARM10EJ */ 424 { "SA-1", "CPU_SA110" }, /* CPU_CLASS_SA1 */ 425 { "XScale", "CPU_XSCALE_..." }, /* CPU_CLASS_XSCALE */ 426 { "ARM11J", "CPU_ARM11" }, /* CPU_CLASS_ARM11J */ 427 }; 428 429 /* 430 * Report the type of the specified arm processor. This uses the generic and 431 * arm specific information in the CPU structure to identify the processor. 432 * The remaining fields in the CPU structure are filled in appropriately. 433 */ 434 435 static const char * const wtnames[] = { 436 "write-through", 437 "write-back", 438 "write-back", 439 "**unknown 3**", 440 "**unknown 4**", 441 "write-back-locking", /* XXX XScale-specific? */ 442 "write-back-locking-A", 443 "write-back-locking-B", 444 "**unknown 8**", 445 "**unknown 9**", 446 "**unknown 10**", 447 "**unknown 11**", 448 "**unknown 12**", 449 "**unknown 13**", 450 "write-back-locking-C", 451 "**unknown 15**", 452 }; 453 454 void 455 identify_arm_cpu(struct device *dv, struct cpu_info *ci) 456 { 457 u_int cpuid; 458 enum cpu_class cpu_class = CPU_CLASS_NONE; 459 int i; 460 461 cpuid = ci->ci_arm_cpuid; 462 463 if (cpuid == 0) { 464 aprint_error("Processor failed probe - no CPU ID\n"); 465 return; 466 } 467 468 for (i = 0; cpuids[i].cpuid != 0; i++) 469 if (cpuids[i].cpuid == (cpuid & CPU_ID_CPU_MASK)) { 470 cpu_class = cpuids[i].cpu_class; 471 sprintf(cpu_model, "%s %s (%s core)", 472 cpuids[i].cpu_name, 473 cpuids[i].cpu_steppings[cpuid & 474 CPU_ID_REVISION_MASK], 475 cpu_classes[cpu_class].class_name); 476 break; 477 } 478 479 if (cpuids[i].cpuid == 0) 480 sprintf(cpu_model, "unknown CPU (ID = 0x%x)", cpuid); 481 482 aprint_naive(": %s\n", cpu_model); 483 aprint_normal(": %s\n", cpu_model); 484 485 aprint_normal("%s:", dv->dv_xname); 486 487 switch (cpu_class) { 488 case CPU_CLASS_ARM6: 489 case CPU_CLASS_ARM7: 490 case CPU_CLASS_ARM7TDMI: 491 case CPU_CLASS_ARM8: 492 if ((ci->ci_ctrl & CPU_CONTROL_IDC_ENABLE) == 0) 493 aprint_normal(" IDC disabled"); 494 else 495 aprint_normal(" IDC enabled"); 496 break; 497 case CPU_CLASS_ARM9TDMI: 498 case CPU_CLASS_ARM9ES: 499 case CPU_CLASS_ARM9EJS: 500 case CPU_CLASS_ARM10E: 501 case CPU_CLASS_ARM10EJ: 502 case CPU_CLASS_SA1: 503 case CPU_CLASS_XSCALE: 504 case CPU_CLASS_ARM11J: 505 if ((ci->ci_ctrl & CPU_CONTROL_DC_ENABLE) == 0) 506 aprint_normal(" DC disabled"); 507 else 508 aprint_normal(" DC enabled"); 509 if ((ci->ci_ctrl & CPU_CONTROL_IC_ENABLE) == 0) 510 aprint_normal(" IC disabled"); 511 else 512 aprint_normal(" IC enabled"); 513 break; 514 default: 515 break; 516 } 517 if ((ci->ci_ctrl & CPU_CONTROL_WBUF_ENABLE) == 0) 518 aprint_normal(" WB disabled"); 519 else 520 aprint_normal(" WB enabled"); 521 522 if (ci->ci_ctrl & CPU_CONTROL_LABT_ENABLE) 523 aprint_normal(" LABT"); 524 else 525 aprint_normal(" EABT"); 526 527 if (ci->ci_ctrl & CPU_CONTROL_BPRD_ENABLE) 528 aprint_normal(" branch prediction enabled"); 529 530 aprint_normal("\n"); 531 532 /* Print cache info. */ 533 if (arm_picache_line_size == 0 && arm_pdcache_line_size == 0) 534 goto skip_pcache; 535 536 if (arm_pcache_unified) { 537 aprint_normal("%s: %dKB/%dB %d-way %s unified cache\n", 538 dv->dv_xname, arm_pdcache_size / 1024, 539 arm_pdcache_line_size, arm_pdcache_ways, 540 wtnames[arm_pcache_type]); 541 } else { 542 aprint_normal("%s: %dKB/%dB %d-way Instruction cache\n", 543 dv->dv_xname, arm_picache_size / 1024, 544 arm_picache_line_size, arm_picache_ways); 545 aprint_normal("%s: %dKB/%dB %d-way %s Data cache\n", 546 dv->dv_xname, arm_pdcache_size / 1024, 547 arm_pdcache_line_size, arm_pdcache_ways, 548 wtnames[arm_pcache_type]); 549 } 550 551 skip_pcache: 552 553 switch (cpu_class) { 554 #ifdef CPU_ARM2 555 case CPU_CLASS_ARM2: 556 #endif 557 #ifdef CPU_ARM250 558 case CPU_CLASS_ARM2AS: 559 #endif 560 #ifdef CPU_ARM3 561 case CPU_CLASS_ARM3: 562 #endif 563 #ifdef CPU_ARM6 564 case CPU_CLASS_ARM6: 565 #endif 566 #ifdef CPU_ARM7 567 case CPU_CLASS_ARM7: 568 #endif 569 #ifdef CPU_ARM7TDMI 570 case CPU_CLASS_ARM7TDMI: 571 #endif 572 #ifdef CPU_ARM8 573 case CPU_CLASS_ARM8: 574 #endif 575 #ifdef CPU_ARM9 576 case CPU_CLASS_ARM9TDMI: 577 #endif 578 #ifdef CPU_ARM9E 579 case CPU_CLASS_ARM9ES: 580 case CPU_CLASS_ARM9EJS: 581 #endif 582 #ifdef CPU_ARM10 583 case CPU_CLASS_ARM10E: 584 case CPU_CLASS_ARM10EJ: 585 #endif 586 #if defined(CPU_SA110) || defined(CPU_SA1100) || \ 587 defined(CPU_SA1110) || defined(CPU_IXP12X0) 588 case CPU_CLASS_SA1: 589 #endif 590 #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 591 defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425) 592 case CPU_CLASS_XSCALE: 593 #endif 594 #ifdef CPU_ARM11 595 case CPU_CLASS_ARM11J: 596 #endif 597 break; 598 default: 599 if (cpu_classes[cpu_class].class_option == NULL) 600 aprint_error("%s: %s does not fully support this CPU." 601 "\n", dv->dv_xname, ostype); 602 else { 603 aprint_error("%s: This kernel does not fully support " 604 "this CPU.\n", dv->dv_xname); 605 aprint_normal("%s: Recompile with \"options %s\" to " 606 "correct this.\n", dv->dv_xname, 607 cpu_classes[cpu_class].class_option); 608 } 609 break; 610 } 611 612 } 613 614 /* End of cpu.c */ 615
Indexes created Sat Sep 27 14:09:57 GMT 2025