cpu.c revision 1.68
1 /* $NetBSD: cpu.c,v 1.68 2008/04/27 18:58:43 matt Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Mark Brinicombe. 5 * Copyright (c) 1995 Brini. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Brini. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * cpu.c 38 * 39 * Probing and configuration for the master CPU 40 * 41 * Created : 10/10/95 42 */ 43 44 #include "opt_armfpe.h" 45 #include "opt_multiprocessor.h" 46 47 #include <sys/param.h> 48 49 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.68 2008/04/27 18:58:43 matt Exp $"); 50 51 #include <sys/systm.h> 52 #include <sys/malloc.h> 53 #include <sys/device.h> 54 #include <sys/proc.h> 55 #include <sys/conf.h> 56 #include <uvm/uvm_extern.h> 57 #include <machine/cpu.h> 58 59 #include <arm/cpuconf.h> 60 #include <arm/undefined.h> 61 62 #ifdef ARMFPE 63 #include <machine/bootconfig.h> /* For boot args */ 64 #include <arm/fpe-arm/armfpe.h> 65 #endif 66 67 #ifdef FPU_VFP 68 #include <arm/vfpvar.h> 69 #endif 70 71 char cpu_model[256]; 72 73 /* Prototypes */ 74 void identify_arm_cpu(struct device *dv, struct cpu_info *); 75 76 /* 77 * Identify the master (boot) CPU 78 */ 79 80 void 81 cpu_attach(struct device *dv) 82 { 83 int usearmfpe; 84 85 usearmfpe = 1; /* when compiled in, its enabled by default */ 86 87 curcpu()->ci_dev = dv; 88 89 evcnt_attach_dynamic(&curcpu()->ci_arm700bugcount, EVCNT_TYPE_MISC, 90 NULL, dv->dv_xname, "arm700swibug"); 91 92 /* Get the CPU ID from coprocessor 15 */ 93 94 curcpu()->ci_arm_cpuid = cpu_id(); 95 curcpu()->ci_arm_cputype = curcpu()->ci_arm_cpuid & CPU_ID_CPU_MASK; 96 curcpu()->ci_arm_cpurev = 97 curcpu()->ci_arm_cpuid & CPU_ID_REVISION_MASK; 98 99 identify_arm_cpu(dv, curcpu()); 100 101 if (curcpu()->ci_arm_cputype == CPU_ID_SA110 && 102 curcpu()->ci_arm_cpurev < 3) { 103 aprint_normal("%s: SA-110 with bugged STM^ instruction\n", 104 dv->dv_xname); 105 } 106 107 #ifdef CPU_ARM8 108 if ((curcpu()->ci_arm_cpuid & CPU_ID_CPU_MASK) == CPU_ID_ARM810) { 109 int clock = arm8_clock_config(0, 0); 110 char *fclk; 111 aprint_normal("%s: ARM810 cp15=%02x", dv->dv_xname, clock); 112 aprint_normal(" clock:%s", (clock & 1) ? " dynamic" : ""); 113 aprint_normal("%s", (clock & 2) ? " sync" : ""); 114 switch ((clock >> 2) & 3) { 115 case 0: 116 fclk = "bus clock"; 117 break; 118 case 1: 119 fclk = "ref clock"; 120 break; 121 case 3: 122 fclk = "pll"; 123 break; 124 default: 125 fclk = "illegal"; 126 break; 127 } 128 aprint_normal(" fclk source=%s\n", fclk); 129 } 130 #endif 131 132 #ifdef ARMFPE 133 /* 134 * Ok now we test for an FPA 135 * At this point no floating point emulator has been installed. 136 * This means any FP instruction will cause undefined exception. 137 * We install a temporay coproc 1 handler which will modify 138 * undefined_test if it is called. 139 * We then try to read the FP status register. If undefined_test 140 * has been decremented then the instruction was not handled by 141 * an FPA so we know the FPA is missing. If undefined_test is 142 * still 1 then we know the instruction was handled by an FPA. 143 * We then remove our test handler and look at the 144 * FP status register for identification. 145 */ 146 147 /* 148 * Ok if ARMFPE is defined and the boot options request the 149 * ARM FPE then it will be installed as the FPE. 150 * This is just while I work on integrating the new FPE. 151 * It means the new FPE gets installed if compiled int (ARMFPE 152 * defined) and also gives me a on/off option when I boot in 153 * case the new FPE is causing panics. 154 */ 155 156 157 if (boot_args) 158 get_bootconf_option(boot_args, "armfpe", 159 BOOTOPT_TYPE_BOOLEAN, &usearmfpe); 160 if (usearmfpe) 161 initialise_arm_fpe(); 162 #endif 163 164 #ifdef FPU_VFP 165 vfp_attach(); 166 #endif 167 } 168 169 enum cpu_class { 170 CPU_CLASS_NONE, 171 CPU_CLASS_ARM2, 172 CPU_CLASS_ARM2AS, 173 CPU_CLASS_ARM3, 174 CPU_CLASS_ARM6, 175 CPU_CLASS_ARM7, 176 CPU_CLASS_ARM7TDMI, 177 CPU_CLASS_ARM8, 178 CPU_CLASS_ARM9TDMI, 179 CPU_CLASS_ARM9ES, 180 CPU_CLASS_ARM9EJS, 181 CPU_CLASS_ARM10E, 182 CPU_CLASS_ARM10EJ, 183 CPU_CLASS_SA1, 184 CPU_CLASS_XSCALE, 185 CPU_CLASS_ARM11J 186 }; 187 188 static const char * const generic_steppings[16] = { 189 "rev 0", "rev 1", "rev 2", "rev 3", 190 "rev 4", "rev 5", "rev 6", "rev 7", 191 "rev 8", "rev 9", "rev 10", "rev 11", 192 "rev 12", "rev 13", "rev 14", "rev 15", 193 }; 194 195 static const char * const pN_steppings[16] = { 196 "*p0", "*p1", "*p2", "*p3", "*p4", "*p5", "*p6", "*p7", 197 "*p8", "*p9", "*p10", "*p11", "*p12", "*p13", "*p14", "*p15", 198 }; 199 200 static const char * const sa110_steppings[16] = { 201 "rev 0", "step J", "step K", "step S", 202 "step T", "rev 5", "rev 6", "rev 7", 203 "rev 8", "rev 9", "rev 10", "rev 11", 204 "rev 12", "rev 13", "rev 14", "rev 15", 205 }; 206 207 static const char * const sa1100_steppings[16] = { 208 "rev 0", "step B", "step C", "rev 3", 209 "rev 4", "rev 5", "rev 6", "rev 7", 210 "step D", "step E", "rev 10" "step G", 211 "rev 12", "rev 13", "rev 14", "rev 15", 212 }; 213 214 static const char * const sa1110_steppings[16] = { 215 "step A-0", "rev 1", "rev 2", "rev 3", 216 "step B-0", "step B-1", "step B-2", "step B-3", 217 "step B-4", "step B-5", "rev 10", "rev 11", 218 "rev 12", "rev 13", "rev 14", "rev 15", 219 }; 220 221 static const char * const ixp12x0_steppings[16] = { 222 "(IXP1200 step A)", "(IXP1200 step B)", 223 "rev 2", "(IXP1200 step C)", 224 "(IXP1200 step D)", "(IXP1240/1250 step A)", 225 "(IXP1240 step B)", "(IXP1250 step B)", 226 "rev 8", "rev 9", "rev 10", "rev 11", 227 "rev 12", "rev 13", "rev 14", "rev 15", 228 }; 229 230 static const char * const xscale_steppings[16] = { 231 "step A-0", "step A-1", "step B-0", "step C-0", 232 "step D-0", "rev 5", "rev 6", "rev 7", 233 "rev 8", "rev 9", "rev 10", "rev 11", 234 "rev 12", "rev 13", "rev 14", "rev 15", 235 }; 236 237 static const char * const i80321_steppings[16] = { 238 "step A-0", "step B-0", "rev 2", "rev 3", 239 "rev 4", "rev 5", "rev 6", "rev 7", 240 "rev 8", "rev 9", "rev 10", "rev 11", 241 "rev 12", "rev 13", "rev 14", "rev 15", 242 }; 243 244 static const char * const i80219_steppings[16] = { 245 "step A-0", "rev 1", "rev 2", "rev 3", 246 "rev 4", "rev 5", "rev 6", "rev 7", 247 "rev 8", "rev 9", "rev 10", "rev 11", 248 "rev 12", "rev 13", "rev 14", "rev 15", 249 }; 250 251 /* Steppings for PXA2[15]0 */ 252 static const char * const pxa2x0_steppings[16] = { 253 "step A-0", "step A-1", "step B-0", "step B-1", 254 "step B-2", "step C-0", "rev 6", "rev 7", 255 "rev 8", "rev 9", "rev 10", "rev 11", 256 "rev 12", "rev 13", "rev 14", "rev 15", 257 }; 258 259 /* Steppings for PXA255/26x. 260 * rev 5: PXA26x B0, rev 6: PXA255 A0 261 */ 262 static const char * const pxa255_steppings[16] = { 263 "rev 0", "rev 1", "rev 2", "step A-0", 264 "rev 4", "step B-0", "step A-0", "rev 7", 265 "rev 8", "rev 9", "rev 10", "rev 11", 266 "rev 12", "rev 13", "rev 14", "rev 15", 267 }; 268 269 /* Stepping for PXA27x */ 270 static const char * const pxa27x_steppings[16] = { 271 "step A-0", "step A-1", "step B-0", "step B-1", 272 "step C-0", "rev 5", "rev 6", "rev 7", 273 "rev 8", "rev 9", "rev 10", "rev 11", 274 "rev 12", "rev 13", "rev 14", "rev 15", 275 }; 276 277 static const char * const ixp425_steppings[16] = { 278 "step 0", "rev 1", "rev 2", "rev 3", 279 "rev 4", "rev 5", "rev 6", "rev 7", 280 "rev 8", "rev 9", "rev 10", "rev 11", 281 "rev 12", "rev 13", "rev 14", "rev 15", 282 }; 283 284 struct cpuidtab { 285 u_int32_t cpuid; 286 enum cpu_class cpu_class; 287 const char *cpu_name; 288 const char * const *cpu_steppings; 289 }; 290 291 const struct cpuidtab cpuids[] = { 292 { CPU_ID_ARM2, CPU_CLASS_ARM2, "ARM2", 293 generic_steppings }, 294 { CPU_ID_ARM250, CPU_CLASS_ARM2AS, "ARM250", 295 generic_steppings }, 296 297 { CPU_ID_ARM3, CPU_CLASS_ARM3, "ARM3", 298 generic_steppings }, 299 300 { CPU_ID_ARM600, CPU_CLASS_ARM6, "ARM600", 301 generic_steppings }, 302 { CPU_ID_ARM610, CPU_CLASS_ARM6, "ARM610", 303 generic_steppings }, 304 { CPU_ID_ARM620, CPU_CLASS_ARM6, "ARM620", 305 generic_steppings }, 306 307 { CPU_ID_ARM700, CPU_CLASS_ARM7, "ARM700", 308 generic_steppings }, 309 { CPU_ID_ARM710, CPU_CLASS_ARM7, "ARM710", 310 generic_steppings }, 311 { CPU_ID_ARM7500, CPU_CLASS_ARM7, "ARM7500", 312 generic_steppings }, 313 { CPU_ID_ARM710A, CPU_CLASS_ARM7, "ARM710a", 314 generic_steppings }, 315 { CPU_ID_ARM7500FE, CPU_CLASS_ARM7, "ARM7500FE", 316 generic_steppings }, 317 { CPU_ID_ARM710T, CPU_CLASS_ARM7TDMI, "ARM710T", 318 generic_steppings }, 319 { CPU_ID_ARM720T, CPU_CLASS_ARM7TDMI, "ARM720T", 320 generic_steppings }, 321 { CPU_ID_ARM740T8K, CPU_CLASS_ARM7TDMI, "ARM740T (8 KB cache)", 322 generic_steppings }, 323 { CPU_ID_ARM740T4K, CPU_CLASS_ARM7TDMI, "ARM740T (4 KB cache)", 324 generic_steppings }, 325 326 { CPU_ID_ARM810, CPU_CLASS_ARM8, "ARM810", 327 generic_steppings }, 328 329 { CPU_ID_ARM920T, CPU_CLASS_ARM9TDMI, "ARM920T", 330 generic_steppings }, 331 { CPU_ID_ARM922T, CPU_CLASS_ARM9TDMI, "ARM922T", 332 generic_steppings }, 333 { CPU_ID_ARM926EJS, CPU_CLASS_ARM9EJS, "ARM926EJ-S", 334 generic_steppings }, 335 { CPU_ID_ARM940T, CPU_CLASS_ARM9TDMI, "ARM940T", 336 generic_steppings }, 337 { CPU_ID_ARM946ES, CPU_CLASS_ARM9ES, "ARM946E-S", 338 generic_steppings }, 339 { CPU_ID_ARM966ES, CPU_CLASS_ARM9ES, "ARM966E-S", 340 generic_steppings }, 341 { CPU_ID_ARM966ESR1, CPU_CLASS_ARM9ES, "ARM966E-S", 342 generic_steppings }, 343 { CPU_ID_TI925T, CPU_CLASS_ARM9TDMI, "TI ARM925T", 344 generic_steppings }, 345 346 { CPU_ID_ARM1020E, CPU_CLASS_ARM10E, "ARM1020E", 347 generic_steppings }, 348 { CPU_ID_ARM1022ES, CPU_CLASS_ARM10E, "ARM1022E-S", 349 generic_steppings }, 350 { CPU_ID_ARM1026EJS, CPU_CLASS_ARM10EJ, "ARM1026EJ-S", 351 generic_steppings }, 352 353 { CPU_ID_SA110, CPU_CLASS_SA1, "SA-110", 354 sa110_steppings }, 355 { CPU_ID_SA1100, CPU_CLASS_SA1, "SA-1100", 356 sa1100_steppings }, 357 { CPU_ID_SA1110, CPU_CLASS_SA1, "SA-1110", 358 sa1110_steppings }, 359 360 { CPU_ID_IXP1200, CPU_CLASS_SA1, "IXP1200", 361 ixp12x0_steppings }, 362 363 { CPU_ID_80200, CPU_CLASS_XSCALE, "i80200", 364 xscale_steppings }, 365 366 { CPU_ID_80321_400, CPU_CLASS_XSCALE, "i80321 400MHz", 367 i80321_steppings }, 368 { CPU_ID_80321_600, CPU_CLASS_XSCALE, "i80321 600MHz", 369 i80321_steppings }, 370 { CPU_ID_80321_400_B0, CPU_CLASS_XSCALE, "i80321 400MHz", 371 i80321_steppings }, 372 { CPU_ID_80321_600_B0, CPU_CLASS_XSCALE, "i80321 600MHz", 373 i80321_steppings }, 374 375 { CPU_ID_80219_400, CPU_CLASS_XSCALE, "i80219 400MHz", 376 i80219_steppings }, 377 { CPU_ID_80219_600, CPU_CLASS_XSCALE, "i80219 600MHz", 378 i80219_steppings }, 379 380 { CPU_ID_PXA27X, CPU_CLASS_XSCALE, "PXA27x", 381 pxa27x_steppings }, 382 { CPU_ID_PXA250A, CPU_CLASS_XSCALE, "PXA250", 383 pxa2x0_steppings }, 384 { CPU_ID_PXA210A, CPU_CLASS_XSCALE, "PXA210", 385 pxa2x0_steppings }, 386 { CPU_ID_PXA250B, CPU_CLASS_XSCALE, "PXA250", 387 pxa2x0_steppings }, 388 { CPU_ID_PXA210B, CPU_CLASS_XSCALE, "PXA210", 389 pxa2x0_steppings }, 390 { CPU_ID_PXA250C, CPU_CLASS_XSCALE, "PXA255/26x", 391 pxa255_steppings }, 392 { CPU_ID_PXA210C, CPU_CLASS_XSCALE, "PXA210", 393 pxa2x0_steppings }, 394 395 { CPU_ID_IXP425_533, CPU_CLASS_XSCALE, "IXP425 533MHz", 396 ixp425_steppings }, 397 { CPU_ID_IXP425_400, CPU_CLASS_XSCALE, "IXP425 400MHz", 398 ixp425_steppings }, 399 { CPU_ID_IXP425_266, CPU_CLASS_XSCALE, "IXP425 266MHz", 400 ixp425_steppings }, 401 402 { CPU_ID_ARM1136JS, CPU_CLASS_ARM11J, "ARM1136J-S r0", 403 pN_steppings }, 404 { CPU_ID_ARM1136JSR1, CPU_CLASS_ARM11J, "ARM1136J-S r1", 405 pN_steppings }, 406 { CPU_ID_ARM1176JS, CPU_CLASS_ARM11J, "ARM1176J-S r0", 407 pN_steppings }, 408 409 { 0, CPU_CLASS_NONE, NULL, NULL } 410 }; 411 412 struct cpu_classtab { 413 const char *class_name; 414 const char *class_option; 415 }; 416 417 const struct cpu_classtab cpu_classes[] = { 418 { "unknown", NULL }, /* CPU_CLASS_NONE */ 419 { "ARM2", "CPU_ARM2" }, /* CPU_CLASS_ARM2 */ 420 { "ARM2as", "CPU_ARM250" }, /* CPU_CLASS_ARM2AS */ 421 { "ARM3", "CPU_ARM3" }, /* CPU_CLASS_ARM3 */ 422 { "ARM6", "CPU_ARM6" }, /* CPU_CLASS_ARM6 */ 423 { "ARM7", "CPU_ARM7" }, /* CPU_CLASS_ARM7 */ 424 { "ARM7TDMI", "CPU_ARM7TDMI" }, /* CPU_CLASS_ARM7TDMI */ 425 { "ARM8", "CPU_ARM8" }, /* CPU_CLASS_ARM8 */ 426 { "ARM9TDMI", NULL }, /* CPU_CLASS_ARM9TDMI */ 427 { "ARM9E-S", "CPU_ARM9E" }, /* CPU_CLASS_ARM9ES */ 428 { "ARM9EJ-S", "CPU_ARM9E" }, /* CPU_CLASS_ARM9EJS */ 429 { "ARM10E", "CPU_ARM10" }, /* CPU_CLASS_ARM10E */ 430 { "ARM10EJ", "CPU_ARM10" }, /* CPU_CLASS_ARM10EJ */ 431 { "SA-1", "CPU_SA110" }, /* CPU_CLASS_SA1 */ 432 { "XScale", "CPU_XSCALE_..." }, /* CPU_CLASS_XSCALE */ 433 { "ARM11J", "CPU_ARM11" }, /* CPU_CLASS_ARM11J */ 434 }; 435 436 /* 437 * Report the type of the specified arm processor. This uses the generic and 438 * arm specific information in the CPU structure to identify the processor. 439 * The remaining fields in the CPU structure are filled in appropriately. 440 */ 441 442 static const char * const wtnames[] = { 443 "write-through", 444 "write-back", 445 "write-back", 446 "**unknown 3**", 447 "**unknown 4**", 448 "write-back-locking", /* XXX XScale-specific? */ 449 "write-back-locking-A", 450 "write-back-locking-B", 451 "**unknown 8**", 452 "**unknown 9**", 453 "**unknown 10**", 454 "**unknown 11**", 455 "**unknown 12**", 456 "**unknown 13**", 457 "write-back-locking-C", 458 "**unknown 15**", 459 }; 460 461 void 462 identify_arm_cpu(struct device *dv, struct cpu_info *ci) 463 { 464 u_int cpuid; 465 enum cpu_class cpu_class = CPU_CLASS_NONE; 466 int i; 467 const char *steppingstr; 468 469 cpuid = ci->ci_arm_cpuid; 470 471 if (cpuid == 0) { 472 aprint_error("Processor failed probe - no CPU ID\n"); 473 return; 474 } 475 476 for (i = 0; cpuids[i].cpuid != 0; i++) 477 if (cpuids[i].cpuid == (cpuid & CPU_ID_CPU_MASK)) { 478 cpu_class = cpuids[i].cpu_class; 479 steppingstr = cpuids[i].cpu_steppings[cpuid & 480 CPU_ID_REVISION_MASK], 481 sprintf(cpu_model, "%s%s%s (%s core)", 482 cpuids[i].cpu_name, 483 steppingstr[0] == '*' ? "" : " ", 484 &steppingstr[steppingstr[0] == '*'], 485 cpu_classes[cpu_class].class_name); 486 break; 487 } 488 489 if (cpuids[i].cpuid == 0) 490 sprintf(cpu_model, "unknown CPU (ID = 0x%x)", cpuid); 491 492 aprint_naive(": %s\n", cpu_model); 493 aprint_normal(": %s\n", cpu_model); 494 495 aprint_normal("%s:", dv->dv_xname); 496 497 switch (cpu_class) { 498 case CPU_CLASS_ARM6: 499 case CPU_CLASS_ARM7: 500 case CPU_CLASS_ARM7TDMI: 501 case CPU_CLASS_ARM8: 502 if ((ci->ci_ctrl & CPU_CONTROL_IDC_ENABLE) == 0) 503 aprint_normal(" IDC disabled"); 504 else 505 aprint_normal(" IDC enabled"); 506 break; 507 case CPU_CLASS_ARM9TDMI: 508 case CPU_CLASS_ARM9ES: 509 case CPU_CLASS_ARM9EJS: 510 case CPU_CLASS_ARM10E: 511 case CPU_CLASS_ARM10EJ: 512 case CPU_CLASS_SA1: 513 case CPU_CLASS_XSCALE: 514 case CPU_CLASS_ARM11J: 515 if ((ci->ci_ctrl & CPU_CONTROL_DC_ENABLE) == 0) 516 aprint_normal(" DC disabled"); 517 else 518 aprint_normal(" DC enabled"); 519 if ((ci->ci_ctrl & CPU_CONTROL_IC_ENABLE) == 0) 520 aprint_normal(" IC disabled"); 521 else 522 aprint_normal(" IC enabled"); 523 break; 524 default: 525 break; 526 } 527 if ((ci->ci_ctrl & CPU_CONTROL_WBUF_ENABLE) == 0) 528 aprint_normal(" WB disabled"); 529 else 530 aprint_normal(" WB enabled"); 531 532 if (ci->ci_ctrl & CPU_CONTROL_LABT_ENABLE) 533 aprint_normal(" LABT"); 534 else 535 aprint_normal(" EABT"); 536 537 if (ci->ci_ctrl & CPU_CONTROL_BPRD_ENABLE) 538 aprint_normal(" branch prediction enabled"); 539 540 aprint_normal("\n"); 541 542 /* Print cache info. */ 543 if (arm_picache_line_size == 0 && arm_pdcache_line_size == 0) 544 goto skip_pcache; 545 546 if (arm_pcache_unified) { 547 aprint_normal("%s: %dKB/%dB %d-way %s unified cache\n", 548 dv->dv_xname, arm_pdcache_size / 1024, 549 arm_pdcache_line_size, arm_pdcache_ways, 550 wtnames[arm_pcache_type]); 551 } else { 552 aprint_normal("%s: %dKB/%dB %d-way Instruction cache\n", 553 dv->dv_xname, arm_picache_size / 1024, 554 arm_picache_line_size, arm_picache_ways); 555 aprint_normal("%s: %dKB/%dB %d-way %s Data cache\n", 556 dv->dv_xname, arm_pdcache_size / 1024, 557 arm_pdcache_line_size, arm_pdcache_ways, 558 wtnames[arm_pcache_type]); 559 } 560 561 skip_pcache: 562 563 switch (cpu_class) { 564 #ifdef CPU_ARM2 565 case CPU_CLASS_ARM2: 566 #endif 567 #ifdef CPU_ARM250 568 case CPU_CLASS_ARM2AS: 569 #endif 570 #ifdef CPU_ARM3 571 case CPU_CLASS_ARM3: 572 #endif 573 #ifdef CPU_ARM6 574 case CPU_CLASS_ARM6: 575 #endif 576 #ifdef CPU_ARM7 577 case CPU_CLASS_ARM7: 578 #endif 579 #ifdef CPU_ARM7TDMI 580 case CPU_CLASS_ARM7TDMI: 581 #endif 582 #ifdef CPU_ARM8 583 case CPU_CLASS_ARM8: 584 #endif 585 #ifdef CPU_ARM9 586 case CPU_CLASS_ARM9TDMI: 587 #endif 588 #ifdef CPU_ARM9E 589 case CPU_CLASS_ARM9ES: 590 case CPU_CLASS_ARM9EJS: 591 #endif 592 #ifdef CPU_ARM10 593 case CPU_CLASS_ARM10E: 594 case CPU_CLASS_ARM10EJ: 595 #endif 596 #if defined(CPU_SA110) || defined(CPU_SA1100) || \ 597 defined(CPU_SA1110) || defined(CPU_IXP12X0) 598 case CPU_CLASS_SA1: 599 #endif 600 #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 601 defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425) 602 case CPU_CLASS_XSCALE: 603 #endif 604 #if defined(CPU_ARM11) 605 case CPU_CLASS_ARM11J: 606 #endif 607 break; 608 default: 609 if (cpu_classes[cpu_class].class_option == NULL) 610 aprint_error("%s: %s does not fully support this CPU." 611 "\n", dv->dv_xname, ostype); 612 else { 613 aprint_error("%s: This kernel does not fully support " 614 "this CPU.\n", dv->dv_xname); 615 aprint_normal("%s: Recompile with \"options %s\" to " 616 "correct this.\n", dv->dv_xname, 617 cpu_classes[cpu_class].class_option); 618 } 619 break; 620 } 621 622 } 623 624 /* End of cpu.c */ 625
Indexes created Thu Sep 25 06:09:39 GMT 2025