cpu.c revision 1.71.12.1
1 /* $NetBSD: cpu.c,v 1.71.12.1 2014/02/15 16:18:36 matt Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Mark Brinicombe. 5 * Copyright (c) 1995 Brini. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Brini. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * cpu.c 38 * 39 * Probing and configuration for the master CPU 40 * 41 * Created : 10/10/95 42 */ 43 44 #include "opt_armfpe.h" 45 #include "opt_multiprocessor.h" 46 47 #include <sys/param.h> 48 49 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.71.12.1 2014/02/15 16:18:36 matt Exp $"); 50 51 #include <sys/systm.h> 52 #include <sys/conf.h> 53 #include <sys/cpu.h> 54 #include <sys/device.h> 55 #include <sys/kmem.h> 56 #include <sys/proc.h> 57 58 #include <uvm/uvm_extern.h> 59 60 #include <arm/locore.h> 61 #include <arm/undefined.h> 62 63 char cpu_model[256]; 64 extern const char *cpu_arch; 65 66 #ifdef MULTIPROCESSOR 67 volatile u_int arm_cpu_hatched = 0; 68 u_int arm_cpu_max = 0; 69 uint32_t arm_cpu_mbox __cacheline_aligned = 0; 70 uint32_t arm_cpu_marker __cacheline_aligned = 1; 71 #endif 72 73 /* Prototypes */ 74 void identify_arm_cpu(device_t dv, struct cpu_info *); 75 void identify_cortex_caches(device_t dv); 76 void identify_features(device_t dv); 77 78 /* 79 * Identify the master (boot) CPU 80 */ 81 82 void 83 cpu_attach(device_t dv, cpuid_t id) 84 { 85 const char * const xname = device_xname(dv); 86 struct cpu_info *ci; 87 88 if (id == 0) { 89 ci = curcpu(); 90 91 /* Get the CPU ID from coprocessor 15 */ 92 93 ci->ci_arm_cpuid = cpu_id(); 94 ci->ci_arm_cputype = ci->ci_arm_cpuid & CPU_ID_CPU_MASK; 95 ci->ci_arm_cpurev = ci->ci_arm_cpuid & CPU_ID_REVISION_MASK; 96 } else { 97 #ifdef MULTIPROCESSOR 98 KASSERT(cpu_info[id] == NULL); 99 ci = kmem_zalloc(sizeof(*ci), KM_SLEEP); 100 KASSERT(ci != NULL); 101 ci->ci_cpl = IPL_HIGH; 102 ci->ci_cpuid = id; 103 ci->ci_data.cpu_core_id = id; 104 ci->ci_data.cpu_cc_freq = cpu_info_store.ci_data.cpu_cc_freq; 105 ci->ci_arm_cpuid = cpu_info_store.ci_arm_cpuid; 106 ci->ci_arm_cputype = cpu_info_store.ci_arm_cputype; 107 ci->ci_arm_cpurev = cpu_info_store.ci_arm_cpurev; 108 cpu_info[ci->ci_cpuid] = ci; 109 if ((arm_cpu_hatched & (1 << id)) == 0) { 110 ci->ci_dev = dv; 111 dv->dv_private = ci; 112 aprint_naive(": disabled\n"); 113 aprint_normal(": disabled (unresponsive)\n"); 114 return; 115 } 116 #else 117 aprint_naive(": disabled\n"); 118 aprint_normal(": disabled (uniprocessor kernel)\n"); 119 return; 120 #endif 121 } 122 123 ci->ci_dev = dv; 124 dv->dv_private = ci; 125 126 evcnt_attach_dynamic(&ci->ci_arm700bugcount, EVCNT_TYPE_MISC, 127 NULL, xname, "arm700swibug"); 128 129 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_WRTBUF_0], EVCNT_TYPE_TRAP, 130 NULL, xname, "vector abort"); 131 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_WRTBUF_1], EVCNT_TYPE_TRAP, 132 NULL, xname, "terminal abort"); 133 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_BUSERR_0], EVCNT_TYPE_TRAP, 134 NULL, xname, "external linefetch abort (S)"); 135 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_BUSERR_1], EVCNT_TYPE_TRAP, 136 NULL, xname, "external linefetch abort (P)"); 137 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_BUSERR_2], EVCNT_TYPE_TRAP, 138 NULL, xname, "external non-linefetch abort (S)"); 139 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_BUSERR_3], EVCNT_TYPE_TRAP, 140 NULL, xname, "external non-linefetch abort (P)"); 141 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_BUSTRNL1], EVCNT_TYPE_TRAP, 142 NULL, xname, "external translation abort (L1)"); 143 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_BUSTRNL2], EVCNT_TYPE_TRAP, 144 NULL, xname, "external translation abort (L2)"); 145 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_ALIGN_0], EVCNT_TYPE_TRAP, 146 NULL, xname, "alignment abort (0)"); 147 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_ALIGN_1], EVCNT_TYPE_TRAP, 148 NULL, xname, "alignment abort (1)"); 149 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_TRANS_S], EVCNT_TYPE_TRAP, 150 NULL, xname, "translation abort (S)"); 151 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_TRANS_P], EVCNT_TYPE_TRAP, 152 NULL, xname, "translation abort (P)"); 153 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_DOMAIN_S], EVCNT_TYPE_TRAP, 154 NULL, xname, "domain abort (S)"); 155 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_DOMAIN_P], EVCNT_TYPE_TRAP, 156 NULL, xname, "domain abort (P)"); 157 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_PERM_S], EVCNT_TYPE_TRAP, 158 NULL, xname, "permission abort (S)"); 159 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_PERM_P], EVCNT_TYPE_TRAP, 160 NULL, xname, "permission abort (P)"); 161 162 #ifdef MULTIPROCESSOR 163 /* 164 * and we are done if this is a secondary processor. 165 */ 166 if (!CPU_IS_PRIMARY(ci)) { 167 aprint_naive(": %s\n", cpu_model); 168 aprint_normal(": %s\n", cpu_model); 169 mi_cpu_attach(ci); 170 return; 171 } 172 #endif 173 174 identify_arm_cpu(dv, ci); 175 176 #ifdef CPU_STRONGARM 177 if (ci->ci_arm_cputype == CPU_ID_SA110 && 178 ci->ci_arm_cpurev < 3) { 179 aprint_normal_dev(dv, "SA-110 with bugged STM^ instruction\n"); 180 } 181 #endif 182 183 #ifdef CPU_ARM8 184 if ((ci->ci_arm_cpuid & CPU_ID_CPU_MASK) == CPU_ID_ARM810) { 185 int clock = arm8_clock_config(0, 0); 186 char *fclk; 187 aprint_normal_dev(dv, "ARM810 cp15=%02x", clock); 188 aprint_normal(" clock:%s", (clock & 1) ? " dynamic" : ""); 189 aprint_normal("%s", (clock & 2) ? " sync" : ""); 190 switch ((clock >> 2) & 3) { 191 case 0: 192 fclk = "bus clock"; 193 break; 194 case 1: 195 fclk = "ref clock"; 196 break; 197 case 3: 198 fclk = "pll"; 199 break; 200 default: 201 fclk = "illegal"; 202 break; 203 } 204 aprint_normal(" fclk source=%s\n", fclk); 205 } 206 #endif 207 } 208 209 enum cpu_class { 210 CPU_CLASS_NONE, 211 CPU_CLASS_ARM2, 212 CPU_CLASS_ARM2AS, 213 CPU_CLASS_ARM3, 214 CPU_CLASS_ARM6, 215 CPU_CLASS_ARM7, 216 CPU_CLASS_ARM7TDMI, 217 CPU_CLASS_ARM8, 218 CPU_CLASS_ARM9TDMI, 219 CPU_CLASS_ARM9ES, 220 CPU_CLASS_ARM9EJS, 221 CPU_CLASS_ARM10E, 222 CPU_CLASS_ARM10EJ, 223 CPU_CLASS_SA1, 224 CPU_CLASS_XSCALE, 225 CPU_CLASS_ARM11J, 226 CPU_CLASS_ARMV4, 227 CPU_CLASS_CORTEX, 228 CPU_CLASS_PJ4B, 229 }; 230 231 static const char * const generic_steppings[16] = { 232 "rev 0", "rev 1", "rev 2", "rev 3", 233 "rev 4", "rev 5", "rev 6", "rev 7", 234 "rev 8", "rev 9", "rev 10", "rev 11", 235 "rev 12", "rev 13", "rev 14", "rev 15", 236 }; 237 238 static const char * const pN_steppings[16] = { 239 "*p0", "*p1", "*p2", "*p3", "*p4", "*p5", "*p6", "*p7", 240 "*p8", "*p9", "*p10", "*p11", "*p12", "*p13", "*p14", "*p15", 241 }; 242 243 static const char * const sa110_steppings[16] = { 244 "rev 0", "step J", "step K", "step S", 245 "step T", "rev 5", "rev 6", "rev 7", 246 "rev 8", "rev 9", "rev 10", "rev 11", 247 "rev 12", "rev 13", "rev 14", "rev 15", 248 }; 249 250 static const char * const sa1100_steppings[16] = { 251 "rev 0", "step B", "step C", "rev 3", 252 "rev 4", "rev 5", "rev 6", "rev 7", 253 "step D", "step E", "rev 10" "step G", 254 "rev 12", "rev 13", "rev 14", "rev 15", 255 }; 256 257 static const char * const sa1110_steppings[16] = { 258 "step A-0", "rev 1", "rev 2", "rev 3", 259 "step B-0", "step B-1", "step B-2", "step B-3", 260 "step B-4", "step B-5", "rev 10", "rev 11", 261 "rev 12", "rev 13", "rev 14", "rev 15", 262 }; 263 264 static const char * const ixp12x0_steppings[16] = { 265 "(IXP1200 step A)", "(IXP1200 step B)", 266 "rev 2", "(IXP1200 step C)", 267 "(IXP1200 step D)", "(IXP1240/1250 step A)", 268 "(IXP1240 step B)", "(IXP1250 step B)", 269 "rev 8", "rev 9", "rev 10", "rev 11", 270 "rev 12", "rev 13", "rev 14", "rev 15", 271 }; 272 273 static const char * const xscale_steppings[16] = { 274 "step A-0", "step A-1", "step B-0", "step C-0", 275 "step D-0", "rev 5", "rev 6", "rev 7", 276 "rev 8", "rev 9", "rev 10", "rev 11", 277 "rev 12", "rev 13", "rev 14", "rev 15", 278 }; 279 280 static const char * const i80321_steppings[16] = { 281 "step A-0", "step B-0", "rev 2", "rev 3", 282 "rev 4", "rev 5", "rev 6", "rev 7", 283 "rev 8", "rev 9", "rev 10", "rev 11", 284 "rev 12", "rev 13", "rev 14", "rev 15", 285 }; 286 287 static const char * const i80219_steppings[16] = { 288 "step A-0", "rev 1", "rev 2", "rev 3", 289 "rev 4", "rev 5", "rev 6", "rev 7", 290 "rev 8", "rev 9", "rev 10", "rev 11", 291 "rev 12", "rev 13", "rev 14", "rev 15", 292 }; 293 294 /* Steppings for PXA2[15]0 */ 295 static const char * const pxa2x0_steppings[16] = { 296 "step A-0", "step A-1", "step B-0", "step B-1", 297 "step B-2", "step C-0", "rev 6", "rev 7", 298 "rev 8", "rev 9", "rev 10", "rev 11", 299 "rev 12", "rev 13", "rev 14", "rev 15", 300 }; 301 302 /* Steppings for PXA255/26x. 303 * rev 5: PXA26x B0, rev 6: PXA255 A0 304 */ 305 static const char * const pxa255_steppings[16] = { 306 "rev 0", "rev 1", "rev 2", "step A-0", 307 "rev 4", "step B-0", "step A-0", "rev 7", 308 "rev 8", "rev 9", "rev 10", "rev 11", 309 "rev 12", "rev 13", "rev 14", "rev 15", 310 }; 311 312 /* Stepping for PXA27x */ 313 static const char * const pxa27x_steppings[16] = { 314 "step A-0", "step A-1", "step B-0", "step B-1", 315 "step C-0", "rev 5", "rev 6", "rev 7", 316 "rev 8", "rev 9", "rev 10", "rev 11", 317 "rev 12", "rev 13", "rev 14", "rev 15", 318 }; 319 320 static const char * const ixp425_steppings[16] = { 321 "step 0", "rev 1", "rev 2", "rev 3", 322 "rev 4", "rev 5", "rev 6", "rev 7", 323 "rev 8", "rev 9", "rev 10", "rev 11", 324 "rev 12", "rev 13", "rev 14", "rev 15", 325 }; 326 327 struct cpuidtab { 328 uint32_t cpuid; 329 enum cpu_class cpu_class; 330 const char *cpu_classname; 331 const char * const *cpu_steppings; 332 char cpu_arch[8]; 333 }; 334 335 const struct cpuidtab cpuids[] = { 336 { CPU_ID_ARM2, CPU_CLASS_ARM2, "ARM2", 337 generic_steppings, "2" }, 338 { CPU_ID_ARM250, CPU_CLASS_ARM2AS, "ARM250", 339 generic_steppings, "2" }, 340 341 { CPU_ID_ARM3, CPU_CLASS_ARM3, "ARM3", 342 generic_steppings, "2A" }, 343 344 { CPU_ID_ARM600, CPU_CLASS_ARM6, "ARM600", 345 generic_steppings, "3" }, 346 { CPU_ID_ARM610, CPU_CLASS_ARM6, "ARM610", 347 generic_steppings, "3" }, 348 { CPU_ID_ARM620, CPU_CLASS_ARM6, "ARM620", 349 generic_steppings, "3" }, 350 351 { CPU_ID_ARM700, CPU_CLASS_ARM7, "ARM700", 352 generic_steppings, "3" }, 353 { CPU_ID_ARM710, CPU_CLASS_ARM7, "ARM710", 354 generic_steppings, "3" }, 355 { CPU_ID_ARM7500, CPU_CLASS_ARM7, "ARM7500", 356 generic_steppings, "3" }, 357 { CPU_ID_ARM710A, CPU_CLASS_ARM7, "ARM710a", 358 generic_steppings, "3" }, 359 { CPU_ID_ARM7500FE, CPU_CLASS_ARM7, "ARM7500FE", 360 generic_steppings, "3" }, 361 362 { CPU_ID_ARM810, CPU_CLASS_ARM8, "ARM810", 363 generic_steppings, "4" }, 364 365 { CPU_ID_SA110, CPU_CLASS_SA1, "SA-110", 366 sa110_steppings, "4" }, 367 { CPU_ID_SA1100, CPU_CLASS_SA1, "SA-1100", 368 sa1100_steppings, "4" }, 369 { CPU_ID_SA1110, CPU_CLASS_SA1, "SA-1110", 370 sa1110_steppings, "4" }, 371 372 { CPU_ID_FA526, CPU_CLASS_ARMV4, "FA526", 373 generic_steppings, "4" }, 374 375 { CPU_ID_IXP1200, CPU_CLASS_SA1, "IXP1200", 376 ixp12x0_steppings, "4" }, 377 378 { CPU_ID_ARM710T, CPU_CLASS_ARM7TDMI, "ARM710T", 379 generic_steppings, "4T" }, 380 { CPU_ID_ARM720T, CPU_CLASS_ARM7TDMI, "ARM720T", 381 generic_steppings, "4T" }, 382 { CPU_ID_ARM740T8K, CPU_CLASS_ARM7TDMI, "ARM740T (8 KB cache)", 383 generic_steppings, "4T" }, 384 { CPU_ID_ARM740T4K, CPU_CLASS_ARM7TDMI, "ARM740T (4 KB cache)", 385 generic_steppings, "4T" }, 386 { CPU_ID_ARM920T, CPU_CLASS_ARM9TDMI, "ARM920T", 387 generic_steppings, "4T" }, 388 { CPU_ID_ARM922T, CPU_CLASS_ARM9TDMI, "ARM922T", 389 generic_steppings, "4T" }, 390 { CPU_ID_ARM940T, CPU_CLASS_ARM9TDMI, "ARM940T", 391 generic_steppings, "4T" }, 392 { CPU_ID_TI925T, CPU_CLASS_ARM9TDMI, "TI ARM925T", 393 generic_steppings, "4T" }, 394 395 { CPU_ID_ARM946ES, CPU_CLASS_ARM9ES, "ARM946E-S", 396 generic_steppings, "5TE" }, 397 { CPU_ID_ARM966ES, CPU_CLASS_ARM9ES, "ARM966E-S", 398 generic_steppings, "5TE" }, 399 { CPU_ID_ARM966ESR1, CPU_CLASS_ARM9ES, "ARM966E-S", 400 generic_steppings, "5TE" }, 401 { CPU_ID_MV88SV131, CPU_CLASS_ARM9ES, "Sheeva 88SV131", 402 generic_steppings, "5TE" }, 403 { CPU_ID_MV88FR571_VD, CPU_CLASS_ARM9ES, "Sheeva 88FR571-vd", 404 generic_steppings, "5TE" }, 405 406 { CPU_ID_80200, CPU_CLASS_XSCALE, "i80200", 407 xscale_steppings, "5TE" }, 408 409 { CPU_ID_80321_400, CPU_CLASS_XSCALE, "i80321 400MHz", 410 i80321_steppings, "5TE" }, 411 { CPU_ID_80321_600, CPU_CLASS_XSCALE, "i80321 600MHz", 412 i80321_steppings, "5TE" }, 413 { CPU_ID_80321_400_B0, CPU_CLASS_XSCALE, "i80321 400MHz", 414 i80321_steppings, "5TE" }, 415 { CPU_ID_80321_600_B0, CPU_CLASS_XSCALE, "i80321 600MHz", 416 i80321_steppings, "5TE" }, 417 418 { CPU_ID_80219_400, CPU_CLASS_XSCALE, "i80219 400MHz", 419 i80219_steppings, "5TE" }, 420 { CPU_ID_80219_600, CPU_CLASS_XSCALE, "i80219 600MHz", 421 i80219_steppings, "5TE" }, 422 423 { CPU_ID_PXA27X, CPU_CLASS_XSCALE, "PXA27x", 424 pxa27x_steppings, "5TE" }, 425 { CPU_ID_PXA250A, CPU_CLASS_XSCALE, "PXA250", 426 pxa2x0_steppings, "5TE" }, 427 { CPU_ID_PXA210A, CPU_CLASS_XSCALE, "PXA210", 428 pxa2x0_steppings, "5TE" }, 429 { CPU_ID_PXA250B, CPU_CLASS_XSCALE, "PXA250", 430 pxa2x0_steppings, "5TE" }, 431 { CPU_ID_PXA210B, CPU_CLASS_XSCALE, "PXA210", 432 pxa2x0_steppings, "5TE" }, 433 { CPU_ID_PXA250C, CPU_CLASS_XSCALE, "PXA255/26x", 434 pxa255_steppings, "5TE" }, 435 { CPU_ID_PXA210C, CPU_CLASS_XSCALE, "PXA210", 436 pxa2x0_steppings, "5TE" }, 437 438 { CPU_ID_IXP425_533, CPU_CLASS_XSCALE, "IXP425 533MHz", 439 ixp425_steppings, "5TE" }, 440 { CPU_ID_IXP425_400, CPU_CLASS_XSCALE, "IXP425 400MHz", 441 ixp425_steppings, "5TE" }, 442 { CPU_ID_IXP425_266, CPU_CLASS_XSCALE, "IXP425 266MHz", 443 ixp425_steppings, "5TE" }, 444 445 { CPU_ID_ARM1020E, CPU_CLASS_ARM10E, "ARM1020E", 446 generic_steppings, "5TE" }, 447 { CPU_ID_ARM1022ES, CPU_CLASS_ARM10E, "ARM1022E-S", 448 generic_steppings, "5TE" }, 449 450 { CPU_ID_ARM1026EJS, CPU_CLASS_ARM10EJ, "ARM1026EJ-S", 451 generic_steppings, "5TEJ" }, 452 { CPU_ID_ARM926EJS, CPU_CLASS_ARM9EJS, "ARM926EJ-S", 453 generic_steppings, "5TEJ" }, 454 455 { CPU_ID_ARM1136JS, CPU_CLASS_ARM11J, "ARM1136J-S r0", 456 pN_steppings, "6J" }, 457 { CPU_ID_ARM1136JSR1, CPU_CLASS_ARM11J, "ARM1136J-S r1", 458 pN_steppings, "6J" }, 459 #if 0 460 /* The ARM1156T2-S only has a memory protection unit */ 461 { CPU_ID_ARM1156T2S, CPU_CLASS_ARM11J, "ARM1156T2-S r0", 462 pN_steppings, "6T2" }, 463 #endif 464 { CPU_ID_ARM1176JZS, CPU_CLASS_ARM11J, "ARM1176JZ-S r0", 465 pN_steppings, "6ZK" }, 466 467 { CPU_ID_ARM11MPCORE, CPU_CLASS_ARM11J, "ARM11 MPCore", 468 generic_steppings, "6K" }, 469 470 { CPU_ID_CORTEXA5R0, CPU_CLASS_CORTEX, "Cortex-A5 r0", 471 pN_steppings, "7A" }, 472 { CPU_ID_CORTEXA7R0, CPU_CLASS_CORTEX, "Cortex-A7 r0", 473 pN_steppings, "7A" }, 474 { CPU_ID_CORTEXA8R1, CPU_CLASS_CORTEX, "Cortex-A8 r1", 475 pN_steppings, "7A" }, 476 { CPU_ID_CORTEXA8R2, CPU_CLASS_CORTEX, "Cortex-A8 r2", 477 pN_steppings, "7A" }, 478 { CPU_ID_CORTEXA8R3, CPU_CLASS_CORTEX, "Cortex-A8 r3", 479 pN_steppings, "7A" }, 480 { CPU_ID_CORTEXA9R2, CPU_CLASS_CORTEX, "Cortex-A9 r2", 481 pN_steppings, "7A" }, 482 { CPU_ID_CORTEXA9R3, CPU_CLASS_CORTEX, "Cortex-A9 r3", 483 pN_steppings, "7A" }, 484 { CPU_ID_CORTEXA9R4, CPU_CLASS_CORTEX, "Cortex-A9 r4", 485 pN_steppings, "7A" }, 486 { CPU_ID_CORTEXA15R2, CPU_CLASS_CORTEX, "Cortex-A15 r2", 487 pN_steppings, "7A" }, 488 { CPU_ID_CORTEXA15R3, CPU_CLASS_CORTEX, "Cortex-A15 r3", 489 pN_steppings, "7A" }, 490 491 { CPU_ID_MV88SV581X_V6, CPU_CLASS_PJ4B, "Sheeva 88SV581x", 492 generic_steppings }, 493 { CPU_ID_ARM_88SV581X_V6, CPU_CLASS_PJ4B, "Sheeva 88SV581x", 494 generic_steppings }, 495 { CPU_ID_MV88SV581X_V7, CPU_CLASS_PJ4B, "Sheeva 88SV581x", 496 generic_steppings }, 497 { CPU_ID_ARM_88SV581X_V7, CPU_CLASS_PJ4B, "Sheeva 88SV581x", 498 generic_steppings }, 499 { CPU_ID_MV88SV584X_V6, CPU_CLASS_PJ4B, "Sheeva 88SV584x", 500 generic_steppings }, 501 { CPU_ID_ARM_88SV584X_V6, CPU_CLASS_PJ4B, "Sheeva 88SV584x", 502 generic_steppings }, 503 { CPU_ID_MV88SV584X_V7, CPU_CLASS_PJ4B, "Sheeva 88SV584x", 504 generic_steppings }, 505 506 507 { 0, CPU_CLASS_NONE, NULL, NULL, "" } 508 }; 509 510 struct cpu_classtab { 511 const char *class_name; 512 const char *class_option; 513 }; 514 515 const struct cpu_classtab cpu_classes[] = { 516 [CPU_CLASS_NONE] = { "unknown", NULL }, 517 [CPU_CLASS_ARM2] = { "ARM2", "CPU_ARM2" }, 518 [CPU_CLASS_ARM2AS] = { "ARM2as", "CPU_ARM250" }, 519 [CPU_CLASS_ARM3] = { "ARM3", "CPU_ARM3" }, 520 [CPU_CLASS_ARM6] = { "ARM6", "CPU_ARM6" }, 521 [CPU_CLASS_ARM7] = { "ARM7", "CPU_ARM7" }, 522 [CPU_CLASS_ARM7TDMI] = { "ARM7TDMI", "CPU_ARM7TDMI" }, 523 [CPU_CLASS_ARM8] = { "ARM8", "CPU_ARM8" }, 524 [CPU_CLASS_ARM9TDMI] = { "ARM9TDMI", NULL }, 525 [CPU_CLASS_ARM9ES] = { "ARM9E-S", "CPU_ARM9E" }, 526 [CPU_CLASS_ARM9EJS] = { "ARM9EJ-S", "CPU_ARM9E" }, 527 [CPU_CLASS_ARM10E] = { "ARM10E", "CPU_ARM10" }, 528 [CPU_CLASS_ARM10EJ] = { "ARM10EJ", "CPU_ARM10" }, 529 [CPU_CLASS_SA1] = { "SA-1", "CPU_SA110" }, 530 [CPU_CLASS_XSCALE] = { "XScale", "CPU_XSCALE_..." }, 531 [CPU_CLASS_ARM11J] = { "ARM11J", "CPU_ARM11" }, 532 [CPU_CLASS_ARMV4] = { "ARMv4", "CPU_ARMV4" }, 533 [CPU_CLASS_CORTEX] = { "Cortex", "CPU_CORTEX" }, 534 [CPU_CLASS_PJ4B] = { "Marvell", "CPU_PJ4B" }, 535 }; 536 537 /* 538 * Report the type of the specified arm processor. This uses the generic and 539 * arm specific information in the CPU structure to identify the processor. 540 * The remaining fields in the CPU structure are filled in appropriately. 541 */ 542 543 static const char * const wtnames[] = { 544 "write-through", 545 "write-back", 546 "write-back", 547 "**unknown 3**", 548 "**unknown 4**", 549 "write-back-locking", /* XXX XScale-specific? */ 550 "write-back-locking-A", 551 "write-back-locking-B", 552 "**unknown 8**", 553 "**unknown 9**", 554 "**unknown 10**", 555 "**unknown 11**", 556 "**unknown 12**", 557 "**unknown 13**", 558 "write-back-locking-C", 559 "write-back-locking-D", 560 }; 561 562 static void 563 print_cache_info(device_t dv, struct arm_cache_info *info, u_int level) 564 { 565 if (info->cache_unified) { 566 aprint_normal_dev(dv, "%dKB/%dB %d-way %s L%u Unified cache\n", 567 info->dcache_size / 1024, 568 info->dcache_line_size, info->dcache_ways, 569 wtnames[info->cache_type], level + 1); 570 } else { 571 aprint_normal_dev(dv, "%dKB/%dB %d-way L%u Instruction cache\n", 572 info->icache_size / 1024, 573 info->icache_line_size, info->icache_ways, level + 1); 574 aprint_normal_dev(dv, "%dKB/%dB %d-way %s L%u Data cache\n", 575 info->dcache_size / 1024, 576 info->dcache_line_size, info->dcache_ways, 577 wtnames[info->cache_type], level + 1); 578 } 579 } 580 581 void 582 identify_arm_cpu(device_t dv, struct cpu_info *ci) 583 { 584 enum cpu_class cpu_class = CPU_CLASS_NONE; 585 const u_int cpuid = ci->ci_arm_cpuid; 586 const char * const xname = device_xname(dv); 587 const char *steppingstr; 588 int i; 589 590 if (cpuid == 0) { 591 aprint_error("Processor failed probe - no CPU ID\n"); 592 return; 593 } 594 595 for (i = 0; cpuids[i].cpuid != 0; i++) 596 if (cpuids[i].cpuid == (cpuid & CPU_ID_CPU_MASK)) { 597 cpu_class = cpuids[i].cpu_class; 598 cpu_arch = cpuids[i].cpu_arch; 599 steppingstr = cpuids[i].cpu_steppings[cpuid & 600 CPU_ID_REVISION_MASK]; 601 snprintf(cpu_model, sizeof(cpu_model), 602 "%s%s%s (%s V%s core)", cpuids[i].cpu_classname, 603 steppingstr[0] == '*' ? "" : " ", 604 &steppingstr[steppingstr[0] == '*'], 605 cpu_classes[cpu_class].class_name, 606 cpu_arch); 607 break; 608 } 609 610 if (cpuids[i].cpuid == 0) 611 snprintf(cpu_model, sizeof(cpu_model), 612 "unknown CPU (ID = 0x%x)", cpuid); 613 614 if (ci->ci_data.cpu_cc_freq != 0) { 615 char freqbuf[8]; 616 humanize_number(freqbuf, sizeof(freqbuf), ci->ci_data.cpu_cc_freq, 617 "Hz", 1000); 618 619 aprint_naive(": %s %s\n", freqbuf, cpu_model); 620 aprint_normal(": %s %s\n", freqbuf, cpu_model); 621 } else { 622 aprint_naive(": %s\n", cpu_model); 623 aprint_normal(": %s\n", cpu_model); 624 } 625 626 aprint_normal("%s:", xname); 627 628 switch (cpu_class) { 629 case CPU_CLASS_ARM6: 630 case CPU_CLASS_ARM7: 631 case CPU_CLASS_ARM7TDMI: 632 case CPU_CLASS_ARM8: 633 if ((ci->ci_ctrl & CPU_CONTROL_IDC_ENABLE) == 0) 634 aprint_normal(" IDC disabled"); 635 else 636 aprint_normal(" IDC enabled"); 637 break; 638 case CPU_CLASS_ARM9TDMI: 639 case CPU_CLASS_ARM9ES: 640 case CPU_CLASS_ARM9EJS: 641 case CPU_CLASS_ARM10E: 642 case CPU_CLASS_ARM10EJ: 643 case CPU_CLASS_SA1: 644 case CPU_CLASS_XSCALE: 645 case CPU_CLASS_ARM11J: 646 case CPU_CLASS_ARMV4: 647 case CPU_CLASS_CORTEX: 648 case CPU_CLASS_PJ4B: 649 if ((ci->ci_ctrl & CPU_CONTROL_DC_ENABLE) == 0) 650 aprint_normal(" DC disabled"); 651 else 652 aprint_normal(" DC enabled"); 653 if ((ci->ci_ctrl & CPU_CONTROL_IC_ENABLE) == 0) 654 aprint_normal(" IC disabled"); 655 else 656 aprint_normal(" IC enabled"); 657 break; 658 default: 659 break; 660 } 661 if ((ci->ci_ctrl & CPU_CONTROL_WBUF_ENABLE) == 0) 662 aprint_normal(" WB disabled"); 663 else 664 aprint_normal(" WB enabled"); 665 666 if (ci->ci_ctrl & CPU_CONTROL_LABT_ENABLE) 667 aprint_normal(" LABT"); 668 else 669 aprint_normal(" EABT"); 670 671 if (ci->ci_ctrl & CPU_CONTROL_BPRD_ENABLE) 672 aprint_normal(" branch prediction enabled"); 673 674 aprint_normal("\n"); 675 676 if (CPU_ID_CORTEX_P(cpuid) || CPU_ID_ARM11_P(cpuid) || CPU_ID_MV88SV58XX_P(cpuid)) { 677 identify_features(dv); 678 } 679 680 /* Print cache info. */ 681 if (arm_pcache.icache_line_size != 0 || arm_pcache.dcache_line_size != 0) { 682 print_cache_info(dv, &arm_pcache, 0); 683 } 684 if (arm_scache.icache_line_size != 0 || arm_scache.dcache_line_size != 0) { 685 print_cache_info(dv, &arm_scache, 1); 686 } 687 688 689 switch (cpu_class) { 690 #ifdef CPU_ARM2 691 case CPU_CLASS_ARM2: 692 #endif 693 #ifdef CPU_ARM250 694 case CPU_CLASS_ARM2AS: 695 #endif 696 #ifdef CPU_ARM3 697 case CPU_CLASS_ARM3: 698 #endif 699 #ifdef CPU_ARM6 700 case CPU_CLASS_ARM6: 701 #endif 702 #ifdef CPU_ARM7 703 case CPU_CLASS_ARM7: 704 #endif 705 #ifdef CPU_ARM7TDMI 706 case CPU_CLASS_ARM7TDMI: 707 #endif 708 #ifdef CPU_ARM8 709 case CPU_CLASS_ARM8: 710 #endif 711 #ifdef CPU_ARM9 712 case CPU_CLASS_ARM9TDMI: 713 #endif 714 #if defined(CPU_ARM9E) || defined(CPU_SHEEVA) 715 case CPU_CLASS_ARM9ES: 716 case CPU_CLASS_ARM9EJS: 717 #endif 718 #ifdef CPU_ARM10 719 case CPU_CLASS_ARM10E: 720 case CPU_CLASS_ARM10EJ: 721 #endif 722 #if defined(CPU_SA110) || defined(CPU_SA1100) || \ 723 defined(CPU_SA1110) || defined(CPU_IXP12X0) 724 case CPU_CLASS_SA1: 725 #endif 726 #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 727 defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425) 728 case CPU_CLASS_XSCALE: 729 #endif 730 #if defined(CPU_ARM11) 731 case CPU_CLASS_ARM11J: 732 #endif 733 #if defined(CPU_CORTEX) 734 case CPU_CLASS_CORTEX: 735 #endif 736 #if defined(CPU_PJ4B) 737 case CPU_CLASS_PJ4B: 738 #endif 739 #if defined(CPU_FA526) 740 case CPU_CLASS_ARMV4: 741 #endif 742 break; 743 default: 744 if (cpu_classes[cpu_class].class_option == NULL) { 745 aprint_error_dev(dv, "%s does not fully support this CPU.\n", 746 ostype); 747 } else { 748 aprint_error_dev(dv, "This kernel does not fully support " 749 "this CPU.\n"); 750 aprint_normal_dev(dv, "Recompile with \"options %s\" to " 751 "correct this.\n", cpu_classes[cpu_class].class_option); 752 } 753 break; 754 } 755 } 756 757 extern int cpu_instruction_set_attributes[6]; 758 extern int cpu_memory_model_features[4]; 759 extern int cpu_processor_features[2]; 760 extern int cpu_simd_present; 761 extern int cpu_simdex_present; 762 763 void 764 identify_features(device_t dv) 765 { 766 cpu_instruction_set_attributes[0] = armreg_isar0_read(); 767 cpu_instruction_set_attributes[1] = armreg_isar1_read(); 768 cpu_instruction_set_attributes[2] = armreg_isar2_read(); 769 cpu_instruction_set_attributes[3] = armreg_isar3_read(); 770 cpu_instruction_set_attributes[4] = armreg_isar4_read(); 771 cpu_instruction_set_attributes[5] = armreg_isar5_read(); 772 773 cpu_hwdiv_present = 774 ((cpu_instruction_set_attributes[0] >> 24) & 0x0f) >= 2; 775 cpu_simd_present = 776 ((cpu_instruction_set_attributes[3] >> 4) & 0x0f) >= 3; 777 cpu_simdex_present = cpu_simd_present 778 && ((cpu_instruction_set_attributes[1] >> 12) & 0x0f) >= 2; 779 780 cpu_memory_model_features[0] = armreg_mmfr0_read(); 781 cpu_memory_model_features[1] = armreg_mmfr1_read(); 782 cpu_memory_model_features[2] = armreg_mmfr2_read(); 783 cpu_memory_model_features[3] = armreg_mmfr3_read(); 784 785 if (__SHIFTOUT(cpu_memory_model_features[3], __BITS(23,20))) { 786 /* 787 * Updates to the translation tables do not require a clean 788 * to the point of unification to ensure visibility by 789 * subsequent translation table walks. 790 */ 791 pmap_needs_pte_sync = 0; 792 } 793 794 cpu_processor_features[0] = armreg_pfr0_read(); 795 cpu_processor_features[1] = armreg_pfr1_read(); 796 797 aprint_verbose_dev(dv, 798 "isar: [0]=%#x [1]=%#x [2]=%#x [3]=%#x, [4]=%#x, [5]=%#x\n", 799 cpu_instruction_set_attributes[0], 800 cpu_instruction_set_attributes[1], 801 cpu_instruction_set_attributes[2], 802 cpu_instruction_set_attributes[3], 803 cpu_instruction_set_attributes[4], 804 cpu_instruction_set_attributes[5]); 805 aprint_verbose_dev(dv, 806 "mmfr: [0]=%#x [1]=%#x [2]=%#x [3]=%#x\n", 807 cpu_memory_model_features[0], cpu_memory_model_features[1], 808 cpu_memory_model_features[2], cpu_memory_model_features[3]); 809 aprint_verbose_dev(dv, 810 "pfr: [0]=%#x [1]=%#x\n", 811 cpu_processor_features[0], cpu_processor_features[1]); 812 } 813
Indexes created Wed Oct 22 00:09:40 GMT 2025