cpu.c revision 1.72.2.1
1 /* $NetBSD: cpu.c,v 1.72.2.1 2010/08/17 06:44:01 uebayasi Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Mark Brinicombe. 5 * Copyright (c) 1995 Brini. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Brini. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * cpu.c 38 * 39 * Probing and configuration for the master CPU 40 * 41 * Created : 10/10/95 42 */ 43 44 #include "opt_armfpe.h" 45 #include "opt_multiprocessor.h" 46 47 #include <sys/param.h> 48 49 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.72.2.1 2010/08/17 06:44:01 uebayasi Exp $"); 50 51 #include <sys/systm.h> 52 #include <sys/malloc.h> 53 #include <sys/device.h> 54 #include <sys/proc.h> 55 #include <sys/conf.h> 56 #include <uvm/uvm_extern.h> 57 #include <machine/cpu.h> 58 59 #include <arm/cpuconf.h> 60 #include <arm/undefined.h> 61 62 #ifdef ARMFPE 63 #include <machine/bootconfig.h> /* For boot args */ 64 #include <arm/fpe-arm/armfpe.h> 65 #endif 66 67 #ifdef FPU_VFP 68 #include <arm/vfpvar.h> 69 #endif 70 71 char cpu_model[256]; 72 73 /* Prototypes */ 74 void identify_arm_cpu(struct device *dv, struct cpu_info *); 75 76 /* 77 * Identify the master (boot) CPU 78 */ 79 80 void 81 cpu_attach(struct device *dv) 82 { 83 int usearmfpe; 84 85 usearmfpe = 1; /* when compiled in, its enabled by default */ 86 87 curcpu()->ci_dev = dv; 88 89 evcnt_attach_dynamic(&curcpu()->ci_arm700bugcount, EVCNT_TYPE_MISC, 90 NULL, dv->dv_xname, "arm700swibug"); 91 92 /* Get the CPU ID from coprocessor 15 */ 93 94 curcpu()->ci_arm_cpuid = cpu_id(); 95 curcpu()->ci_arm_cputype = curcpu()->ci_arm_cpuid & CPU_ID_CPU_MASK; 96 curcpu()->ci_arm_cpurev = 97 curcpu()->ci_arm_cpuid & CPU_ID_REVISION_MASK; 98 99 identify_arm_cpu(dv, curcpu()); 100 101 if (curcpu()->ci_arm_cputype == CPU_ID_SA110 && 102 curcpu()->ci_arm_cpurev < 3) { 103 aprint_normal("%s: SA-110 with bugged STM^ instruction\n", 104 dv->dv_xname); 105 } 106 107 #ifdef CPU_ARM8 108 if ((curcpu()->ci_arm_cpuid & CPU_ID_CPU_MASK) == CPU_ID_ARM810) { 109 int clock = arm8_clock_config(0, 0); 110 char *fclk; 111 aprint_normal("%s: ARM810 cp15=%02x", dv->dv_xname, clock); 112 aprint_normal(" clock:%s", (clock & 1) ? " dynamic" : ""); 113 aprint_normal("%s", (clock & 2) ? " sync" : ""); 114 switch ((clock >> 2) & 3) { 115 case 0: 116 fclk = "bus clock"; 117 break; 118 case 1: 119 fclk = "ref clock"; 120 break; 121 case 3: 122 fclk = "pll"; 123 break; 124 default: 125 fclk = "illegal"; 126 break; 127 } 128 aprint_normal(" fclk source=%s\n", fclk); 129 } 130 #endif 131 132 #ifdef ARMFPE 133 /* 134 * Ok now we test for an FPA 135 * At this point no floating point emulator has been installed. 136 * This means any FP instruction will cause undefined exception. 137 * We install a temporay coproc 1 handler which will modify 138 * undefined_test if it is called. 139 * We then try to read the FP status register. If undefined_test 140 * has been decremented then the instruction was not handled by 141 * an FPA so we know the FPA is missing. If undefined_test is 142 * still 1 then we know the instruction was handled by an FPA. 143 * We then remove our test handler and look at the 144 * FP status register for identification. 145 */ 146 147 /* 148 * Ok if ARMFPE is defined and the boot options request the 149 * ARM FPE then it will be installed as the FPE. 150 * This is just while I work on integrating the new FPE. 151 * It means the new FPE gets installed if compiled int (ARMFPE 152 * defined) and also gives me a on/off option when I boot in 153 * case the new FPE is causing panics. 154 */ 155 156 157 if (boot_args) 158 get_bootconf_option(boot_args, "armfpe", 159 BOOTOPT_TYPE_BOOLEAN, &usearmfpe); 160 if (usearmfpe) 161 initialise_arm_fpe(); 162 #endif 163 164 #ifdef FPU_VFP 165 vfp_attach(); 166 #endif 167 } 168 169 enum cpu_class { 170 CPU_CLASS_NONE, 171 CPU_CLASS_ARM2, 172 CPU_CLASS_ARM2AS, 173 CPU_CLASS_ARM3, 174 CPU_CLASS_ARM6, 175 CPU_CLASS_ARM7, 176 CPU_CLASS_ARM7TDMI, 177 CPU_CLASS_ARM8, 178 CPU_CLASS_ARM9TDMI, 179 CPU_CLASS_ARM9ES, 180 CPU_CLASS_ARM9EJS, 181 CPU_CLASS_ARM10E, 182 CPU_CLASS_ARM10EJ, 183 CPU_CLASS_SA1, 184 CPU_CLASS_XSCALE, 185 CPU_CLASS_ARM11J, 186 CPU_CLASS_ARMV4, 187 CPU_CLASS_CORTEX, 188 }; 189 190 static const char * const generic_steppings[16] = { 191 "rev 0", "rev 1", "rev 2", "rev 3", 192 "rev 4", "rev 5", "rev 6", "rev 7", 193 "rev 8", "rev 9", "rev 10", "rev 11", 194 "rev 12", "rev 13", "rev 14", "rev 15", 195 }; 196 197 static const char * const pN_steppings[16] = { 198 "*p0", "*p1", "*p2", "*p3", "*p4", "*p5", "*p6", "*p7", 199 "*p8", "*p9", "*p10", "*p11", "*p12", "*p13", "*p14", "*p15", 200 }; 201 202 static const char * const sa110_steppings[16] = { 203 "rev 0", "step J", "step K", "step S", 204 "step T", "rev 5", "rev 6", "rev 7", 205 "rev 8", "rev 9", "rev 10", "rev 11", 206 "rev 12", "rev 13", "rev 14", "rev 15", 207 }; 208 209 static const char * const sa1100_steppings[16] = { 210 "rev 0", "step B", "step C", "rev 3", 211 "rev 4", "rev 5", "rev 6", "rev 7", 212 "step D", "step E", "rev 10" "step G", 213 "rev 12", "rev 13", "rev 14", "rev 15", 214 }; 215 216 static const char * const sa1110_steppings[16] = { 217 "step A-0", "rev 1", "rev 2", "rev 3", 218 "step B-0", "step B-1", "step B-2", "step B-3", 219 "step B-4", "step B-5", "rev 10", "rev 11", 220 "rev 12", "rev 13", "rev 14", "rev 15", 221 }; 222 223 static const char * const ixp12x0_steppings[16] = { 224 "(IXP1200 step A)", "(IXP1200 step B)", 225 "rev 2", "(IXP1200 step C)", 226 "(IXP1200 step D)", "(IXP1240/1250 step A)", 227 "(IXP1240 step B)", "(IXP1250 step B)", 228 "rev 8", "rev 9", "rev 10", "rev 11", 229 "rev 12", "rev 13", "rev 14", "rev 15", 230 }; 231 232 static const char * const xscale_steppings[16] = { 233 "step A-0", "step A-1", "step B-0", "step C-0", 234 "step D-0", "rev 5", "rev 6", "rev 7", 235 "rev 8", "rev 9", "rev 10", "rev 11", 236 "rev 12", "rev 13", "rev 14", "rev 15", 237 }; 238 239 static const char * const i80321_steppings[16] = { 240 "step A-0", "step B-0", "rev 2", "rev 3", 241 "rev 4", "rev 5", "rev 6", "rev 7", 242 "rev 8", "rev 9", "rev 10", "rev 11", 243 "rev 12", "rev 13", "rev 14", "rev 15", 244 }; 245 246 static const char * const i80219_steppings[16] = { 247 "step A-0", "rev 1", "rev 2", "rev 3", 248 "rev 4", "rev 5", "rev 6", "rev 7", 249 "rev 8", "rev 9", "rev 10", "rev 11", 250 "rev 12", "rev 13", "rev 14", "rev 15", 251 }; 252 253 /* Steppings for PXA2[15]0 */ 254 static const char * const pxa2x0_steppings[16] = { 255 "step A-0", "step A-1", "step B-0", "step B-1", 256 "step B-2", "step C-0", "rev 6", "rev 7", 257 "rev 8", "rev 9", "rev 10", "rev 11", 258 "rev 12", "rev 13", "rev 14", "rev 15", 259 }; 260 261 /* Steppings for PXA255/26x. 262 * rev 5: PXA26x B0, rev 6: PXA255 A0 263 */ 264 static const char * const pxa255_steppings[16] = { 265 "rev 0", "rev 1", "rev 2", "step A-0", 266 "rev 4", "step B-0", "step A-0", "rev 7", 267 "rev 8", "rev 9", "rev 10", "rev 11", 268 "rev 12", "rev 13", "rev 14", "rev 15", 269 }; 270 271 /* Stepping for PXA27x */ 272 static const char * const pxa27x_steppings[16] = { 273 "step A-0", "step A-1", "step B-0", "step B-1", 274 "step C-0", "rev 5", "rev 6", "rev 7", 275 "rev 8", "rev 9", "rev 10", "rev 11", 276 "rev 12", "rev 13", "rev 14", "rev 15", 277 }; 278 279 static const char * const ixp425_steppings[16] = { 280 "step 0", "rev 1", "rev 2", "rev 3", 281 "rev 4", "rev 5", "rev 6", "rev 7", 282 "rev 8", "rev 9", "rev 10", "rev 11", 283 "rev 12", "rev 13", "rev 14", "rev 15", 284 }; 285 286 struct cpuidtab { 287 u_int32_t cpuid; 288 enum cpu_class cpu_class; 289 const char *cpu_classname; 290 const char * const *cpu_steppings; 291 }; 292 293 const struct cpuidtab cpuids[] = { 294 { CPU_ID_ARM2, CPU_CLASS_ARM2, "ARM2", 295 generic_steppings }, 296 { CPU_ID_ARM250, CPU_CLASS_ARM2AS, "ARM250", 297 generic_steppings }, 298 299 { CPU_ID_ARM3, CPU_CLASS_ARM3, "ARM3", 300 generic_steppings }, 301 302 { CPU_ID_ARM600, CPU_CLASS_ARM6, "ARM600", 303 generic_steppings }, 304 { CPU_ID_ARM610, CPU_CLASS_ARM6, "ARM610", 305 generic_steppings }, 306 { CPU_ID_ARM620, CPU_CLASS_ARM6, "ARM620", 307 generic_steppings }, 308 309 { CPU_ID_ARM700, CPU_CLASS_ARM7, "ARM700", 310 generic_steppings }, 311 { CPU_ID_ARM710, CPU_CLASS_ARM7, "ARM710", 312 generic_steppings }, 313 { CPU_ID_ARM7500, CPU_CLASS_ARM7, "ARM7500", 314 generic_steppings }, 315 { CPU_ID_ARM710A, CPU_CLASS_ARM7, "ARM710a", 316 generic_steppings }, 317 { CPU_ID_ARM7500FE, CPU_CLASS_ARM7, "ARM7500FE", 318 generic_steppings }, 319 { CPU_ID_ARM710T, CPU_CLASS_ARM7TDMI, "ARM710T", 320 generic_steppings }, 321 { CPU_ID_ARM720T, CPU_CLASS_ARM7TDMI, "ARM720T", 322 generic_steppings }, 323 { CPU_ID_ARM740T8K, CPU_CLASS_ARM7TDMI, "ARM740T (8 KB cache)", 324 generic_steppings }, 325 { CPU_ID_ARM740T4K, CPU_CLASS_ARM7TDMI, "ARM740T (4 KB cache)", 326 generic_steppings }, 327 328 { CPU_ID_ARM810, CPU_CLASS_ARM8, "ARM810", 329 generic_steppings }, 330 331 { CPU_ID_ARM920T, CPU_CLASS_ARM9TDMI, "ARM920T", 332 generic_steppings }, 333 { CPU_ID_ARM922T, CPU_CLASS_ARM9TDMI, "ARM922T", 334 generic_steppings }, 335 { CPU_ID_ARM926EJS, CPU_CLASS_ARM9EJS, "ARM926EJ-S", 336 generic_steppings }, 337 { CPU_ID_ARM940T, CPU_CLASS_ARM9TDMI, "ARM940T", 338 generic_steppings }, 339 { CPU_ID_ARM946ES, CPU_CLASS_ARM9ES, "ARM946E-S", 340 generic_steppings }, 341 { CPU_ID_ARM966ES, CPU_CLASS_ARM9ES, "ARM966E-S", 342 generic_steppings }, 343 { CPU_ID_ARM966ESR1, CPU_CLASS_ARM9ES, "ARM966E-S", 344 generic_steppings }, 345 { CPU_ID_TI925T, CPU_CLASS_ARM9TDMI, "TI ARM925T", 346 generic_steppings }, 347 348 { CPU_ID_ARM1020E, CPU_CLASS_ARM10E, "ARM1020E", 349 generic_steppings }, 350 { CPU_ID_ARM1022ES, CPU_CLASS_ARM10E, "ARM1022E-S", 351 generic_steppings }, 352 { CPU_ID_ARM1026EJS, CPU_CLASS_ARM10EJ, "ARM1026EJ-S", 353 generic_steppings }, 354 355 { CPU_ID_SA110, CPU_CLASS_SA1, "SA-110", 356 sa110_steppings }, 357 { CPU_ID_SA1100, CPU_CLASS_SA1, "SA-1100", 358 sa1100_steppings }, 359 { CPU_ID_SA1110, CPU_CLASS_SA1, "SA-1110", 360 sa1110_steppings }, 361 362 { CPU_ID_IXP1200, CPU_CLASS_SA1, "IXP1200", 363 ixp12x0_steppings }, 364 365 { CPU_ID_80200, CPU_CLASS_XSCALE, "i80200", 366 xscale_steppings }, 367 368 { CPU_ID_80321_400, CPU_CLASS_XSCALE, "i80321 400MHz", 369 i80321_steppings }, 370 { CPU_ID_80321_600, CPU_CLASS_XSCALE, "i80321 600MHz", 371 i80321_steppings }, 372 { CPU_ID_80321_400_B0, CPU_CLASS_XSCALE, "i80321 400MHz", 373 i80321_steppings }, 374 { CPU_ID_80321_600_B0, CPU_CLASS_XSCALE, "i80321 600MHz", 375 i80321_steppings }, 376 377 { CPU_ID_80219_400, CPU_CLASS_XSCALE, "i80219 400MHz", 378 i80219_steppings }, 379 { CPU_ID_80219_600, CPU_CLASS_XSCALE, "i80219 600MHz", 380 i80219_steppings }, 381 382 { CPU_ID_PXA27X, CPU_CLASS_XSCALE, "PXA27x", 383 pxa27x_steppings }, 384 { CPU_ID_PXA250A, CPU_CLASS_XSCALE, "PXA250", 385 pxa2x0_steppings }, 386 { CPU_ID_PXA210A, CPU_CLASS_XSCALE, "PXA210", 387 pxa2x0_steppings }, 388 { CPU_ID_PXA250B, CPU_CLASS_XSCALE, "PXA250", 389 pxa2x0_steppings }, 390 { CPU_ID_PXA210B, CPU_CLASS_XSCALE, "PXA210", 391 pxa2x0_steppings }, 392 { CPU_ID_PXA250C, CPU_CLASS_XSCALE, "PXA255/26x", 393 pxa255_steppings }, 394 { CPU_ID_PXA210C, CPU_CLASS_XSCALE, "PXA210", 395 pxa2x0_steppings }, 396 397 { CPU_ID_IXP425_533, CPU_CLASS_XSCALE, "IXP425 533MHz", 398 ixp425_steppings }, 399 { CPU_ID_IXP425_400, CPU_CLASS_XSCALE, "IXP425 400MHz", 400 ixp425_steppings }, 401 { CPU_ID_IXP425_266, CPU_CLASS_XSCALE, "IXP425 266MHz", 402 ixp425_steppings }, 403 404 { CPU_ID_ARM1136JS, CPU_CLASS_ARM11J, "ARM1136J-S r0", 405 pN_steppings }, 406 { CPU_ID_ARM1136JSR1, CPU_CLASS_ARM11J, "ARM1136J-S r1", 407 pN_steppings }, 408 { CPU_ID_ARM1176JS, CPU_CLASS_ARM11J, "ARM1176J-S r0", 409 pN_steppings }, 410 411 { CPU_ID_CORTEXA8R1, CPU_CLASS_CORTEX, "Cortex-A8 r1", 412 pN_steppings }, 413 { CPU_ID_CORTEXA8R2, CPU_CLASS_CORTEX, "Cortex-A8 r2", 414 pN_steppings }, 415 { CPU_ID_CORTEXA8R3, CPU_CLASS_CORTEX, "Cortex-A8 r3", 416 pN_steppings }, 417 { CPU_ID_CORTEXA9R1, CPU_CLASS_CORTEX, "Cortex-A9 r1", 418 pN_steppings }, 419 { CPU_ID_CORTEXA8R3, CPU_CLASS_ARM11J, "Cortex-A8 r3", 420 pN_steppings }, 421 422 { CPU_ID_FA526, CPU_CLASS_ARMV4, "FA526", 423 generic_steppings }, 424 425 { 0, CPU_CLASS_NONE, NULL, NULL } 426 }; 427 428 struct cpu_classtab { 429 const char *class_name; 430 const char *class_option; 431 }; 432 433 const struct cpu_classtab cpu_classes[] = { 434 [CPU_CLASS_NONE] = { "unknown", NULL }, 435 [CPU_CLASS_ARM2] = { "ARM2", "CPU_ARM2" }, 436 [CPU_CLASS_ARM2AS] = { "ARM2as", "CPU_ARM250" }, 437 [CPU_CLASS_ARM3] = { "ARM3", "CPU_ARM3" }, 438 [CPU_CLASS_ARM6] = { "ARM6", "CPU_ARM6" }, 439 [CPU_CLASS_ARM7] = { "ARM7", "CPU_ARM7" }, 440 [CPU_CLASS_ARM7TDMI] = { "ARM7TDMI", "CPU_ARM7TDMI" }, 441 [CPU_CLASS_ARM8] = { "ARM8", "CPU_ARM8" }, 442 [CPU_CLASS_ARM9TDMI] = { "ARM9TDMI", NULL }, 443 [CPU_CLASS_ARM9ES] = { "ARM9E-S", "CPU_ARM9E" }, 444 [CPU_CLASS_ARM9EJS] = { "ARM9EJ-S", "CPU_ARM9E" }, 445 [CPU_CLASS_ARM10E] = { "ARM10E", "CPU_ARM10" }, 446 [CPU_CLASS_ARM10EJ] = { "ARM10EJ", "CPU_ARM10" }, 447 [CPU_CLASS_SA1] = { "SA-1", "CPU_SA110" }, 448 [CPU_CLASS_XSCALE] = { "XScale", "CPU_XSCALE_..." }, 449 [CPU_CLASS_ARM11J] = { "ARM11J", "CPU_ARM11" }, 450 [CPU_CLASS_ARMV4] = { "ARMv4", "CPU_ARMV4" }, 451 [CPU_CLASS_CORTEX] = { "Cortex", "CPU_CORTEX" }, 452 }; 453 454 /* 455 * Report the type of the specified arm processor. This uses the generic and 456 * arm specific information in the CPU structure to identify the processor. 457 * The remaining fields in the CPU structure are filled in appropriately. 458 */ 459 460 static const char * const wtnames[] = { 461 "write-through", 462 "write-back", 463 "write-back", 464 "**unknown 3**", 465 "**unknown 4**", 466 "write-back-locking", /* XXX XScale-specific? */ 467 "write-back-locking-A", 468 "write-back-locking-B", 469 "**unknown 8**", 470 "**unknown 9**", 471 "**unknown 10**", 472 "**unknown 11**", 473 "**unknown 12**", 474 "**unknown 13**", 475 "write-back-locking-C", 476 "**unknown 15**", 477 }; 478 479 void 480 identify_arm_cpu(struct device *dv, struct cpu_info *ci) 481 { 482 u_int cpuid; 483 enum cpu_class cpu_class = CPU_CLASS_NONE; 484 int i; 485 const char *steppingstr; 486 487 cpuid = ci->ci_arm_cpuid; 488 489 if (cpuid == 0) { 490 aprint_error("Processor failed probe - no CPU ID\n"); 491 return; 492 } 493 494 for (i = 0; cpuids[i].cpuid != 0; i++) 495 if (cpuids[i].cpuid == (cpuid & CPU_ID_CPU_MASK)) { 496 cpu_class = cpuids[i].cpu_class; 497 steppingstr = cpuids[i].cpu_steppings[cpuid & 498 CPU_ID_REVISION_MASK], 499 sprintf(cpu_model, "%s%s%s (%s core)", 500 cpuids[i].cpu_classname, 501 steppingstr[0] == '*' ? "" : " ", 502 &steppingstr[steppingstr[0] == '*'], 503 cpu_classes[cpu_class].class_name); 504 break; 505 } 506 507 if (cpuids[i].cpuid == 0) 508 sprintf(cpu_model, "unknown CPU (ID = 0x%x)", cpuid); 509 510 aprint_naive(": %s\n", cpu_model); 511 aprint_normal(": %s\n", cpu_model); 512 513 aprint_normal("%s:", dv->dv_xname); 514 515 switch (cpu_class) { 516 case CPU_CLASS_ARM6: 517 case CPU_CLASS_ARM7: 518 case CPU_CLASS_ARM7TDMI: 519 case CPU_CLASS_ARM8: 520 if ((ci->ci_ctrl & CPU_CONTROL_IDC_ENABLE) == 0) 521 aprint_normal(" IDC disabled"); 522 else 523 aprint_normal(" IDC enabled"); 524 break; 525 case CPU_CLASS_ARM9TDMI: 526 case CPU_CLASS_ARM9ES: 527 case CPU_CLASS_ARM9EJS: 528 case CPU_CLASS_ARM10E: 529 case CPU_CLASS_ARM10EJ: 530 case CPU_CLASS_SA1: 531 case CPU_CLASS_XSCALE: 532 case CPU_CLASS_ARM11J: 533 case CPU_CLASS_ARMV4: 534 case CPU_CLASS_CORTEX: 535 if ((ci->ci_ctrl & CPU_CONTROL_DC_ENABLE) == 0) 536 aprint_normal(" DC disabled"); 537 else 538 aprint_normal(" DC enabled"); 539 if ((ci->ci_ctrl & CPU_CONTROL_IC_ENABLE) == 0) 540 aprint_normal(" IC disabled"); 541 else 542 aprint_normal(" IC enabled"); 543 break; 544 default: 545 break; 546 } 547 if ((ci->ci_ctrl & CPU_CONTROL_WBUF_ENABLE) == 0) 548 aprint_normal(" WB disabled"); 549 else 550 aprint_normal(" WB enabled"); 551 552 if (ci->ci_ctrl & CPU_CONTROL_LABT_ENABLE) 553 aprint_normal(" LABT"); 554 else 555 aprint_normal(" EABT"); 556 557 if (ci->ci_ctrl & CPU_CONTROL_BPRD_ENABLE) 558 aprint_normal(" branch prediction enabled"); 559 560 aprint_normal("\n"); 561 562 /* Print cache info. */ 563 if (arm_picache_line_size == 0 && arm_pdcache_line_size == 0) 564 goto skip_pcache; 565 566 if (arm_pcache_unified) { 567 aprint_normal("%s: %dKB/%dB %d-way %s unified cache\n", 568 dv->dv_xname, arm_pdcache_size / 1024, 569 arm_pdcache_line_size, arm_pdcache_ways, 570 wtnames[arm_pcache_type]); 571 } else { 572 aprint_normal("%s: %dKB/%dB %d-way Instruction cache\n", 573 dv->dv_xname, arm_picache_size / 1024, 574 arm_picache_line_size, arm_picache_ways); 575 aprint_normal("%s: %dKB/%dB %d-way %s Data cache\n", 576 dv->dv_xname, arm_pdcache_size / 1024, 577 arm_pdcache_line_size, arm_pdcache_ways, 578 wtnames[arm_pcache_type]); 579 } 580 581 skip_pcache: 582 583 switch (cpu_class) { 584 #ifdef CPU_ARM2 585 case CPU_CLASS_ARM2: 586 #endif 587 #ifdef CPU_ARM250 588 case CPU_CLASS_ARM2AS: 589 #endif 590 #ifdef CPU_ARM3 591 case CPU_CLASS_ARM3: 592 #endif 593 #ifdef CPU_ARM6 594 case CPU_CLASS_ARM6: 595 #endif 596 #ifdef CPU_ARM7 597 case CPU_CLASS_ARM7: 598 #endif 599 #ifdef CPU_ARM7TDMI 600 case CPU_CLASS_ARM7TDMI: 601 #endif 602 #ifdef CPU_ARM8 603 case CPU_CLASS_ARM8: 604 #endif 605 #ifdef CPU_ARM9 606 case CPU_CLASS_ARM9TDMI: 607 #endif 608 #ifdef CPU_ARM9E 609 case CPU_CLASS_ARM9ES: 610 case CPU_CLASS_ARM9EJS: 611 #endif 612 #ifdef CPU_ARM10 613 case CPU_CLASS_ARM10E: 614 case CPU_CLASS_ARM10EJ: 615 #endif 616 #if defined(CPU_SA110) || defined(CPU_SA1100) || \ 617 defined(CPU_SA1110) || defined(CPU_IXP12X0) 618 case CPU_CLASS_SA1: 619 #endif 620 #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 621 defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425) 622 case CPU_CLASS_XSCALE: 623 #endif 624 #if defined(CPU_ARM11) 625 case CPU_CLASS_ARM11J: 626 #endif 627 #if defined(CPU_CORTEX) 628 case CPU_CLASS_CORTEX: 629 #endif 630 #if defined(CPU_FA526) 631 case CPU_CLASS_ARMV4: 632 #endif 633 break; 634 default: 635 if (cpu_classes[cpu_class].class_option == NULL) 636 aprint_error("%s: %s does not fully support this CPU." 637 "\n", dv->dv_xname, ostype); 638 else { 639 aprint_error("%s: This kernel does not fully support " 640 "this CPU.\n", dv->dv_xname); 641 aprint_normal("%s: Recompile with \"options %s\" to " 642 "correct this.\n", dv->dv_xname, 643 cpu_classes[cpu_class].class_option); 644 } 645 break; 646 } 647 648 } 649 650 /* End of cpu.c */ 651
Indexes created Fri Oct 17 00:09:41 GMT 2025