cpu.c revision 1.86.2.2
1 /* $NetBSD: cpu.c,v 1.86.2.2 2013/02/25 00:28:24 tls Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Mark Brinicombe. 5 * Copyright (c) 1995 Brini. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Brini. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * cpu.c 38 * 39 * Probing and configuration for the master CPU 40 * 41 * Created : 10/10/95 42 */ 43 44 #include "opt_armfpe.h" 45 #include "opt_multiprocessor.h" 46 47 #include <sys/param.h> 48 49 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.86.2.2 2013/02/25 00:28:24 tls Exp $"); 50 51 #include <sys/systm.h> 52 #include <sys/conf.h> 53 #include <sys/cpu.h> 54 #include <sys/device.h> 55 #include <sys/kmem.h> 56 #include <sys/proc.h> 57 58 #include <uvm/uvm_extern.h> 59 60 #include <arm/cpuconf.h> 61 #include <arm/undefined.h> 62 63 char cpu_model[256]; 64 extern const char *cpu_arch; 65 66 #ifdef MULTIPROCESSOR 67 volatile u_int arm_cpu_hatched = 0; 68 u_int arm_cpu_max = 0; 69 uint32_t arm_cpu_mbox __cacheline_aligned = 0; 70 uint32_t arm_cpu_marker __cacheline_aligned = 1; 71 #endif 72 73 /* Prototypes */ 74 void identify_arm_cpu(device_t dv, struct cpu_info *); 75 void identify_cortex_caches(device_t dv); 76 void identify_features(device_t dv); 77 78 /* 79 * Identify the master (boot) CPU 80 */ 81 82 void 83 cpu_attach(device_t dv, cpuid_t id) 84 { 85 const char * const xname = device_xname(dv); 86 struct cpu_info *ci; 87 88 if (id == 0) { 89 ci = curcpu(); 90 91 /* Get the CPU ID from coprocessor 15 */ 92 93 ci->ci_arm_cpuid = cpu_id(); 94 ci->ci_arm_cputype = ci->ci_arm_cpuid & CPU_ID_CPU_MASK; 95 ci->ci_arm_cpurev = ci->ci_arm_cpuid & CPU_ID_REVISION_MASK; 96 } else { 97 #ifdef MULTIPROCESSOR 98 KASSERT(cpu_info[id] == NULL); 99 ci = kmem_zalloc(sizeof(*ci), KM_SLEEP); 100 KASSERT(ci != NULL); 101 ci->ci_cpl = IPL_HIGH; 102 ci->ci_cpuid = id; 103 ci->ci_data.cpu_core_id = id; 104 ci->ci_data.cpu_cc_freq = cpu_info_store.ci_data.cpu_cc_freq; 105 ci->ci_arm_cpuid = cpu_info_store.ci_arm_cpuid; 106 ci->ci_arm_cputype = cpu_info_store.ci_arm_cputype; 107 ci->ci_arm_cpurev = cpu_info_store.ci_arm_cpurev; 108 cpu_info[ci->ci_cpuid] = ci; 109 if ((arm_cpu_hatched & (1 << id)) == 0) { 110 ci->ci_dev = dv; 111 dv->dv_private = ci; 112 aprint_naive(": disabled\n"); 113 aprint_normal(": disabled (unresponsive)\n"); 114 return; 115 } 116 #else 117 aprint_naive(": disabled\n"); 118 aprint_normal(": disabled (uniprocessor kernel)\n"); 119 return; 120 #endif 121 } 122 123 ci->ci_dev = dv; 124 dv->dv_private = ci; 125 126 evcnt_attach_dynamic(&ci->ci_arm700bugcount, EVCNT_TYPE_MISC, 127 NULL, xname, "arm700swibug"); 128 129 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_WRTBUF_0], EVCNT_TYPE_TRAP, 130 NULL, xname, "vector abort"); 131 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_WRTBUF_1], EVCNT_TYPE_TRAP, 132 NULL, xname, "terminal abort"); 133 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_BUSERR_0], EVCNT_TYPE_TRAP, 134 NULL, xname, "external linefetch abort (S)"); 135 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_BUSERR_1], EVCNT_TYPE_TRAP, 136 NULL, xname, "external linefetch abort (P)"); 137 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_BUSERR_2], EVCNT_TYPE_TRAP, 138 NULL, xname, "external non-linefetch abort (S)"); 139 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_BUSERR_3], EVCNT_TYPE_TRAP, 140 NULL, xname, "external non-linefetch abort (P)"); 141 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_BUSTRNL1], EVCNT_TYPE_TRAP, 142 NULL, xname, "external translation abort (L1)"); 143 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_BUSTRNL2], EVCNT_TYPE_TRAP, 144 NULL, xname, "external translation abort (L2)"); 145 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_ALIGN_0], EVCNT_TYPE_TRAP, 146 NULL, xname, "alignment abort (0)"); 147 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_ALIGN_1], EVCNT_TYPE_TRAP, 148 NULL, xname, "alignment abort (1)"); 149 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_TRANS_S], EVCNT_TYPE_TRAP, 150 NULL, xname, "translation abort (S)"); 151 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_TRANS_P], EVCNT_TYPE_TRAP, 152 NULL, xname, "translation abort (P)"); 153 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_DOMAIN_S], EVCNT_TYPE_TRAP, 154 NULL, xname, "domain abort (S)"); 155 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_DOMAIN_P], EVCNT_TYPE_TRAP, 156 NULL, xname, "domain abort (P)"); 157 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_PERM_S], EVCNT_TYPE_TRAP, 158 NULL, xname, "permission abort (S)"); 159 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_PERM_P], EVCNT_TYPE_TRAP, 160 NULL, xname, "permission abort (P)"); 161 162 #ifdef MULTIPROCESSOR 163 /* 164 * and we are done if this is a secondary processor. 165 */ 166 if (!CPU_IS_PRIMARY(ci)) { 167 aprint_naive(": %s\n", cpu_model); 168 aprint_normal(": %s\n", cpu_model); 169 mi_cpu_attach(ci); 170 return; 171 } 172 #endif 173 174 identify_arm_cpu(dv, ci); 175 176 #ifdef CPU_STRONGARM 177 if (ci->ci_arm_cputype == CPU_ID_SA110 && 178 ci->ci_arm_cpurev < 3) { 179 aprint_normal_dev(dv, "SA-110 with bugged STM^ instruction\n"); 180 } 181 #endif 182 183 #ifdef CPU_ARM8 184 if ((ci->ci_arm_cpuid & CPU_ID_CPU_MASK) == CPU_ID_ARM810) { 185 int clock = arm8_clock_config(0, 0); 186 char *fclk; 187 aprint_normal_dev(dv, "ARM810 cp15=%02x", clock); 188 aprint_normal(" clock:%s", (clock & 1) ? " dynamic" : ""); 189 aprint_normal("%s", (clock & 2) ? " sync" : ""); 190 switch ((clock >> 2) & 3) { 191 case 0: 192 fclk = "bus clock"; 193 break; 194 case 1: 195 fclk = "ref clock"; 196 break; 197 case 3: 198 fclk = "pll"; 199 break; 200 default: 201 fclk = "illegal"; 202 break; 203 } 204 aprint_normal(" fclk source=%s\n", fclk); 205 } 206 #endif 207 208 vfp_attach(); /* XXX SMP */ 209 } 210 211 enum cpu_class { 212 CPU_CLASS_NONE, 213 CPU_CLASS_ARM2, 214 CPU_CLASS_ARM2AS, 215 CPU_CLASS_ARM3, 216 CPU_CLASS_ARM6, 217 CPU_CLASS_ARM7, 218 CPU_CLASS_ARM7TDMI, 219 CPU_CLASS_ARM8, 220 CPU_CLASS_ARM9TDMI, 221 CPU_CLASS_ARM9ES, 222 CPU_CLASS_ARM9EJS, 223 CPU_CLASS_ARM10E, 224 CPU_CLASS_ARM10EJ, 225 CPU_CLASS_SA1, 226 CPU_CLASS_XSCALE, 227 CPU_CLASS_ARM11J, 228 CPU_CLASS_ARMV4, 229 CPU_CLASS_CORTEX, 230 }; 231 232 static const char * const generic_steppings[16] = { 233 "rev 0", "rev 1", "rev 2", "rev 3", 234 "rev 4", "rev 5", "rev 6", "rev 7", 235 "rev 8", "rev 9", "rev 10", "rev 11", 236 "rev 12", "rev 13", "rev 14", "rev 15", 237 }; 238 239 static const char * const pN_steppings[16] = { 240 "*p0", "*p1", "*p2", "*p3", "*p4", "*p5", "*p6", "*p7", 241 "*p8", "*p9", "*p10", "*p11", "*p12", "*p13", "*p14", "*p15", 242 }; 243 244 static const char * const sa110_steppings[16] = { 245 "rev 0", "step J", "step K", "step S", 246 "step T", "rev 5", "rev 6", "rev 7", 247 "rev 8", "rev 9", "rev 10", "rev 11", 248 "rev 12", "rev 13", "rev 14", "rev 15", 249 }; 250 251 static const char * const sa1100_steppings[16] = { 252 "rev 0", "step B", "step C", "rev 3", 253 "rev 4", "rev 5", "rev 6", "rev 7", 254 "step D", "step E", "rev 10" "step G", 255 "rev 12", "rev 13", "rev 14", "rev 15", 256 }; 257 258 static const char * const sa1110_steppings[16] = { 259 "step A-0", "rev 1", "rev 2", "rev 3", 260 "step B-0", "step B-1", "step B-2", "step B-3", 261 "step B-4", "step B-5", "rev 10", "rev 11", 262 "rev 12", "rev 13", "rev 14", "rev 15", 263 }; 264 265 static const char * const ixp12x0_steppings[16] = { 266 "(IXP1200 step A)", "(IXP1200 step B)", 267 "rev 2", "(IXP1200 step C)", 268 "(IXP1200 step D)", "(IXP1240/1250 step A)", 269 "(IXP1240 step B)", "(IXP1250 step B)", 270 "rev 8", "rev 9", "rev 10", "rev 11", 271 "rev 12", "rev 13", "rev 14", "rev 15", 272 }; 273 274 static const char * const xscale_steppings[16] = { 275 "step A-0", "step A-1", "step B-0", "step C-0", 276 "step D-0", "rev 5", "rev 6", "rev 7", 277 "rev 8", "rev 9", "rev 10", "rev 11", 278 "rev 12", "rev 13", "rev 14", "rev 15", 279 }; 280 281 static const char * const i80321_steppings[16] = { 282 "step A-0", "step B-0", "rev 2", "rev 3", 283 "rev 4", "rev 5", "rev 6", "rev 7", 284 "rev 8", "rev 9", "rev 10", "rev 11", 285 "rev 12", "rev 13", "rev 14", "rev 15", 286 }; 287 288 static const char * const i80219_steppings[16] = { 289 "step A-0", "rev 1", "rev 2", "rev 3", 290 "rev 4", "rev 5", "rev 6", "rev 7", 291 "rev 8", "rev 9", "rev 10", "rev 11", 292 "rev 12", "rev 13", "rev 14", "rev 15", 293 }; 294 295 /* Steppings for PXA2[15]0 */ 296 static const char * const pxa2x0_steppings[16] = { 297 "step A-0", "step A-1", "step B-0", "step B-1", 298 "step B-2", "step C-0", "rev 6", "rev 7", 299 "rev 8", "rev 9", "rev 10", "rev 11", 300 "rev 12", "rev 13", "rev 14", "rev 15", 301 }; 302 303 /* Steppings for PXA255/26x. 304 * rev 5: PXA26x B0, rev 6: PXA255 A0 305 */ 306 static const char * const pxa255_steppings[16] = { 307 "rev 0", "rev 1", "rev 2", "step A-0", 308 "rev 4", "step B-0", "step A-0", "rev 7", 309 "rev 8", "rev 9", "rev 10", "rev 11", 310 "rev 12", "rev 13", "rev 14", "rev 15", 311 }; 312 313 /* Stepping for PXA27x */ 314 static const char * const pxa27x_steppings[16] = { 315 "step A-0", "step A-1", "step B-0", "step B-1", 316 "step C-0", "rev 5", "rev 6", "rev 7", 317 "rev 8", "rev 9", "rev 10", "rev 11", 318 "rev 12", "rev 13", "rev 14", "rev 15", 319 }; 320 321 static const char * const ixp425_steppings[16] = { 322 "step 0", "rev 1", "rev 2", "rev 3", 323 "rev 4", "rev 5", "rev 6", "rev 7", 324 "rev 8", "rev 9", "rev 10", "rev 11", 325 "rev 12", "rev 13", "rev 14", "rev 15", 326 }; 327 328 struct cpuidtab { 329 uint32_t cpuid; 330 enum cpu_class cpu_class; 331 const char *cpu_classname; 332 const char * const *cpu_steppings; 333 char cpu_arch[8]; 334 }; 335 336 const struct cpuidtab cpuids[] = { 337 { CPU_ID_ARM2, CPU_CLASS_ARM2, "ARM2", 338 generic_steppings, "2" }, 339 { CPU_ID_ARM250, CPU_CLASS_ARM2AS, "ARM250", 340 generic_steppings, "2" }, 341 342 { CPU_ID_ARM3, CPU_CLASS_ARM3, "ARM3", 343 generic_steppings, "2A" }, 344 345 { CPU_ID_ARM600, CPU_CLASS_ARM6, "ARM600", 346 generic_steppings, "3" }, 347 { CPU_ID_ARM610, CPU_CLASS_ARM6, "ARM610", 348 generic_steppings, "3" }, 349 { CPU_ID_ARM620, CPU_CLASS_ARM6, "ARM620", 350 generic_steppings, "3" }, 351 352 { CPU_ID_ARM700, CPU_CLASS_ARM7, "ARM700", 353 generic_steppings, "3" }, 354 { CPU_ID_ARM710, CPU_CLASS_ARM7, "ARM710", 355 generic_steppings, "3" }, 356 { CPU_ID_ARM7500, CPU_CLASS_ARM7, "ARM7500", 357 generic_steppings, "3" }, 358 { CPU_ID_ARM710A, CPU_CLASS_ARM7, "ARM710a", 359 generic_steppings, "3" }, 360 { CPU_ID_ARM7500FE, CPU_CLASS_ARM7, "ARM7500FE", 361 generic_steppings, "3" }, 362 363 { CPU_ID_ARM810, CPU_CLASS_ARM8, "ARM810", 364 generic_steppings, "4" }, 365 366 { CPU_ID_SA110, CPU_CLASS_SA1, "SA-110", 367 sa110_steppings, "4" }, 368 { CPU_ID_SA1100, CPU_CLASS_SA1, "SA-1100", 369 sa1100_steppings, "4" }, 370 { CPU_ID_SA1110, CPU_CLASS_SA1, "SA-1110", 371 sa1110_steppings, "4" }, 372 373 { CPU_ID_FA526, CPU_CLASS_ARMV4, "FA526", 374 generic_steppings, "4" }, 375 376 { CPU_ID_IXP1200, CPU_CLASS_SA1, "IXP1200", 377 ixp12x0_steppings, "4" }, 378 379 { CPU_ID_ARM710T, CPU_CLASS_ARM7TDMI, "ARM710T", 380 generic_steppings, "4T" }, 381 { CPU_ID_ARM720T, CPU_CLASS_ARM7TDMI, "ARM720T", 382 generic_steppings, "4T" }, 383 { CPU_ID_ARM740T8K, CPU_CLASS_ARM7TDMI, "ARM740T (8 KB cache)", 384 generic_steppings, "4T" }, 385 { CPU_ID_ARM740T4K, CPU_CLASS_ARM7TDMI, "ARM740T (4 KB cache)", 386 generic_steppings, "4T" }, 387 { CPU_ID_ARM920T, CPU_CLASS_ARM9TDMI, "ARM920T", 388 generic_steppings, "4T" }, 389 { CPU_ID_ARM922T, CPU_CLASS_ARM9TDMI, "ARM922T", 390 generic_steppings, "4T" }, 391 { CPU_ID_ARM940T, CPU_CLASS_ARM9TDMI, "ARM940T", 392 generic_steppings, "4T" }, 393 { CPU_ID_TI925T, CPU_CLASS_ARM9TDMI, "TI ARM925T", 394 generic_steppings, "4T" }, 395 396 { CPU_ID_ARM946ES, CPU_CLASS_ARM9ES, "ARM946E-S", 397 generic_steppings, "5TE" }, 398 { CPU_ID_ARM966ES, CPU_CLASS_ARM9ES, "ARM966E-S", 399 generic_steppings, "5TE" }, 400 { CPU_ID_ARM966ESR1, CPU_CLASS_ARM9ES, "ARM966E-S", 401 generic_steppings, "5TE" }, 402 { CPU_ID_MV88SV131, CPU_CLASS_ARM9ES, "Sheeva 88SV131", 403 generic_steppings, "5TE" }, 404 { CPU_ID_MV88FR571_VD, CPU_CLASS_ARM9ES, "Sheeva 88FR571-vd", 405 generic_steppings, "5TE" }, 406 407 { CPU_ID_80200, CPU_CLASS_XSCALE, "i80200", 408 xscale_steppings, "5TE" }, 409 410 { CPU_ID_80321_400, CPU_CLASS_XSCALE, "i80321 400MHz", 411 i80321_steppings, "5TE" }, 412 { CPU_ID_80321_600, CPU_CLASS_XSCALE, "i80321 600MHz", 413 i80321_steppings, "5TE" }, 414 { CPU_ID_80321_400_B0, CPU_CLASS_XSCALE, "i80321 400MHz", 415 i80321_steppings, "5TE" }, 416 { CPU_ID_80321_600_B0, CPU_CLASS_XSCALE, "i80321 600MHz", 417 i80321_steppings, "5TE" }, 418 419 { CPU_ID_80219_400, CPU_CLASS_XSCALE, "i80219 400MHz", 420 i80219_steppings, "5TE" }, 421 { CPU_ID_80219_600, CPU_CLASS_XSCALE, "i80219 600MHz", 422 i80219_steppings, "5TE" }, 423 424 { CPU_ID_PXA27X, CPU_CLASS_XSCALE, "PXA27x", 425 pxa27x_steppings, "5TE" }, 426 { CPU_ID_PXA250A, CPU_CLASS_XSCALE, "PXA250", 427 pxa2x0_steppings, "5TE" }, 428 { CPU_ID_PXA210A, CPU_CLASS_XSCALE, "PXA210", 429 pxa2x0_steppings, "5TE" }, 430 { CPU_ID_PXA250B, CPU_CLASS_XSCALE, "PXA250", 431 pxa2x0_steppings, "5TE" }, 432 { CPU_ID_PXA210B, CPU_CLASS_XSCALE, "PXA210", 433 pxa2x0_steppings, "5TE" }, 434 { CPU_ID_PXA250C, CPU_CLASS_XSCALE, "PXA255/26x", 435 pxa255_steppings, "5TE" }, 436 { CPU_ID_PXA210C, CPU_CLASS_XSCALE, "PXA210", 437 pxa2x0_steppings, "5TE" }, 438 439 { CPU_ID_IXP425_533, CPU_CLASS_XSCALE, "IXP425 533MHz", 440 ixp425_steppings, "5TE" }, 441 { CPU_ID_IXP425_400, CPU_CLASS_XSCALE, "IXP425 400MHz", 442 ixp425_steppings, "5TE" }, 443 { CPU_ID_IXP425_266, CPU_CLASS_XSCALE, "IXP425 266MHz", 444 ixp425_steppings, "5TE" }, 445 446 { CPU_ID_ARM1020E, CPU_CLASS_ARM10E, "ARM1020E", 447 generic_steppings, "5TE" }, 448 { CPU_ID_ARM1022ES, CPU_CLASS_ARM10E, "ARM1022E-S", 449 generic_steppings, "5TE" }, 450 451 { CPU_ID_ARM1026EJS, CPU_CLASS_ARM10EJ, "ARM1026EJ-S", 452 generic_steppings, "5TEJ" }, 453 { CPU_ID_ARM926EJS, CPU_CLASS_ARM9EJS, "ARM926EJ-S", 454 generic_steppings, "5TEJ" }, 455 456 { CPU_ID_ARM1136JS, CPU_CLASS_ARM11J, "ARM1136J-S r0", 457 pN_steppings, "6J" }, 458 { CPU_ID_ARM1136JSR1, CPU_CLASS_ARM11J, "ARM1136J-S r1", 459 pN_steppings, "6J" }, 460 #if 0 461 /* The ARM1156T2-S only has a memory protection unit */ 462 { CPU_ID_ARM1156T2S, CPU_CLASS_ARM11J, "ARM1156T2-S r0", 463 pN_steppings, "6T2" }, 464 #endif 465 { CPU_ID_ARM1176JZS, CPU_CLASS_ARM11J, "ARM1176JZ-S r0", 466 pN_steppings, "6ZK" }, 467 468 { CPU_ID_ARM11MPCORE, CPU_CLASS_ARM11J, "ARM11 MPCore", 469 generic_steppings, "6K" }, 470 471 { CPU_ID_CORTEXA5R0, CPU_CLASS_CORTEX, "Cortex-A5 r0", 472 pN_steppings, "7A" }, 473 { CPU_ID_CORTEXA8R1, CPU_CLASS_CORTEX, "Cortex-A8 r1", 474 pN_steppings, "7A" }, 475 { CPU_ID_CORTEXA8R2, CPU_CLASS_CORTEX, "Cortex-A8 r2", 476 pN_steppings, "7A" }, 477 { CPU_ID_CORTEXA8R3, CPU_CLASS_CORTEX, "Cortex-A8 r3", 478 pN_steppings, "7A" }, 479 { CPU_ID_CORTEXA9R2, CPU_CLASS_CORTEX, "Cortex-A9 r2", 480 pN_steppings, "7A" }, 481 { CPU_ID_CORTEXA9R3, CPU_CLASS_CORTEX, "Cortex-A9 r3", 482 pN_steppings, "7A" }, 483 { CPU_ID_CORTEXA9R4, CPU_CLASS_CORTEX, "Cortex-A9 r4", 484 pN_steppings, "7A" }, 485 { CPU_ID_CORTEXA15R2, CPU_CLASS_CORTEX, "Cortex-A15 r2", 486 pN_steppings, "7A" }, 487 { CPU_ID_CORTEXA15R3, CPU_CLASS_CORTEX, "Cortex-A15 r3", 488 pN_steppings, "7A" }, 489 490 { 0, CPU_CLASS_NONE, NULL, NULL, "" } 491 }; 492 493 struct cpu_classtab { 494 const char *class_name; 495 const char *class_option; 496 }; 497 498 const struct cpu_classtab cpu_classes[] = { 499 [CPU_CLASS_NONE] = { "unknown", NULL }, 500 [CPU_CLASS_ARM2] = { "ARM2", "CPU_ARM2" }, 501 [CPU_CLASS_ARM2AS] = { "ARM2as", "CPU_ARM250" }, 502 [CPU_CLASS_ARM3] = { "ARM3", "CPU_ARM3" }, 503 [CPU_CLASS_ARM6] = { "ARM6", "CPU_ARM6" }, 504 [CPU_CLASS_ARM7] = { "ARM7", "CPU_ARM7" }, 505 [CPU_CLASS_ARM7TDMI] = { "ARM7TDMI", "CPU_ARM7TDMI" }, 506 [CPU_CLASS_ARM8] = { "ARM8", "CPU_ARM8" }, 507 [CPU_CLASS_ARM9TDMI] = { "ARM9TDMI", NULL }, 508 [CPU_CLASS_ARM9ES] = { "ARM9E-S", "CPU_ARM9E" }, 509 [CPU_CLASS_ARM9EJS] = { "ARM9EJ-S", "CPU_ARM9E" }, 510 [CPU_CLASS_ARM10E] = { "ARM10E", "CPU_ARM10" }, 511 [CPU_CLASS_ARM10EJ] = { "ARM10EJ", "CPU_ARM10" }, 512 [CPU_CLASS_SA1] = { "SA-1", "CPU_SA110" }, 513 [CPU_CLASS_XSCALE] = { "XScale", "CPU_XSCALE_..." }, 514 [CPU_CLASS_ARM11J] = { "ARM11J", "CPU_ARM11" }, 515 [CPU_CLASS_ARMV4] = { "ARMv4", "CPU_ARMV4" }, 516 [CPU_CLASS_CORTEX] = { "Cortex", "CPU_CORTEX" }, 517 }; 518 519 /* 520 * Report the type of the specified arm processor. This uses the generic and 521 * arm specific information in the CPU structure to identify the processor. 522 * The remaining fields in the CPU structure are filled in appropriately. 523 */ 524 525 static const char * const wtnames[] = { 526 "write-through", 527 "write-back", 528 "write-back", 529 "**unknown 3**", 530 "**unknown 4**", 531 "write-back-locking", /* XXX XScale-specific? */ 532 "write-back-locking-A", 533 "write-back-locking-B", 534 "**unknown 8**", 535 "**unknown 9**", 536 "**unknown 10**", 537 "**unknown 11**", 538 "**unknown 12**", 539 "**unknown 13**", 540 "write-back-locking-C", 541 "write-back-locking-D", 542 }; 543 544 static void 545 print_cache_info(device_t dv, struct arm_cache_info *info, u_int level) 546 { 547 if (info->cache_unified) { 548 aprint_normal_dev(dv, "%dKB/%dB %d-way %s L%u Unified cache\n", 549 info->dcache_size / 1024, 550 info->dcache_line_size, info->dcache_ways, 551 wtnames[info->cache_type], level + 1); 552 } else { 553 aprint_normal_dev(dv, "%dKB/%dB %d-way L%u Instruction cache\n", 554 info->icache_size / 1024, 555 info->icache_line_size, info->icache_ways, level + 1); 556 aprint_normal_dev(dv, "%dKB/%dB %d-way %s L%u Data cache\n", 557 info->dcache_size / 1024, 558 info->dcache_line_size, info->dcache_ways, 559 wtnames[info->cache_type], level + 1); 560 } 561 } 562 563 void 564 identify_arm_cpu(device_t dv, struct cpu_info *ci) 565 { 566 enum cpu_class cpu_class = CPU_CLASS_NONE; 567 const u_int cpuid = ci->ci_arm_cpuid; 568 const char * const xname = device_xname(dv); 569 const char *steppingstr; 570 int i; 571 572 if (cpuid == 0) { 573 aprint_error("Processor failed probe - no CPU ID\n"); 574 return; 575 } 576 577 for (i = 0; cpuids[i].cpuid != 0; i++) 578 if (cpuids[i].cpuid == (cpuid & CPU_ID_CPU_MASK)) { 579 cpu_class = cpuids[i].cpu_class; 580 cpu_arch = cpuids[i].cpu_arch; 581 steppingstr = cpuids[i].cpu_steppings[cpuid & 582 CPU_ID_REVISION_MASK]; 583 snprintf(cpu_model, sizeof(cpu_model), 584 "%s%s%s (%s V%s core)", cpuids[i].cpu_classname, 585 steppingstr[0] == '*' ? "" : " ", 586 &steppingstr[steppingstr[0] == '*'], 587 cpu_classes[cpu_class].class_name, 588 cpu_arch); 589 break; 590 } 591 592 if (cpuids[i].cpuid == 0) 593 snprintf(cpu_model, sizeof(cpu_model), 594 "unknown CPU (ID = 0x%x)", cpuid); 595 596 if (ci->ci_data.cpu_cc_freq != 0) { 597 char freqbuf[8]; 598 humanize_number(freqbuf, sizeof(freqbuf), ci->ci_data.cpu_cc_freq, 599 "Hz", 1000); 600 601 aprint_naive(": %s %s\n", freqbuf, cpu_model); 602 aprint_normal(": %s %s\n", freqbuf, cpu_model); 603 } else { 604 aprint_naive(": %s\n", cpu_model); 605 aprint_normal(": %s\n", cpu_model); 606 } 607 608 aprint_normal("%s:", xname); 609 610 switch (cpu_class) { 611 case CPU_CLASS_ARM6: 612 case CPU_CLASS_ARM7: 613 case CPU_CLASS_ARM7TDMI: 614 case CPU_CLASS_ARM8: 615 if ((ci->ci_ctrl & CPU_CONTROL_IDC_ENABLE) == 0) 616 aprint_normal(" IDC disabled"); 617 else 618 aprint_normal(" IDC enabled"); 619 break; 620 case CPU_CLASS_ARM9TDMI: 621 case CPU_CLASS_ARM9ES: 622 case CPU_CLASS_ARM9EJS: 623 case CPU_CLASS_ARM10E: 624 case CPU_CLASS_ARM10EJ: 625 case CPU_CLASS_SA1: 626 case CPU_CLASS_XSCALE: 627 case CPU_CLASS_ARM11J: 628 case CPU_CLASS_ARMV4: 629 case CPU_CLASS_CORTEX: 630 if ((ci->ci_ctrl & CPU_CONTROL_DC_ENABLE) == 0) 631 aprint_normal(" DC disabled"); 632 else 633 aprint_normal(" DC enabled"); 634 if ((ci->ci_ctrl & CPU_CONTROL_IC_ENABLE) == 0) 635 aprint_normal(" IC disabled"); 636 else 637 aprint_normal(" IC enabled"); 638 break; 639 default: 640 break; 641 } 642 if ((ci->ci_ctrl & CPU_CONTROL_WBUF_ENABLE) == 0) 643 aprint_normal(" WB disabled"); 644 else 645 aprint_normal(" WB enabled"); 646 647 if (ci->ci_ctrl & CPU_CONTROL_LABT_ENABLE) 648 aprint_normal(" LABT"); 649 else 650 aprint_normal(" EABT"); 651 652 if (ci->ci_ctrl & CPU_CONTROL_BPRD_ENABLE) 653 aprint_normal(" branch prediction enabled"); 654 655 aprint_normal("\n"); 656 657 if (CPU_ID_CORTEX_P(cpuid) || CPU_ID_ARM11_P(cpuid)) { 658 identify_features(dv); 659 } 660 661 /* Print cache info. */ 662 if (arm_pcache.icache_line_size != 0 || arm_pcache.dcache_line_size != 0) { 663 print_cache_info(dv, &arm_pcache, 0); 664 } 665 if (arm_scache.icache_line_size != 0 || arm_scache.dcache_line_size != 0) { 666 print_cache_info(dv, &arm_scache, 1); 667 } 668 669 670 switch (cpu_class) { 671 #ifdef CPU_ARM2 672 case CPU_CLASS_ARM2: 673 #endif 674 #ifdef CPU_ARM250 675 case CPU_CLASS_ARM2AS: 676 #endif 677 #ifdef CPU_ARM3 678 case CPU_CLASS_ARM3: 679 #endif 680 #ifdef CPU_ARM6 681 case CPU_CLASS_ARM6: 682 #endif 683 #ifdef CPU_ARM7 684 case CPU_CLASS_ARM7: 685 #endif 686 #ifdef CPU_ARM7TDMI 687 case CPU_CLASS_ARM7TDMI: 688 #endif 689 #ifdef CPU_ARM8 690 case CPU_CLASS_ARM8: 691 #endif 692 #ifdef CPU_ARM9 693 case CPU_CLASS_ARM9TDMI: 694 #endif 695 #if defined(CPU_ARM9E) || defined(CPU_SHEEVA) 696 case CPU_CLASS_ARM9ES: 697 case CPU_CLASS_ARM9EJS: 698 #endif 699 #ifdef CPU_ARM10 700 case CPU_CLASS_ARM10E: 701 case CPU_CLASS_ARM10EJ: 702 #endif 703 #if defined(CPU_SA110) || defined(CPU_SA1100) || \ 704 defined(CPU_SA1110) || defined(CPU_IXP12X0) 705 case CPU_CLASS_SA1: 706 #endif 707 #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 708 defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425) 709 case CPU_CLASS_XSCALE: 710 #endif 711 #if defined(CPU_ARM11) 712 case CPU_CLASS_ARM11J: 713 #endif 714 #if defined(CPU_CORTEX) 715 case CPU_CLASS_CORTEX: 716 #endif 717 #if defined(CPU_FA526) 718 case CPU_CLASS_ARMV4: 719 #endif 720 break; 721 default: 722 if (cpu_classes[cpu_class].class_option == NULL) { 723 aprint_error_dev(dv, "%s does not fully support this CPU.\n", 724 ostype); 725 } else { 726 aprint_error_dev(dv, "This kernel does not fully support " 727 "this CPU.\n"); 728 aprint_normal_dev(dv, "Recompile with \"options %s\" to " 729 "correct this.\n", cpu_classes[cpu_class].class_option); 730 } 731 break; 732 } 733 } 734 735 extern int cpu_instruction_set_attributes[6]; 736 extern int cpu_memory_model_features[4]; 737 extern int cpu_processor_features[2]; 738 extern int cpu_simd_present; 739 extern int cpu_simdex_present; 740 741 void 742 identify_features(device_t dv) 743 { 744 cpu_instruction_set_attributes[0] = armreg_isar0_read(); 745 cpu_instruction_set_attributes[1] = armreg_isar1_read(); 746 cpu_instruction_set_attributes[2] = armreg_isar2_read(); 747 cpu_instruction_set_attributes[3] = armreg_isar3_read(); 748 cpu_instruction_set_attributes[4] = armreg_isar4_read(); 749 cpu_instruction_set_attributes[5] = armreg_isar5_read(); 750 751 cpu_simd_present = 752 ((cpu_instruction_set_attributes[3] >> 4) & 0x0f) >= 3; 753 cpu_simdex_present = cpu_simd_present 754 && ((cpu_instruction_set_attributes[1] >> 12) & 0x0f) >= 2; 755 756 cpu_memory_model_features[0] = armreg_mmfr0_read(); 757 cpu_memory_model_features[1] = armreg_mmfr1_read(); 758 cpu_memory_model_features[2] = armreg_mmfr2_read(); 759 cpu_memory_model_features[3] = armreg_mmfr3_read(); 760 761 if (__SHIFTOUT(cpu_memory_model_features[3], __BITS(23,20))) { 762 /* 763 * Updates to the translation tables do not require a clean 764 * to the point of unification to ensure visibility by 765 * subsequent translation table walks. 766 */ 767 pmap_needs_pte_sync = 0; 768 } 769 770 cpu_processor_features[0] = armreg_pfr0_read(); 771 cpu_processor_features[1] = armreg_pfr1_read(); 772 773 aprint_verbose_dev(dv, 774 "isar: [0]=%#x [1]=%#x [2]=%#x [3]=%#x, [4]=%#x, [5]=%#x\n", 775 cpu_instruction_set_attributes[0], 776 cpu_instruction_set_attributes[1], 777 cpu_instruction_set_attributes[2], 778 cpu_instruction_set_attributes[3], 779 cpu_instruction_set_attributes[4], 780 cpu_instruction_set_attributes[5]); 781 aprint_verbose_dev(dv, 782 "mmfr: [0]=%#x [1]=%#x [2]=%#x [3]=%#x\n", 783 cpu_memory_model_features[0], cpu_memory_model_features[1], 784 cpu_memory_model_features[2], cpu_memory_model_features[3]); 785 aprint_verbose_dev(dv, 786 "pfr: [0]=%#x [1]=%#x\n", 787 cpu_processor_features[0], cpu_processor_features[1]); 788 } 789
Indexes created Fri Oct 17 03:10:13 GMT 2025