cpu.c revision 1.90
1 /* $NetBSD: cpu.c,v 1.90 2012/11/30 08:15:45 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Mark Brinicombe. 5 * Copyright (c) 1995 Brini. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Brini. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * cpu.c 38 * 39 * Probing and configuration for the master CPU 40 * 41 * Created : 10/10/95 42 */ 43 44 #include "opt_armfpe.h" 45 #include "opt_multiprocessor.h" 46 47 #include <sys/param.h> 48 49 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.90 2012/11/30 08:15:45 msaitoh Exp $"); 50 51 #include <sys/systm.h> 52 #include <sys/conf.h> 53 #include <sys/cpu.h> 54 #include <sys/device.h> 55 #include <sys/kmem.h> 56 #include <sys/proc.h> 57 58 #include <uvm/uvm_extern.h> 59 60 #include <arm/cpuconf.h> 61 #include <arm/undefined.h> 62 63 #ifdef ARMFPE 64 #include <machine/bootconfig.h> /* For boot args */ 65 #include <arm/fpe-arm/armfpe.h> 66 #endif 67 68 char cpu_model[256]; 69 70 #ifdef MULTIPROCESSOR 71 volatile u_int arm_cpu_hatched = 0; 72 u_int arm_cpu_max = 0; 73 uint32_t arm_cpu_mbox __cacheline_aligned = 0; 74 uint32_t arm_cpu_marker __cacheline_aligned = 1; 75 #endif 76 77 /* Prototypes */ 78 void identify_arm_cpu(device_t dv, struct cpu_info *); 79 void identify_cortex_caches(device_t dv); 80 void identify_features(device_t dv); 81 82 /* 83 * Identify the master (boot) CPU 84 */ 85 86 void 87 cpu_attach(device_t dv, cpuid_t id) 88 { 89 const char * const xname = device_xname(dv); 90 struct cpu_info *ci; 91 92 if (id == 0) { 93 ci = curcpu(); 94 95 /* Get the CPU ID from coprocessor 15 */ 96 97 ci->ci_arm_cpuid = cpu_id(); 98 ci->ci_arm_cputype = ci->ci_arm_cpuid & CPU_ID_CPU_MASK; 99 ci->ci_arm_cpurev = ci->ci_arm_cpuid & CPU_ID_REVISION_MASK; 100 } else { 101 #ifdef MULTIPROCESSOR 102 KASSERT(cpu_info[id] == NULL); 103 ci = kmem_zalloc(sizeof(*ci), KM_SLEEP); 104 KASSERT(ci != NULL); 105 ci->ci_cpl = IPL_HIGH; 106 ci->ci_cpuid = id; 107 ci->ci_data.cpu_core_id = id; 108 ci->ci_data.cpu_cc_freq = cpu_info_store.ci_data.cpu_cc_freq; 109 ci->ci_arm_cpuid = cpu_info_store.ci_arm_cpuid; 110 ci->ci_arm_cputype = cpu_info_store.ci_arm_cputype; 111 ci->ci_arm_cpurev = cpu_info_store.ci_arm_cpurev; 112 cpu_info[ci->ci_cpuid] = ci; 113 if ((arm_cpu_hatched & (1 << id)) == 0) { 114 ci->ci_dev = dv; 115 dv->dv_private = ci; 116 aprint_naive(": disabled\n"); 117 aprint_normal(": disabled (unresponsive)\n"); 118 return; 119 } 120 #else 121 aprint_naive(": disabled\n"); 122 aprint_normal(": disabled (uniprocessor kernel)\n"); 123 return; 124 #endif 125 } 126 127 ci->ci_dev = dv; 128 dv->dv_private = ci; 129 130 evcnt_attach_dynamic(&ci->ci_arm700bugcount, EVCNT_TYPE_MISC, 131 NULL, xname, "arm700swibug"); 132 133 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_WRTBUF_0], EVCNT_TYPE_TRAP, 134 NULL, xname, "vector abort"); 135 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_WRTBUF_1], EVCNT_TYPE_TRAP, 136 NULL, xname, "terminal abort"); 137 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_BUSERR_0], EVCNT_TYPE_TRAP, 138 NULL, xname, "external linefetch abort (S)"); 139 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_BUSERR_1], EVCNT_TYPE_TRAP, 140 NULL, xname, "external linefetch abort (P)"); 141 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_BUSERR_2], EVCNT_TYPE_TRAP, 142 NULL, xname, "external non-linefetch abort (S)"); 143 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_BUSERR_3], EVCNT_TYPE_TRAP, 144 NULL, xname, "external non-linefetch abort (P)"); 145 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_BUSTRNL1], EVCNT_TYPE_TRAP, 146 NULL, xname, "external translation abort (L1)"); 147 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_BUSTRNL2], EVCNT_TYPE_TRAP, 148 NULL, xname, "external translation abort (L2)"); 149 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_ALIGN_0], EVCNT_TYPE_TRAP, 150 NULL, xname, "alignment abort (0)"); 151 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_ALIGN_1], EVCNT_TYPE_TRAP, 152 NULL, xname, "alignment abort (1)"); 153 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_TRANS_S], EVCNT_TYPE_TRAP, 154 NULL, xname, "translation abort (S)"); 155 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_TRANS_P], EVCNT_TYPE_TRAP, 156 NULL, xname, "translation abort (P)"); 157 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_DOMAIN_S], EVCNT_TYPE_TRAP, 158 NULL, xname, "domain abort (S)"); 159 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_DOMAIN_P], EVCNT_TYPE_TRAP, 160 NULL, xname, "domain abort (P)"); 161 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_PERM_S], EVCNT_TYPE_TRAP, 162 NULL, xname, "permission abort (S)"); 163 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_PERM_P], EVCNT_TYPE_TRAP, 164 NULL, xname, "permission abort (P)"); 165 166 #ifdef MULTIPROCESSOR 167 /* 168 * and we are done if this is a secondary processor. 169 */ 170 if (!CPU_IS_PRIMARY(ci)) { 171 aprint_naive(": %s\n", cpu_model); 172 aprint_normal(": %s\n", cpu_model); 173 mi_cpu_attach(ci); 174 return; 175 } 176 #endif 177 178 identify_arm_cpu(dv, ci); 179 180 #ifdef CPU_STRONGARM 181 if (ci->ci_arm_cputype == CPU_ID_SA110 && 182 ci->ci_arm_cpurev < 3) { 183 aprint_normal_dev(dv, "SA-110 with bugged STM^ instruction\n"); 184 } 185 #endif 186 187 #ifdef CPU_ARM8 188 if ((ci->ci_arm_cpuid & CPU_ID_CPU_MASK) == CPU_ID_ARM810) { 189 int clock = arm8_clock_config(0, 0); 190 char *fclk; 191 aprint_normal_dev(dv, "ARM810 cp15=%02x", clock); 192 aprint_normal(" clock:%s", (clock & 1) ? " dynamic" : ""); 193 aprint_normal("%s", (clock & 2) ? " sync" : ""); 194 switch ((clock >> 2) & 3) { 195 case 0: 196 fclk = "bus clock"; 197 break; 198 case 1: 199 fclk = "ref clock"; 200 break; 201 case 3: 202 fclk = "pll"; 203 break; 204 default: 205 fclk = "illegal"; 206 break; 207 } 208 aprint_normal(" fclk source=%s\n", fclk); 209 } 210 #endif 211 212 #ifdef ARMFPE 213 /* 214 * Ok now we test for an FPA 215 * At this point no floating point emulator has been installed. 216 * This means any FP instruction will cause undefined exception. 217 * We install a temporay coproc 1 handler which will modify 218 * undefined_test if it is called. 219 * We then try to read the FP status register. If undefined_test 220 * has been decremented then the instruction was not handled by 221 * an FPA so we know the FPA is missing. If undefined_test is 222 * still 1 then we know the instruction was handled by an FPA. 223 * We then remove our test handler and look at the 224 * FP status register for identification. 225 */ 226 227 /* 228 * Ok if ARMFPE is defined and the boot options request the 229 * ARM FPE then it will be installed as the FPE. 230 * This is just while I work on integrating the new FPE. 231 * It means the new FPE gets installed if compiled int (ARMFPE 232 * defined) and also gives me a on/off option when I boot in 233 * case the new FPE is causing panics. 234 */ 235 236 237 int usearmfpe = 1; 238 if (boot_args) 239 get_bootconf_option(boot_args, "armfpe", 240 BOOTOPT_TYPE_BOOLEAN, &usearmfpe); 241 if (usearmfpe) 242 initialise_arm_fpe(); 243 #endif 244 245 vfp_attach(); /* XXX SMP */ 246 } 247 248 enum cpu_class { 249 CPU_CLASS_NONE, 250 CPU_CLASS_ARM2, 251 CPU_CLASS_ARM2AS, 252 CPU_CLASS_ARM3, 253 CPU_CLASS_ARM6, 254 CPU_CLASS_ARM7, 255 CPU_CLASS_ARM7TDMI, 256 CPU_CLASS_ARM8, 257 CPU_CLASS_ARM9TDMI, 258 CPU_CLASS_ARM9ES, 259 CPU_CLASS_ARM9EJS, 260 CPU_CLASS_ARM10E, 261 CPU_CLASS_ARM10EJ, 262 CPU_CLASS_SA1, 263 CPU_CLASS_XSCALE, 264 CPU_CLASS_ARM11J, 265 CPU_CLASS_ARMV4, 266 CPU_CLASS_CORTEX, 267 }; 268 269 static const char * const generic_steppings[16] = { 270 "rev 0", "rev 1", "rev 2", "rev 3", 271 "rev 4", "rev 5", "rev 6", "rev 7", 272 "rev 8", "rev 9", "rev 10", "rev 11", 273 "rev 12", "rev 13", "rev 14", "rev 15", 274 }; 275 276 static const char * const pN_steppings[16] = { 277 "*p0", "*p1", "*p2", "*p3", "*p4", "*p5", "*p6", "*p7", 278 "*p8", "*p9", "*p10", "*p11", "*p12", "*p13", "*p14", "*p15", 279 }; 280 281 static const char * const sa110_steppings[16] = { 282 "rev 0", "step J", "step K", "step S", 283 "step T", "rev 5", "rev 6", "rev 7", 284 "rev 8", "rev 9", "rev 10", "rev 11", 285 "rev 12", "rev 13", "rev 14", "rev 15", 286 }; 287 288 static const char * const sa1100_steppings[16] = { 289 "rev 0", "step B", "step C", "rev 3", 290 "rev 4", "rev 5", "rev 6", "rev 7", 291 "step D", "step E", "rev 10" "step G", 292 "rev 12", "rev 13", "rev 14", "rev 15", 293 }; 294 295 static const char * const sa1110_steppings[16] = { 296 "step A-0", "rev 1", "rev 2", "rev 3", 297 "step B-0", "step B-1", "step B-2", "step B-3", 298 "step B-4", "step B-5", "rev 10", "rev 11", 299 "rev 12", "rev 13", "rev 14", "rev 15", 300 }; 301 302 static const char * const ixp12x0_steppings[16] = { 303 "(IXP1200 step A)", "(IXP1200 step B)", 304 "rev 2", "(IXP1200 step C)", 305 "(IXP1200 step D)", "(IXP1240/1250 step A)", 306 "(IXP1240 step B)", "(IXP1250 step B)", 307 "rev 8", "rev 9", "rev 10", "rev 11", 308 "rev 12", "rev 13", "rev 14", "rev 15", 309 }; 310 311 static const char * const xscale_steppings[16] = { 312 "step A-0", "step A-1", "step B-0", "step C-0", 313 "step D-0", "rev 5", "rev 6", "rev 7", 314 "rev 8", "rev 9", "rev 10", "rev 11", 315 "rev 12", "rev 13", "rev 14", "rev 15", 316 }; 317 318 static const char * const i80321_steppings[16] = { 319 "step A-0", "step B-0", "rev 2", "rev 3", 320 "rev 4", "rev 5", "rev 6", "rev 7", 321 "rev 8", "rev 9", "rev 10", "rev 11", 322 "rev 12", "rev 13", "rev 14", "rev 15", 323 }; 324 325 static const char * const i80219_steppings[16] = { 326 "step A-0", "rev 1", "rev 2", "rev 3", 327 "rev 4", "rev 5", "rev 6", "rev 7", 328 "rev 8", "rev 9", "rev 10", "rev 11", 329 "rev 12", "rev 13", "rev 14", "rev 15", 330 }; 331 332 /* Steppings for PXA2[15]0 */ 333 static const char * const pxa2x0_steppings[16] = { 334 "step A-0", "step A-1", "step B-0", "step B-1", 335 "step B-2", "step C-0", "rev 6", "rev 7", 336 "rev 8", "rev 9", "rev 10", "rev 11", 337 "rev 12", "rev 13", "rev 14", "rev 15", 338 }; 339 340 /* Steppings for PXA255/26x. 341 * rev 5: PXA26x B0, rev 6: PXA255 A0 342 */ 343 static const char * const pxa255_steppings[16] = { 344 "rev 0", "rev 1", "rev 2", "step A-0", 345 "rev 4", "step B-0", "step A-0", "rev 7", 346 "rev 8", "rev 9", "rev 10", "rev 11", 347 "rev 12", "rev 13", "rev 14", "rev 15", 348 }; 349 350 /* Stepping for PXA27x */ 351 static const char * const pxa27x_steppings[16] = { 352 "step A-0", "step A-1", "step B-0", "step B-1", 353 "step C-0", "rev 5", "rev 6", "rev 7", 354 "rev 8", "rev 9", "rev 10", "rev 11", 355 "rev 12", "rev 13", "rev 14", "rev 15", 356 }; 357 358 static const char * const ixp425_steppings[16] = { 359 "step 0", "rev 1", "rev 2", "rev 3", 360 "rev 4", "rev 5", "rev 6", "rev 7", 361 "rev 8", "rev 9", "rev 10", "rev 11", 362 "rev 12", "rev 13", "rev 14", "rev 15", 363 }; 364 365 struct cpuidtab { 366 uint32_t cpuid; 367 enum cpu_class cpu_class; 368 const char *cpu_classname; 369 const char * const *cpu_steppings; 370 }; 371 372 const struct cpuidtab cpuids[] = { 373 { CPU_ID_ARM2, CPU_CLASS_ARM2, "ARM2", 374 generic_steppings }, 375 { CPU_ID_ARM250, CPU_CLASS_ARM2AS, "ARM250", 376 generic_steppings }, 377 378 { CPU_ID_ARM3, CPU_CLASS_ARM3, "ARM3", 379 generic_steppings }, 380 381 { CPU_ID_ARM600, CPU_CLASS_ARM6, "ARM600", 382 generic_steppings }, 383 { CPU_ID_ARM610, CPU_CLASS_ARM6, "ARM610", 384 generic_steppings }, 385 { CPU_ID_ARM620, CPU_CLASS_ARM6, "ARM620", 386 generic_steppings }, 387 388 { CPU_ID_ARM700, CPU_CLASS_ARM7, "ARM700", 389 generic_steppings }, 390 { CPU_ID_ARM710, CPU_CLASS_ARM7, "ARM710", 391 generic_steppings }, 392 { CPU_ID_ARM7500, CPU_CLASS_ARM7, "ARM7500", 393 generic_steppings }, 394 { CPU_ID_ARM710A, CPU_CLASS_ARM7, "ARM710a", 395 generic_steppings }, 396 { CPU_ID_ARM7500FE, CPU_CLASS_ARM7, "ARM7500FE", 397 generic_steppings }, 398 { CPU_ID_ARM710T, CPU_CLASS_ARM7TDMI, "ARM710T", 399 generic_steppings }, 400 { CPU_ID_ARM720T, CPU_CLASS_ARM7TDMI, "ARM720T", 401 generic_steppings }, 402 { CPU_ID_ARM740T8K, CPU_CLASS_ARM7TDMI, "ARM740T (8 KB cache)", 403 generic_steppings }, 404 { CPU_ID_ARM740T4K, CPU_CLASS_ARM7TDMI, "ARM740T (4 KB cache)", 405 generic_steppings }, 406 407 { CPU_ID_ARM810, CPU_CLASS_ARM8, "ARM810", 408 generic_steppings }, 409 410 { CPU_ID_ARM920T, CPU_CLASS_ARM9TDMI, "ARM920T", 411 generic_steppings }, 412 { CPU_ID_ARM922T, CPU_CLASS_ARM9TDMI, "ARM922T", 413 generic_steppings }, 414 { CPU_ID_ARM926EJS, CPU_CLASS_ARM9EJS, "ARM926EJ-S", 415 generic_steppings }, 416 { CPU_ID_ARM940T, CPU_CLASS_ARM9TDMI, "ARM940T", 417 generic_steppings }, 418 { CPU_ID_ARM946ES, CPU_CLASS_ARM9ES, "ARM946E-S", 419 generic_steppings }, 420 { CPU_ID_ARM966ES, CPU_CLASS_ARM9ES, "ARM966E-S", 421 generic_steppings }, 422 { CPU_ID_ARM966ESR1, CPU_CLASS_ARM9ES, "ARM966E-S", 423 generic_steppings }, 424 { CPU_ID_TI925T, CPU_CLASS_ARM9TDMI, "TI ARM925T", 425 generic_steppings }, 426 { CPU_ID_MV88SV131, CPU_CLASS_ARM9ES, "Sheeva 88SV131", 427 generic_steppings }, 428 { CPU_ID_MV88FR571_VD, CPU_CLASS_ARM9ES, "Sheeva 88FR571-vd", 429 generic_steppings }, 430 431 { CPU_ID_ARM1020E, CPU_CLASS_ARM10E, "ARM1020E", 432 generic_steppings }, 433 { CPU_ID_ARM1022ES, CPU_CLASS_ARM10E, "ARM1022E-S", 434 generic_steppings }, 435 { CPU_ID_ARM1026EJS, CPU_CLASS_ARM10EJ, "ARM1026EJ-S", 436 generic_steppings }, 437 438 { CPU_ID_SA110, CPU_CLASS_SA1, "SA-110", 439 sa110_steppings }, 440 { CPU_ID_SA1100, CPU_CLASS_SA1, "SA-1100", 441 sa1100_steppings }, 442 { CPU_ID_SA1110, CPU_CLASS_SA1, "SA-1110", 443 sa1110_steppings }, 444 445 { CPU_ID_IXP1200, CPU_CLASS_SA1, "IXP1200", 446 ixp12x0_steppings }, 447 448 { CPU_ID_80200, CPU_CLASS_XSCALE, "i80200", 449 xscale_steppings }, 450 451 { CPU_ID_80321_400, CPU_CLASS_XSCALE, "i80321 400MHz", 452 i80321_steppings }, 453 { CPU_ID_80321_600, CPU_CLASS_XSCALE, "i80321 600MHz", 454 i80321_steppings }, 455 { CPU_ID_80321_400_B0, CPU_CLASS_XSCALE, "i80321 400MHz", 456 i80321_steppings }, 457 { CPU_ID_80321_600_B0, CPU_CLASS_XSCALE, "i80321 600MHz", 458 i80321_steppings }, 459 460 { CPU_ID_80219_400, CPU_CLASS_XSCALE, "i80219 400MHz", 461 i80219_steppings }, 462 { CPU_ID_80219_600, CPU_CLASS_XSCALE, "i80219 600MHz", 463 i80219_steppings }, 464 465 { CPU_ID_PXA27X, CPU_CLASS_XSCALE, "PXA27x", 466 pxa27x_steppings }, 467 { CPU_ID_PXA250A, CPU_CLASS_XSCALE, "PXA250", 468 pxa2x0_steppings }, 469 { CPU_ID_PXA210A, CPU_CLASS_XSCALE, "PXA210", 470 pxa2x0_steppings }, 471 { CPU_ID_PXA250B, CPU_CLASS_XSCALE, "PXA250", 472 pxa2x0_steppings }, 473 { CPU_ID_PXA210B, CPU_CLASS_XSCALE, "PXA210", 474 pxa2x0_steppings }, 475 { CPU_ID_PXA250C, CPU_CLASS_XSCALE, "PXA255/26x", 476 pxa255_steppings }, 477 { CPU_ID_PXA210C, CPU_CLASS_XSCALE, "PXA210", 478 pxa2x0_steppings }, 479 480 { CPU_ID_IXP425_533, CPU_CLASS_XSCALE, "IXP425 533MHz", 481 ixp425_steppings }, 482 { CPU_ID_IXP425_400, CPU_CLASS_XSCALE, "IXP425 400MHz", 483 ixp425_steppings }, 484 { CPU_ID_IXP425_266, CPU_CLASS_XSCALE, "IXP425 266MHz", 485 ixp425_steppings }, 486 487 { CPU_ID_ARM1136JS, CPU_CLASS_ARM11J, "ARM1136J-S r0", 488 pN_steppings }, 489 { CPU_ID_ARM1136JSR1, CPU_CLASS_ARM11J, "ARM1136J-S r1", 490 pN_steppings }, 491 #if 0 492 /* The ARM1156T2-S only has a memory protection unit */ 493 { CPU_ID_ARM1156T2S, CPU_CLASS_ARM11J, "ARM1156T2-S r0", 494 pN_steppings }, 495 #endif 496 { CPU_ID_ARM1176JZS, CPU_CLASS_ARM11J, "ARM1176JZ-S r0", 497 pN_steppings }, 498 499 { CPU_ID_ARM11MPCORE, CPU_CLASS_ARM11J, "ARM11 MPCore", 500 generic_steppings }, 501 502 { CPU_ID_CORTEXA5R0, CPU_CLASS_CORTEX, "Cortex-A5 r0", 503 pN_steppings }, 504 { CPU_ID_CORTEXA8R1, CPU_CLASS_CORTEX, "Cortex-A8 r1", 505 pN_steppings }, 506 { CPU_ID_CORTEXA8R2, CPU_CLASS_CORTEX, "Cortex-A8 r2", 507 pN_steppings }, 508 { CPU_ID_CORTEXA8R3, CPU_CLASS_CORTEX, "Cortex-A8 r3", 509 pN_steppings }, 510 { CPU_ID_CORTEXA9R2, CPU_CLASS_CORTEX, "Cortex-A9 r2", 511 pN_steppings }, 512 { CPU_ID_CORTEXA9R3, CPU_CLASS_CORTEX, "Cortex-A9 r3", 513 pN_steppings }, 514 { CPU_ID_CORTEXA9R4, CPU_CLASS_CORTEX, "Cortex-A9 r4", 515 pN_steppings }, 516 { CPU_ID_CORTEXA15R2, CPU_CLASS_CORTEX, "Cortex-A15 r2", 517 pN_steppings }, 518 { CPU_ID_CORTEXA15R3, CPU_CLASS_CORTEX, "Cortex-A15 r3", 519 pN_steppings }, 520 521 { CPU_ID_FA526, CPU_CLASS_ARMV4, "FA526", 522 generic_steppings }, 523 524 { 0, CPU_CLASS_NONE, NULL, NULL } 525 }; 526 527 struct cpu_classtab { 528 const char *class_name; 529 const char *class_option; 530 }; 531 532 const struct cpu_classtab cpu_classes[] = { 533 [CPU_CLASS_NONE] = { "unknown", NULL }, 534 [CPU_CLASS_ARM2] = { "ARM2", "CPU_ARM2" }, 535 [CPU_CLASS_ARM2AS] = { "ARM2as", "CPU_ARM250" }, 536 [CPU_CLASS_ARM3] = { "ARM3", "CPU_ARM3" }, 537 [CPU_CLASS_ARM6] = { "ARM6", "CPU_ARM6" }, 538 [CPU_CLASS_ARM7] = { "ARM7", "CPU_ARM7" }, 539 [CPU_CLASS_ARM7TDMI] = { "ARM7TDMI", "CPU_ARM7TDMI" }, 540 [CPU_CLASS_ARM8] = { "ARM8", "CPU_ARM8" }, 541 [CPU_CLASS_ARM9TDMI] = { "ARM9TDMI", NULL }, 542 [CPU_CLASS_ARM9ES] = { "ARM9E-S", "CPU_ARM9E" }, 543 [CPU_CLASS_ARM9EJS] = { "ARM9EJ-S", "CPU_ARM9E" }, 544 [CPU_CLASS_ARM10E] = { "ARM10E", "CPU_ARM10" }, 545 [CPU_CLASS_ARM10EJ] = { "ARM10EJ", "CPU_ARM10" }, 546 [CPU_CLASS_SA1] = { "SA-1", "CPU_SA110" }, 547 [CPU_CLASS_XSCALE] = { "XScale", "CPU_XSCALE_..." }, 548 [CPU_CLASS_ARM11J] = { "ARM11J", "CPU_ARM11" }, 549 [CPU_CLASS_ARMV4] = { "ARMv4", "CPU_ARMV4" }, 550 [CPU_CLASS_CORTEX] = { "Cortex", "CPU_CORTEX" }, 551 }; 552 553 /* 554 * Report the type of the specified arm processor. This uses the generic and 555 * arm specific information in the CPU structure to identify the processor. 556 * The remaining fields in the CPU structure are filled in appropriately. 557 */ 558 559 static const char * const wtnames[] = { 560 "write-through", 561 "write-back", 562 "write-back", 563 "**unknown 3**", 564 "**unknown 4**", 565 "write-back-locking", /* XXX XScale-specific? */ 566 "write-back-locking-A", 567 "write-back-locking-B", 568 "**unknown 8**", 569 "**unknown 9**", 570 "**unknown 10**", 571 "**unknown 11**", 572 "**unknown 12**", 573 "**unknown 13**", 574 "write-back-locking-C", 575 "write-back-locking-D", 576 }; 577 578 static void 579 print_cache_info(device_t dv, struct arm_cache_info *info, u_int level) 580 { 581 if (info->cache_unified) { 582 aprint_normal_dev(dv, "%dKB/%dB %d-way %s L%u Unified cache\n", 583 info->dcache_size / 1024, 584 info->dcache_line_size, info->dcache_ways, 585 wtnames[info->cache_type], level + 1); 586 } else { 587 aprint_normal_dev(dv, "%dKB/%dB %d-way L%u Instruction cache\n", 588 info->icache_size / 1024, 589 info->icache_line_size, info->icache_ways, level + 1); 590 aprint_normal_dev(dv, "%dKB/%dB %d-way %s L%u Data cache\n", 591 info->dcache_size / 1024, 592 info->dcache_line_size, info->dcache_ways, 593 wtnames[info->cache_type], level + 1); 594 } 595 } 596 597 void 598 identify_arm_cpu(device_t dv, struct cpu_info *ci) 599 { 600 enum cpu_class cpu_class = CPU_CLASS_NONE; 601 const u_int cpuid = ci->ci_arm_cpuid; 602 const char * const xname = device_xname(dv); 603 const char *steppingstr; 604 int i; 605 606 if (cpuid == 0) { 607 aprint_error("Processor failed probe - no CPU ID\n"); 608 return; 609 } 610 611 for (i = 0; cpuids[i].cpuid != 0; i++) 612 if (cpuids[i].cpuid == (cpuid & CPU_ID_CPU_MASK)) { 613 cpu_class = cpuids[i].cpu_class; 614 steppingstr = cpuids[i].cpu_steppings[cpuid & 615 CPU_ID_REVISION_MASK]; 616 snprintf(cpu_model, sizeof(cpu_model), 617 "%s%s%s (%s core)", cpuids[i].cpu_classname, 618 steppingstr[0] == '*' ? "" : " ", 619 &steppingstr[steppingstr[0] == '*'], 620 cpu_classes[cpu_class].class_name); 621 break; 622 } 623 624 if (cpuids[i].cpuid == 0) 625 snprintf(cpu_model, sizeof(cpu_model), 626 "unknown CPU (ID = 0x%x)", cpuid); 627 628 if (ci->ci_data.cpu_cc_freq != 0) { 629 char freqbuf[8]; 630 humanize_number(freqbuf, sizeof(freqbuf), ci->ci_data.cpu_cc_freq, 631 "Hz", 1000); 632 633 aprint_naive(": %s %s\n", freqbuf, cpu_model); 634 aprint_normal(": %s %s\n", freqbuf, cpu_model); 635 } else { 636 aprint_naive(": %s\n", cpu_model); 637 aprint_normal(": %s\n", cpu_model); 638 } 639 640 aprint_normal("%s:", xname); 641 642 switch (cpu_class) { 643 case CPU_CLASS_ARM6: 644 case CPU_CLASS_ARM7: 645 case CPU_CLASS_ARM7TDMI: 646 case CPU_CLASS_ARM8: 647 if ((ci->ci_ctrl & CPU_CONTROL_IDC_ENABLE) == 0) 648 aprint_normal(" IDC disabled"); 649 else 650 aprint_normal(" IDC enabled"); 651 break; 652 case CPU_CLASS_ARM9TDMI: 653 case CPU_CLASS_ARM9ES: 654 case CPU_CLASS_ARM9EJS: 655 case CPU_CLASS_ARM10E: 656 case CPU_CLASS_ARM10EJ: 657 case CPU_CLASS_SA1: 658 case CPU_CLASS_XSCALE: 659 case CPU_CLASS_ARM11J: 660 case CPU_CLASS_ARMV4: 661 case CPU_CLASS_CORTEX: 662 if ((ci->ci_ctrl & CPU_CONTROL_DC_ENABLE) == 0) 663 aprint_normal(" DC disabled"); 664 else 665 aprint_normal(" DC enabled"); 666 if ((ci->ci_ctrl & CPU_CONTROL_IC_ENABLE) == 0) 667 aprint_normal(" IC disabled"); 668 else 669 aprint_normal(" IC enabled"); 670 break; 671 default: 672 break; 673 } 674 if ((ci->ci_ctrl & CPU_CONTROL_WBUF_ENABLE) == 0) 675 aprint_normal(" WB disabled"); 676 else 677 aprint_normal(" WB enabled"); 678 679 if (ci->ci_ctrl & CPU_CONTROL_LABT_ENABLE) 680 aprint_normal(" LABT"); 681 else 682 aprint_normal(" EABT"); 683 684 if (ci->ci_ctrl & CPU_CONTROL_BPRD_ENABLE) 685 aprint_normal(" branch prediction enabled"); 686 687 aprint_normal("\n"); 688 689 #if defined(CPU_CORTEX) 690 if (CPU_ID_CORTEX_P(cpuid)) { 691 identify_features(dv); 692 } 693 #endif 694 /* Print cache info. */ 695 if (arm_pcache.icache_line_size != 0 || arm_pcache.dcache_line_size != 0) { 696 print_cache_info(dv, &arm_pcache, 0); 697 } 698 if (arm_scache.icache_line_size != 0 || arm_scache.dcache_line_size != 0) { 699 print_cache_info(dv, &arm_scache, 1); 700 } 701 702 703 switch (cpu_class) { 704 #ifdef CPU_ARM2 705 case CPU_CLASS_ARM2: 706 #endif 707 #ifdef CPU_ARM250 708 case CPU_CLASS_ARM2AS: 709 #endif 710 #ifdef CPU_ARM3 711 case CPU_CLASS_ARM3: 712 #endif 713 #ifdef CPU_ARM6 714 case CPU_CLASS_ARM6: 715 #endif 716 #ifdef CPU_ARM7 717 case CPU_CLASS_ARM7: 718 #endif 719 #ifdef CPU_ARM7TDMI 720 case CPU_CLASS_ARM7TDMI: 721 #endif 722 #ifdef CPU_ARM8 723 case CPU_CLASS_ARM8: 724 #endif 725 #ifdef CPU_ARM9 726 case CPU_CLASS_ARM9TDMI: 727 #endif 728 #if defined(CPU_ARM9E) || defined(CPU_SHEEVA) 729 case CPU_CLASS_ARM9ES: 730 case CPU_CLASS_ARM9EJS: 731 #endif 732 #ifdef CPU_ARM10 733 case CPU_CLASS_ARM10E: 734 case CPU_CLASS_ARM10EJ: 735 #endif 736 #if defined(CPU_SA110) || defined(CPU_SA1100) || \ 737 defined(CPU_SA1110) || defined(CPU_IXP12X0) 738 case CPU_CLASS_SA1: 739 #endif 740 #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 741 defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425) 742 case CPU_CLASS_XSCALE: 743 #endif 744 #if defined(CPU_ARM11) 745 case CPU_CLASS_ARM11J: 746 #endif 747 #if defined(CPU_CORTEX) 748 case CPU_CLASS_CORTEX: 749 #endif 750 #if defined(CPU_FA526) 751 case CPU_CLASS_ARMV4: 752 #endif 753 break; 754 default: 755 if (cpu_classes[cpu_class].class_option == NULL) { 756 aprint_error_dev(dv, "%s does not fully support this CPU.\n", 757 ostype); 758 } else { 759 aprint_error_dev(dv, "This kernel does not fully support " 760 "this CPU.\n"); 761 aprint_normal_dev(dv, "Recompile with \"options %s\" to " 762 "correct this.\n", cpu_classes[cpu_class].class_option); 763 } 764 break; 765 } 766 } 767 768 #if defined(CPU_CORTEX) 769 void 770 identify_features(device_t dv) 771 { 772 uint32_t isar0 = armreg_isar0_read(); 773 uint32_t isar1 = armreg_isar1_read(); 774 uint32_t isar2 = armreg_isar2_read(); 775 uint32_t isar3 = armreg_isar3_read(); 776 uint32_t isar4 = armreg_isar4_read(); 777 uint32_t isar5 = armreg_isar5_read(); 778 779 uint32_t mmfr0 = armreg_mmfr0_read(); 780 uint32_t mmfr1 = armreg_mmfr1_read(); 781 uint32_t mmfr2 = armreg_mmfr2_read(); 782 uint32_t mmfr3 = armreg_mmfr3_read(); 783 784 if (__SHIFTOUT(mmfr3, __BITS(23,20))) { 785 /* 786 * Updates to the translation tables do not require a clean 787 * to the point of unification to ensure visibility by subsequent 788 * translation table walks. 789 */ 790 pmap_needs_pte_sync = 0; 791 } 792 793 uint32_t pfr0 = armreg_pfr0_read(); 794 uint32_t pfr1 = armreg_pfr1_read(); 795 796 aprint_verbose_dev(dv, 797 "isar: [0]=%#x [1]=%#x [2]=%#x [3]=%#x, [4]=%#x, [5]=%#x\n", 798 isar0, isar1, isar2, isar3, isar4, isar5); 799 aprint_verbose_dev(dv, 800 "mmfr: [0]=%#x [1]=%#x [2]=%#x [3]=%#x\n", 801 mmfr0, mmfr1, mmfr2, mmfr3); 802 aprint_verbose_dev(dv, 803 "pfr: [0]=%#x [1]=%#x\n", 804 pfr0, pfr1); 805 } 806 #endif /* CPU_CORTEX */ 807
Indexes created Fri Sep 26 08:10:20 GMT 2025