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      1 /*	$NetBSD: spl.S,v 1.11 2021/10/11 07:26:17 rin Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 1996-1998 Mark Brinicombe.
      5  * Copyright (c) Brini.
      6  * All rights reserved.
      7  *
      8  * Redistribution and use in source and binary forms, with or without
      9  * modification, are permitted provided that the following conditions
     10  * are met:
     11  * 1. Redistributions of source code must retain the above copyright
     12  *    notice, this list of conditions and the following disclaimer.
     13  * 2. Redistributions in binary form must reproduce the above copyright
     14  *    notice, this list of conditions and the following disclaimer in the
     15  *    documentation and/or other materials provided with the distribution.
     16  * 3. All advertising materials mentioning features or use of this software
     17  *    must display the following acknowledgement:
     18  *	This product includes software developed by Mark Brinicombe
     19  *	for the NetBSD Project.
     20  * 4. The name of the company nor the name of the author may be used to
     21  *    endorse or promote products derived from this software without specific
     22  *    prior written permission.
     23  *
     24  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
     25  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
     26  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     27  * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
     28  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
     29  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
     30  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     31  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     32  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     33  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     34  * SUCH DAMAGE.
     35  *
     36  * spl routines
     37  *
     38  * Created      : 01/03/96
     39  */
     40 
     41 #include "assym.h"
     42 #include <arm/asm.h>
     43 #include <arm/locore.h>
     44 #include <arm/arm32/psl.h>
     45 
     46 	RCSID("$NetBSD: spl.S,v 1.11 2021/10/11 07:26:17 rin Exp $")
     47 
     48 	.text
     49 	.align	0
     50 
     51 .Lcpu_info_store:
     52 	.word	_C_LABEL(cpu_info_store)
     53 
     54 ENTRY(raisespl)
     55 	mov	r3, r0			/* Save the new value */
     56 	ldr	r1, .Lcpu_info_store	/* Get the current spl level */
     57 	ldr	r0, [r1, #CI_CPL]
     58 	cmp	r3, r0
     59 	RETc(le)
     60 
     61 	stmfd	sp!, {r0, r1, r4, lr}	/* Preserve registers */
     62 
     63 	/* Disable interrupts */
     64 	mrs	r4, cpsr
     65 	orr	r2, r4, #(I32_bit)
     66 	msr	cpsr_c, r2
     67 
     68 	str	r3, [r1, #CI_CPL]	/* Store the new spl level */
     69 	bl	_C_LABEL(irq_setmasks)	/* Update the actual masks */
     70 	msr	cpsr_c, r4		/* Restore interrupts */
     71 
     72 	ldmfd	sp!, {r0, r1, r4, pc}	/* Restore registers */
     73 
     74 ENTRY(lowerspl)
     75 	mov	r3, r0			/* Save the new value */
     76 	ldr	r1, .Lcpu_info_store	/* Get the current spl level */
     77 	ldr	r0, [r1, #CI_CPL]
     78 	cmp	r3, r0
     79 	RETc(ge)
     80 
     81 	stmfd	sp!, {r0, r1, r4, lr}	/* Preserve registers */
     82 
     83 	/* Disable interrupts */
     84 	mrs	r4, cpsr
     85 	orr	r2, r4,  #(I32_bit)
     86 	msr	cpsr_c, r2
     87 
     88 	str	r3, [r1, #CI_CPL]	/* Store the new spl level */
     89 
     90 	bl	_C_LABEL(irq_setmasks)	/* Update the actual masks */
     91 	msr	cpsr_all, r4
     92 #ifdef __HAVE_FAST_SOFTINTS
     93 	bl	_C_LABEL(dosoftints)	/* Process any pending soft ints */
     94 #endif
     95 	ldmfd	sp!, {r0, r1, r4, pc}	/* restore registers */
     96 
     97 ENTRY(splx)
     98 	mov	r3, r0			/* Save the new value */
     99 	ldr	r1, .Lcpu_info_store	/* Get the current spl level */
    100 	ldr	r0, [r1, #CI_CPL]
    101 	cmp	r3, r0
    102 	RETc(eq)
    103 
    104 	stmfd	sp!, {r0, r1, r4, lr}
    105 
    106 	/* Disable interrupts */
    107 	mrs	r4, cpsr
    108 	orr	r2, r4,  #(I32_bit)
    109 	msr	cpsr_c, r2
    110 
    111 	str	r3, [r1, #CI_CPL]	/* Store the new spl level */
    112 
    113 	bl	_C_LABEL(irq_setmasks)	/* Update the actual masks */
    114 	msr	cpsr_c, r4
    115 #ifdef __HAVE_FAST_SOFTINTS
    116 	bl	_C_LABEL(dosoftints)	/* Process any pending soft ints */
    117 #endif
    118 	ldmfd	sp!, {r0, r1, r4, pc}
    119