1 1.3 aymeric /* $Id: at91pmcreg.h,v 1.3 2011/11/04 17:20:54 aymeric Exp $ */ 2 1.2 matt 3 1.2 matt #ifndef _AT91PMCREG_H_ 4 1.2 matt #define _AT91PMCREG_H_ 1 5 1.2 matt 6 1.2 matt /* Power Management Controller (PMC), at, 7 1.2 matt * at91rm9200.pdf, page 271 */ 8 1.2 matt 9 1.2 matt #define PMC_NUM_PCLOCKS 8 10 1.2 matt 11 1.2 matt #define PMC_SCER 0x00U /* 00: System Clock Enable Reg */ 12 1.2 matt #define PMC_SCDR 0x04U /* 04: System Clock Disable Reg */ 13 1.2 matt #define PMC_SCSR 0x08U /* 08: System Clock Status Reg */ 14 1.2 matt #define PMC_PCER 0x10U /* 10: Peripheral Clock Enable */ 15 1.2 matt #define PMC_PCDR 0x14U /* 14: Peripheral Clock Disable */ 16 1.2 matt #define PMC_PCSR 0x18U /* 18: Peripheral Clock Status */ 17 1.2 matt #define PMC_MOR 0x20U /* 20: Main Oscillator Reg */ 18 1.2 matt #define PMC_MCFR 0x24U /* 24: Main Clock Freq Reg */ 19 1.2 matt #define PMC_PLLAR 0x28U /* 28: PLL A Register#define PMC_*/ 20 1.2 matt #define PMC_PLLBR 0x2CU /* 2C: PLL B Register */ 21 1.2 matt #define PMC_MCKR 0x30U /* 30: Master Clock Register */ 22 1.2 matt #define PMC_PCK(num) (0x40U + (num) * 4U) /* 40: Programmable Clocks */ 23 1.2 matt #define PMC_IER 0x60U /* 60: Interrupt Enable Reg */ 24 1.2 matt #define PMC_IDR 0x64U /* 64: Interrupt Disable Reg */ 25 1.2 matt #define PMC_SR 0x68U /* 68: Status Register */ 26 1.2 matt #define PMC_IMR 0x6CU /* 6C: Interrupt Mask Reg */ 27 1.3 aymeric #define PMC_PLLICPR 0x80U /* 80: PLL Charge Pump Current Reg */ 28 1.2 matt 29 1.2 matt /* System Clock Enable Register bits: */ 30 1.2 matt #define PMC_SCSR_PCK3 0x0800U 31 1.2 matt #define PMC_SCSR_PCK2 0x0400U 32 1.2 matt #define PMC_SCSR_PCK1 0x0200U 33 1.2 matt #define PMC_SCSR_PCK0 0x0100U 34 1.3 aymeric #define PMC_SCSR_SAM_UDP 0x0080U 35 1.3 aymeric #define PMC_SCSR_SAM_UHP 0x0040U 36 1.2 matt #define PMC_SCSR_UHP 0x0010U /* 1 = Enable USB Host Port clks */ 37 1.2 matt #define PMC_SCSR_MCKUDP 0x0004U /* 1 = enable Master Clock dis */ 38 1.2 matt #define PMC_SCSR_UDP 0x0002U /* 1 = enable USB Device Port clk */ 39 1.2 matt #define PMC_SCSR_PCK 0x0001U /* 1 = enable the processor clk */ 40 1.2 matt 41 1.2 matt /* Main Oscillator Register bits: */ 42 1.2 matt #define PMC_MOR_OSCOUNT 0xFF00U /* start-up-time / 8 */ 43 1.2 matt #define PMC_MOR_OSCOUNT_SHIFT 8U 44 1.2 matt #define PMC_MOR_MOSCEN 0x1U /* 1 = main oscillator enabled */ 45 1.2 matt 46 1.2 matt /* Main Clock Frequency Register bits: */ 47 1.2 matt #define PMC_MCFR_MAINRDY 0x10000U /* 1= main clock ready */ 48 1.2 matt #define PMC_MCFR_MAINF 0x0FFFFU 49 1.2 matt 50 1.2 matt /* PLL Register bits: */ 51 1.2 matt #define PMC_PLL_MUL 0x07FF0000U 52 1.2 matt #define PMC_PLL_MUL_SHIFT 16U 53 1.2 matt #define PMC_PLL_OUT 0x0000C000U 54 1.2 matt #define PMC_PLL_OUT_80_TO_160 0x00000000U 55 1.2 matt #define PMC_PLL_OUT_150_TO_240 0x00008000U 56 1.2 matt #define PMC_PLL_PLLCOUNT 0x00003F00U 57 1.2 matt #define PMC_PLL_DIV 0x000000FFU 58 1.2 matt #define PMC_PLL_DIV_SHIFT 0U 59 1.2 matt 60 1.2 matt /* PLL B Register bits: */ 61 1.2 matt #define PMC_PLLBR_USB_96M 0x10000000U /* 1 = USB clks = PLL B output / 2 */ 62 1.2 matt 63 1.2 matt /* Master Clock Register bits: */ 64 1.2 matt #define PMC_MCKR_MDIV 0x300U 65 1.2 matt #define PMC_MCKR_MDIV_1 0x000U 66 1.2 matt #define PMC_MCKR_MDIV_2 0x100U 67 1.2 matt #define PMC_MCKR_MDIV_3 0x200U 68 1.2 matt #define PMC_MCKR_MDIV_4 0x300U 69 1.2 matt #define PMC_MCKR_MDIV_SHIFT 8U 70 1.2 matt 71 1.2 matt #define PMC_MCKR_PRES 0x01CU 72 1.2 matt #define PMC_MCKR_PRES_SHIFT 2U 73 1.2 matt #define PMC_MCKR_PRES_1 (0U<<PMC_MCKR_PRES_SHIFT) 74 1.2 matt #define PMC_MCKR_PRES_2 (1U<<PMC_MCKR_PRES_SHIFT) 75 1.2 matt #define PMC_MCKR_PRES_4 (2U<<PMC_MCKR_PRES_SHIFT) 76 1.2 matt #define PMC_MCKR_PRES_8 (3U<<PMC_MCKR_PRES_SHIFT) 77 1.2 matt #define PMC_MCKR_PRES_16 (4U<<PMC_MCKR_PRES_SHIFT) 78 1.2 matt #define PMC_MCKR_PRES_32 (5U<<PMC_MCKR_PRES_SHIFT) 79 1.2 matt #define PMC_MCKR_PRES_64 (6U<<PMC_MCKR_PRES_SHIFT) 80 1.2 matt 81 1.2 matt #define PMC_MCKR_CSS 0x003U 82 1.2 matt #define PMC_MCKR_CSS_SLOW_CLK 0x000U 83 1.2 matt #define PMC_MCKR_CSS_MAIN_CLK 0x001U 84 1.2 matt #define PMC_MCKR_CSS_PLLA 0x002U 85 1.2 matt #define PMC_MCKR_CSS_PLLB 0x003U 86 1.2 matt 87 1.2 matt /* Programmable Clock Register bits: */ 88 1.2 matt #define PMC_PCK_PRES PMC_MCKR_PRES 89 1.2 matt #define PMC_PCK_PRES_SHIFT PMC_MCKR_PRES_SHIFT 90 1.2 matt #define PMC_PCK_PRES_1 PMC_MCKR_PRES_1 91 1.2 matt #define PMC_PCK_PRES_2 PMC_MCKR_PRES_2 92 1.2 matt #define PMC_PCK_PRES_4 PMC_MCKR_PRES_4 93 1.2 matt #define PMC_PCK_PRES_8 PMC_MCKR_PRES_8 94 1.2 matt #define PMC_PCK_PRES_16 PMC_MCKR_PRES_16 95 1.2 matt #define PMC_PCK_PRES_32 PMC_MCKR_PRES_32 96 1.2 matt #define PMC_PCK_PRES_64 PMC_MCKR_PRES_64 97 1.2 matt 98 1.2 matt #define PMC_PCK_CSS PMC_MCKR_CSS 99 1.2 matt #define PMC_PCK_CSS_SLOW_CLK PMC_MCKR_CSS_SLOW_CLK 100 1.2 matt #define PMC_PCK_CSS_CLKC PMC_MCKR_CSS_CLKC 101 1.2 matt #define PMC_PCK_CSS_CLKA PMC_MCKR_CSS_CLKA 102 1.2 matt #define PMC_PCK_CSS_CLKB PMC_MCKR_CSS_CLKB 103 1.2 matt 104 1.2 matt 105 1.2 matt /* Interrupt Enable Register bits: */ 106 1.2 matt #define PMC_SR_PCK7RDY 0x8000U 107 1.2 matt #define PMC_SR_PCK6RDY 0x4000U 108 1.2 matt #define PMC_SR_PCK5RDY 0x2000U 109 1.2 matt #define PMC_SR_PCK4RDY 0x1000U 110 1.2 matt #define PMC_SR_PCK3RDY 0x0800U 111 1.2 matt #define PMC_SR_PCK2RDY 0x0400U 112 1.2 matt #define PMC_SR_PCK1RDY 0x0200U 113 1.2 matt #define PMC_SR_PCK0RDY 0x0100U 114 1.2 matt #define PMC_SR_MCKRDY 0x0008U 115 1.2 matt #define PMC_SR_LOCKB 0x0004U 116 1.2 matt #define PMC_SR_LOCKA 0x0002U 117 1.2 matt #define PMC_SR_MOSCS 0x0001U 118 1.2 matt 119 1.3 aymeric /* PLL Charge Pump Current Reg bits: */ 120 1.3 aymeric #define PMC_PLLICPR_ICPPLLA 0x00000001U 121 1.3 aymeric #define PMC_PLLICPR_ICPPLLB 0x00010000U 122 1.3 aymeric 123 1.2 matt #define PMCREG(offset) *((volatile uint32_t*)(0xfffffc00UL + (offset))) 124 1.2 matt 125 1.2 matt #endif /* !_AT91PMCREG_H_ */ 126
Indexes created Mon Sep 22 05:09:51 GMT 2025