1 /* $Id: at91spireg.h,v 1.2 2008/07/03 01:15:38 matt Exp $ */ 2 /* $NetBSD: at91spireg.h,v 1.2 2008/07/03 01:15:38 matt Exp $ */ 3 4 /*- 5 * Copyright (c) 2007 Embedtronics Oy. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or 9 * without modification, are permitted provided that the following 10 * conditions are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 * 3. All advertising materials mentioning features or use of this 18 * software must display the following acknowledgements: 19 * This product includes software developed by the Urbana-Champaign 20 * Independent Media Center. 21 * This product includes software developed by Garrett D'Amore. 22 * 4. Urbana-Champaign Independent Media Center's name and Garrett 23 * D'Amore's name may not be used to endorse or promote products 24 * derived from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE URBANA-CHAMPAIGN INDEPENDENT 27 * MEDIA CENTER AND GARRETT D'AMORE ``AS IS'' AND ANY EXPRESS OR 28 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 29 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30 * ARE DISCLAIMED. IN NO EVENT SHALL THE URBANA-CHAMPAIGN INDEPENDENT 31 * MEDIA CENTER OR GARRETT D'AMORE BE LIABLE FOR ANY DIRECT, INDIRECT, 32 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 33 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 34 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 38 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 */ 40 41 #ifndef _AT91SPIREG_H_ 42 #define _AT91SPIREG_H_ 43 44 #define SPI_CS_COUNT 4 45 46 #define AT91_SPI_SIZE 0x4000U 47 48 #define SPI_CR 0x00U /* 0x00: Control Register */ 49 #define SPI_MR 0x04U /* 0x04: Mode Register */ 50 #define SPI_RDR 0x08U /* 0x08: Receive Data Register */ 51 #define SPI_TDR 0x0CU /* 0x0C: Transmit Data Register */ 52 #define SPI_SR 0x10U /* 0x10: Status Register */ 53 #define SPI_IER 0x14U /* 0x14: Interrupt Enable Reg */ 54 #define SPI_IDR 0x18U /* 0x18: Interrupt Disable Reg */ 55 #define SPI_IMR 0x1CU /* 0x1C: Interrupt Mask Reg */ 56 #define SPI_CSR(slv) (0x30U + 4 * (slv)) /* 0x30: Chip Select Regs */ 57 #define SPI_PDC_BASE 0x100U /* 0x100: PDC */ 58 59 /* Control Register bits: */ 60 #define SPI_CR_SWRST 0x80 /* 1 = Reset the SPI */ 61 #define SPI_CR_SPIDIS 0x2 /* 1 = disables the SPI */ 62 #define SPI_CR_SPIEN 0x1 /* 1 = enables the SPI */ 63 64 /* Mode Register bits: */ 65 #define SPI_MR_DLYBCS 0xFF000000 /* delay between chip selects */ 66 #define SPI_MR_DLYBCS_SHIFT 24 67 #define SPI_MR_PCS 0x000F0000 /* peripheral chip select */ 68 #define SPI_MR_PCS_SHIFT 16 69 #define SPI_MR_LLB 0x80 /* 1 = local loopback enabled */ 70 #define SPI_MR_MODFDIS 0x10 /* 1 = mode fault detection dis */ 71 #define SPI_MR_DIV32 0x08 /* 1 = SPI operates at MCK/32 */ 72 #define SPI_MR_PCSDEC 0x04 /* 1 = use 4- to 16-bit decoder */ 73 #define SPI_MR_PS 0x02 /* 1 = variable peripheral sel. */ 74 #define SPI_MR_MSTR 0x01 /* 1 = SPI is in Master mode */ 75 76 /* Status Register bits: */ 77 #define SPI_SR_SPIENS 0x10000 /* 1 = SPI is enabled */ 78 #define SPI_SR_TXBUFE 0x80 /* 1 = TX Buffer empty */ 79 #define SPI_SR_RXBUFF 0x40 /* 1 = RX buffer full */ 80 #define SPI_SR_ENDTX 0x20 /* 1 = End of TX buffer */ 81 #define SPI_SR_ENDRX 0x10 /* 1 = End of RX buffer */ 82 #define SPI_SR_OVRES 0x08 /* 1 = Overrun occurred */ 83 #define SPI_SR_MODF 0x04 /* 1 = Mode fault occurred */ 84 #define SPI_SR_TDRE 0x02 /* 1 = Transmit Data Reg empty */ 85 #define SPI_SR_RDRF 0x01 /* 1 = Receive Data Reg full */ 86 87 /* Chip Select Register: */ 88 #define SPI_CSR_DLYBCT 0xFF000000 89 #define SPI_CSR_DLYBCT_SHIFT 24 90 #define SPI_CSR_DLYBS 0x00FF0000 91 #define SPI_CSR_DLYBS_SHIFT 16 92 #define SPI_CSR_SCBR 0x0000FF00 93 #define SPI_CSR_SCBR_SHIFT 8 94 #define SPI_CSR_BITS 0x000000F0 95 #define SPI_CSR_BITS_8 (0U<<4) 96 #define SPI_CSR_BITS_16 (8U<<4) 97 #define SPI_CSR_BITS_SHIFT 4 98 #define SPI_CSR_NCPHA 0x00000002 99 #define SPI_CSR_CPOL 0x00000001 100 #define SPI_CSR_RESERVED 0x0000000C 101 102 #endif /* _AT91SPIREG_H_ */ 103
Indexes created Sun Sep 21 16:09:51 GMT 2025