1 /* $NetBSD: at91usartreg.h,v 1.4 2022/02/13 00:39:45 andvar Exp $ */ 2 3 /* 4 * Copyright (c) 2007 Embedtronics Oy. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 19 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #ifndef _AT91USARTREG_H_ 29 #define _AT91USARTREG_H_ 30 31 #define US_CR 0x00U /* 0x00: Control Register */ 32 #define US_MR 0x04U /* 0x04: Mode Register */ 33 #define US_IER 0x08U /* 0x08: Interrupt Enable Reg */ 34 #define US_IDR 0x0CU /* 0x0C: Interrupt Disable Reg */ 35 #define US_IMR 0x10U /* 0x10: Interrupt Mask Reg */ 36 #define US_CSR 0x14U /* 0x14: Channel Status Reg */ 37 #define US_RHR 0x18U /* 0x18: Receive Holding Reg */ 38 #define US_THR 0x1CU /* 0x1C: Transmit Holding Reg */ 39 #define US_BRGR 0x20U /* 0x20: Baud Rate Generator Rg */ 40 #define US_RTOR 0x24U /* 0x24: Receiver Time-out Reg */ 41 #define US_TTGR 0x28U /* 0x28: Transmitter Timeguard Reg */ 42 #define US_FIDI 0x40U /* 0x40: FI DI Ratio Register */ 43 #define US_NER 0x44U /* 0x44: Number of Errors Reg */ 44 #define US_IF 0x4CU /* 0x4C: IrDA Filter Register */ 45 #define US_PDC 0x100U /* 0x100: PDC */ 46 47 /* Control Register bits: */ 48 #define US_CR_RTSDIS 0x00080000U /* 1 = disable RTS */ 49 #define US_CR_RTSEN 0x00040000U /* 1 = enable RTS */ 50 #define US_CR_DTRDIS 0x00020000U /* 1 = disable DTR */ 51 #define US_CR_DTREN 0x00010000U /* 1 = enable DTR */ 52 #define US_CR_RETTO 0x00008000U /* 1 = Rearm Time-out */ 53 #define US_CR_RSTNACK 0x00004000U /* 1 = Reset Non Acknowledge */ 54 #define US_CR_RSTIT 0x00002000U /* 1 = Reset Iterations */ 55 #define US_CR_SENDA 0x00001000U /* 1 = Send Address */ 56 #define US_CR_STTTO 0x00000800U /* 1 = Start Time-out */ 57 #define US_CR_STPBRK 0x00000400U /* 1 = stop break */ 58 #define US_CR_STTBRK 0x00000200U /* 1 = start break */ 59 #define US_CR_RSTSTA 0x00000100U /* 1 = reset status bits */ 60 #define US_CR_TXDIS 0x00000080U /* 1 = disable transmitter */ 61 #define US_CR_TXEN 0x00000040U /* 1 = enable transmitter */ 62 #define US_CR_RXDIS 0x00000020U /* 1 = disable receiver */ 63 #define US_CR_RXEN 0x00000010U /* 1 = enable receiver */ 64 #define US_CR_RSTTX 0x00000008U /* 1 = reset transmitter */ 65 #define US_CR_RSTRX 0x00000004U /* 1 = reset receiver */ 66 67 /* Mode Register: */ 68 #define US_MR_FILTER 0x10000000U /* 1 = Infrared Receive filter */ 69 #define US_MR_MAX_ITER 0x07000000U /* maximum number of iterations in ISO7816 */ 70 #define US_MR_MAX_ITER_SHIFT 24 71 #define US_MR_DSNACK 0x00200000U /* 1 = disable successive NACK */ 72 #define US_MR_INACK 0x00100000U /* 1 = the NACK is not generated*/ 73 #define US_MR_OVER 0x00080000U /* 1 = 8x oversampling (0 = 16x */ 74 #define US_MR_CLKO 0x00040000U /* 1 = drive SCK */ 75 #define US_MR_MODE9 0x00020000U /* 9-bit character length */ 76 #define US_MR_MSBF 0x00010000U /* 1 = send MSB first */ 77 78 #define US_MR_CHMODE 0x0000C000U /* channel mode */ 79 #define US_MR_CHMODE_SHIFT 14U 80 #define US_MR_CHMODE_NORMAL 0x00000000U 81 #define US_MR_CHMODE_ECHO 0x00004000U 82 #define US_MR_CHMODE_LOCAL_LOOP 0x00008000U 83 #define US_MR_CHMODE_REMOTE_LOOP 0x0000C000U 84 85 #define US_MR_NBSTOP 0x00003000U /* number of stop bits */ 86 #define US_MR_NBSTOP_SHIFT 12U 87 #define US_MR_NBSTOP_1 0x00000000U 88 #define US_MR_NBSTOP_1_5 0x00001000U 89 #define US_MR_NBSTOP_2 0x00002000U 90 91 #define US_MR_PAR 0x00000E00U /* parity type */ 92 #define US_MR_PAR_SHIFT 9U 93 #define US_MR_PAR_EVEN 0x00000000U 94 #define US_MR_PAR_ODD 0x00000200U 95 #define US_MR_PAR_SPACE 0x00000400U 96 #define US_MR_PAR_MARK 0x00000600U 97 #define US_MR_PAR_NONE 0x00000800U 98 #define US_MR_PAR_MULTI_DROP 0x00000C00U 99 100 #define US_MR_SYNC 0x00000100U /* 1 = synchronous mode */ 101 102 #define US_MR_CHRL 0x000000C0U /* character length */ 103 #define US_MR_CHRL_SHIFT 6U 104 #define US_MR_CHRL_5 0x00000000U 105 #define US_MR_CHRL_6 0x00000040U 106 #define US_MR_CHRL_7 0x00000080U 107 #define US_MR_CHRL_8 0x000000C0U 108 109 #define US_MR_USCLKS 0x00000030U /* clock selection */ 110 #define US_MR_USCLKS_SHIFT 4U 111 #define US_MR_USCLKS_MCK 0x00000000U 112 #define US_MR_USCLKS_MCK_DIV 0x00000010U 113 #define US_MR_USCLKS_SCK 0x00000030U 114 115 #define US_MR_MODE 0x0000000FU 116 #define US_MR_MODE_SHIFT 0U 117 #define US_MR_MODE_NORMAL 0x00000000U 118 #define US_MR_MODE_RS485 0x00000001U 119 #define US_MR_MODE_AUTO_RTSCTS 0x00000002U 120 #define US_MR_MODE_MODEM 0x00000003U 121 #define US_MR_MODE_ISO7816_T0 0x00000004U 122 #define US_MR_MODE_ISO7816_T1 0x00000006U 123 #define US_MR_MODE_IRDA 0x00000008U 124 125 126 /* Interrupt bits: */ 127 #define US_CSR_CTSIC 0x00080000U 128 #define US_CSR_DCDIC 0x00040000U 129 #define US_CSR_DSRIC 0x00020000U 130 #define US_CSR_RIIC 0x00010000U 131 #define US_CSR_NACK 0x00002000U 132 #define US_CSR_RXBUFF 0x00001000U 133 #define US_CSR_TXBUFE 0x00000800U 134 #define US_CSR_ITERATION 0x00000400U 135 #define US_CSR_TXEMPTY 0x00000200U 136 #define US_CSR_TIMEOUT 0x00000100U 137 #define US_CSR_PARE 0x00000080U 138 #define US_CSR_FRAME 0x00000040U 139 #define US_CSR_OVRE 0x00000020U 140 #define US_CSR_ENDTX 0x00000010U 141 #define US_CSR_ENDRX 0x00000008U 142 #define US_CSR_RXBRK 0x00000004U 143 #define US_CSR_TXRDY 0x00000002U 144 #define US_CSR_RXRDY 0x00000001U 145 146 /* Channel Status Register bits (int bits + bits below): */ 147 #define US_CSR_CTS 0x00800000U 148 #define US_CSR_DCD 0x00400000U 149 #define US_CSR_DSR 0x00200000U 150 #define US_CSR_RI 0x00100000U 151 152 153 #define USART_INIT(sc, speed) do { \ 154 at91usart_writereg(sc, US_PDC + PDC_PTCR, \ 155 PDC_PTCR_TXTDIS | PDC_PTCR_RXTDIS); \ 156 at91usart_writereg(sc, US_PDC + PDC_RNCR, 0); \ 157 at91usart_writereg(sc, US_PDC + PDC_RCR, 0); \ 158 at91usart_writereg(sc, US_PDC + PDC_TNCR, 0); \ 159 at91usart_writereg(sc, US_PDC + PDC_TCR, 0); \ 160 at91usart_writereg(sc, US_MR, US_MR_USCLKS_MCK | US_MR_CHRL_8 \ 161 | US_MR_PAR_NONE | US_MR_NBSTOP_1); \ 162 at91usart_writereg(sc, US_BRGR, \ 163 (AT91_MSTCLK / 16 + (speed) / 2) / (speed)); \ 164 at91usart_writereg(sc, US_CR, US_CR_RSTRX | US_CR_RSTTX); \ 165 at91usart_writereg(sc, US_CR, US_CR_RSTSTA | US_CR_RXEN | US_CR_TXEN \ 166 | US_CR_STPBRK); \ 167 (void)at91usart_readreg(sc, US_CSR); \ 168 } while (/*CONSTCOND*/0) 169 170 #if 0 171 #define USART_PUTC(sc, ch) do { \ 172 while ((USARTREG(USART_SR) & USART_SR_TXRDY) == 0) ; \ 173 USARTREG(USART_THR) = ch; \ 174 } while (/*CONSTCOND*/0) 175 176 #define USART_PEEKC() ((USARTREG(USART_SR) & USART_SR_RXRDY) ? USARTREG(USART_RHR) : -1) 177 178 #define USART_PUTS(string) do { \ 179 const char *_ptr = (string); \ 180 while (*_ptr) { \ 181 USART_PUTC(*_ptr); \ 182 _ptr++; \ 183 } \ 184 } while (/*CONSTCOND*/0) 185 #endif 186 187 #endif // _AT91USARTREG_H_ 188 189
Indexes created Sat Sep 20 22:09:52 GMT 2025