bcm2835_bsc.c revision 1.10.2.3
1 /* $NetBSD: bcm2835_bsc.c,v 1.10.2.3 2018/07/28 04:37:27 pgoyette Exp $ */ 2 3 /* 4 * Copyright (c) 2012 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: bcm2835_bsc.c,v 1.10.2.3 2018/07/28 04:37:27 pgoyette Exp $"); 31 32 #if defined(_KERNEL_OPT) 33 #include "opt_kernhist.h" 34 #endif 35 36 #include <sys/param.h> 37 #include <sys/bus.h> 38 #include <sys/device.h> 39 #include <sys/kernhist.h> 40 #include <sys/intr.h> 41 #include <sys/mutex.h> 42 #include <sys/once.h> 43 #include <sys/systm.h> 44 45 #include <dev/i2c/i2cvar.h> 46 47 #include <arm/broadcom/bcm2835reg.h> 48 #include <arm/broadcom/bcm2835_bscreg.h> 49 50 #include <dev/fdt/fdtvar.h> 51 52 KERNHIST_DEFINE(bsciichist); 53 54 struct bsciic_softc { 55 device_t sc_dev; 56 bus_space_tag_t sc_iot; 57 bus_space_handle_t sc_ioh; 58 struct i2c_controller sc_i2c; 59 kmutex_t sc_buslock; 60 void *sc_inth; 61 62 struct clk *sc_clk; 63 u_int sc_frequency; 64 u_int sc_clkrate; 65 }; 66 67 static int bsciic_match(device_t, cfdata_t, void *); 68 static void bsciic_attach(device_t, device_t, void *); 69 70 void bsciic_dump_regs(struct bsciic_softc * const); 71 72 static int bsciic_acquire_bus(void *, int); 73 static void bsciic_release_bus(void *, int); 74 static int bsciic_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t, 75 void *, size_t, int); 76 77 CFATTACH_DECL_NEW(bsciic, sizeof(struct bsciic_softc), 78 bsciic_match, bsciic_attach, NULL, NULL); 79 80 static int 81 bsciic_init(void) 82 { 83 84 KERNHIST_INIT(bsciichist, 512); 85 86 return 0; 87 } 88 89 static int 90 bsciic_match(device_t parent, cfdata_t match, void *aux) 91 { 92 const char * const compatible[] = { "brcm,bcm2835-i2c", NULL }; 93 struct fdt_attach_args * const faa = aux; 94 95 return of_match_compatible(faa->faa_phandle, compatible); 96 } 97 98 static void 99 bsciic_attach(device_t parent, device_t self, void *aux) 100 { 101 struct bsciic_softc * const sc = device_private(self); 102 struct fdt_attach_args * const faa = aux; 103 const int phandle = faa->faa_phandle; 104 prop_dictionary_t prop = device_properties(self); 105 bool disable = false; 106 107 static ONCE_DECL(control); 108 RUN_ONCE(&control, bsciic_init); 109 110 bus_addr_t addr; 111 bus_size_t size; 112 113 sc->sc_dev = self; 114 sc->sc_iot = faa->faa_bst; 115 116 int error = fdtbus_get_reg(phandle, 0, &addr, &size); 117 if (error) { 118 aprint_error(": unable to get device registers\n"); 119 return; 120 } 121 122 prop_dictionary_get_bool(prop, "disable", &disable); 123 if (disable) { 124 aprint_naive(": disabled\n"); 125 aprint_normal(": disabled\n"); 126 return; 127 } 128 129 /* Enable clock */ 130 sc->sc_clk = fdtbus_clock_get_index(phandle, 0); 131 if (sc->sc_clk == NULL) { 132 aprint_error(": couldn't acquire clock\n"); 133 return; 134 } 135 136 if (clk_enable(sc->sc_clk) != 0) { 137 aprint_error(": failed to enable clock\n"); 138 return; 139 } 140 141 sc->sc_frequency = clk_get_rate(sc->sc_clk); 142 143 if (of_getprop_uint32(phandle, "clock-frequency", 144 &sc->sc_clkrate) != 0) { 145 sc->sc_clkrate = 100000; 146 } 147 148 if (bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh)) { 149 aprint_error_dev(sc->sc_dev, "unable to map device\n"); 150 return; 151 } 152 153 aprint_naive("\n"); 154 aprint_normal(": Broadcom Serial Controller\n"); 155 156 mutex_init(&sc->sc_buslock, MUTEX_DEFAULT, IPL_NONE); 157 158 /* clear FIFO, disable controller */ 159 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BSC_C, BSC_C_CLEAR_CLEAR); 160 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BSC_S, BSC_S_CLKT | 161 BSC_S_ERR | BSC_S_DONE); 162 163 u_int divider = howmany(sc->sc_frequency, sc->sc_clkrate); 164 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BSC_DIV, 165 __SHIFTIN(divider, BSC_DIV_CDIV)); 166 167 sc->sc_i2c.ic_cookie = sc; 168 sc->sc_i2c.ic_acquire_bus = bsciic_acquire_bus; 169 sc->sc_i2c.ic_release_bus = bsciic_release_bus; 170 sc->sc_i2c.ic_exec = bsciic_exec; 171 172 fdtbus_attach_i2cbus(self, phandle, &sc->sc_i2c, iicbus_print); 173 } 174 175 void 176 bsciic_dump_regs(struct bsciic_softc * const sc) 177 { 178 KERNHIST_FUNC(__func__); 179 KERNHIST_CALLED(bsciichist); 180 181 KERNHIST_LOG(bsciichist, "C %08jx S %08jx D %08jx A %08jx", 182 bus_space_read_4(sc->sc_iot, sc->sc_ioh, BSC_C), 183 bus_space_read_4(sc->sc_iot, sc->sc_ioh, BSC_S), 184 bus_space_read_4(sc->sc_iot, sc->sc_ioh, BSC_DLEN), 185 bus_space_read_4(sc->sc_iot, sc->sc_ioh, BSC_A) 186 ); 187 } 188 189 static int 190 bsciic_acquire_bus(void *v, int flags) 191 { 192 struct bsciic_softc * const sc = v; 193 uint32_t s __diagused; 194 195 mutex_enter(&sc->sc_buslock); 196 197 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BSC_S, BSC_S_CLKT | 198 BSC_S_ERR | BSC_S_DONE); 199 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BSC_C, BSC_C_I2CEN | 200 BSC_C_CLEAR_CLEAR); 201 s = bus_space_read_4(sc->sc_iot, sc->sc_ioh, BSC_S); 202 KASSERT((s & BSC_S_TA) == 0); 203 204 return 0; 205 } 206 207 static void 208 bsciic_release_bus(void *v, int flags) 209 { 210 struct bsciic_softc * const sc = v; 211 212 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BSC_C, BSC_C_CLEAR_CLEAR); 213 214 mutex_exit(&sc->sc_buslock); 215 } 216 217 static int 218 bsciic_exec(void *v, i2c_op_t op, i2c_addr_t addr, const void *cmdbuf, 219 size_t cmdlen, void *databuf, size_t datalen, int flags) 220 { 221 KERNHIST_FUNC(__func__); KERNHIST_CALLED(bsciichist); 222 struct bsciic_softc * const sc = v; 223 uint32_t c, s, dlen, a; 224 uint32_t j; 225 uint8_t *buf; 226 size_t len; 227 size_t pos; 228 int error = 0; 229 int whichbuf = 0; 230 const bool isread = I2C_OP_READ_P(op); 231 232 /* 233 * XXX We don't do 10-bit addressing correctly yet. 234 */ 235 if (addr > 0x7f) 236 return (ENOTSUP); 237 238 flags |= I2C_F_POLL; 239 240 #if 0 241 device_printf(sc->sc_dev, "exec: op %d, addr 0x%x, cmdbuf %p, " 242 "cmdlen %zu, databuf %p, datalen %zu, flags 0x%x\n", 243 op, addr, cmdbuf, cmdlen, databuf, datalen, flags); 244 #endif 245 246 a = __SHIFTIN(addr, BSC_A_ADDR); 247 c = BSC_C_I2CEN | BSC_C_CLEAR_CLEAR; 248 #if notyet 249 c |= BSC_C_INTR | BSC_C_INTT | BSC_C_INTD; 250 #endif 251 252 if (isread && cmdlen == 0) 253 goto only_read; 254 255 buf = __UNCONST(cmdbuf); 256 len = cmdlen; 257 258 if (isread) 259 dlen = cmdlen; 260 else 261 dlen = cmdlen + datalen; 262 dlen = __SHIFTIN(dlen, BSC_DLEN_DLEN); 263 264 s = bus_space_read_4(sc->sc_iot, sc->sc_ioh, BSC_S); 265 if ((s & BSC_S_TA) != 0) 266 bsciic_dump_regs(sc); 267 KASSERT((s & BSC_S_TA) == 0); 268 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BSC_DLEN, dlen); 269 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BSC_A, a); 270 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BSC_C, c | BSC_C_ST); 271 272 do { 273 s = bus_space_read_4(sc->sc_iot, sc->sc_ioh, BSC_S); 274 } while ((s & BSC_S_TA) == 0); 275 276 flood_again: 277 KERNHIST_LOG(bsciichist, "flood top %#jx %ju", 278 (uintptr_t)buf, len, 0, 0); 279 j = 10000000; 280 for (pos = 0; pos < len; ) { 281 if (--j == 0) 282 return -1; 283 s = bus_space_read_4(sc->sc_iot, sc->sc_ioh, BSC_S); 284 KERNHIST_LOG(bsciichist, "w s %08jx", s, 0, 0, 0); 285 if ((s & BSC_S_CLKT) != 0) { 286 error = EIO; 287 goto done; 288 } 289 if ((s & BSC_S_ERR) != 0) { 290 error = EIO; 291 goto done; 292 } 293 if ((s & BSC_S_DONE) != 0) 294 break; 295 if ((s & BSC_S_TXD) == 0) 296 continue; 297 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BSC_FIFO, buf[pos]); 298 KERNHIST_LOG(bsciichist, "w %#jx %#jx %02jx", 299 (uintptr_t)buf, (uintptr_t)&buf[pos], 300 buf[pos], 0); 301 pos++; 302 } 303 KERNHIST_LOG(bsciichist, "flood bot %#jx %ju", 304 (uintptr_t)buf, len, 0, 0); 305 306 if (whichbuf == 0 && !isread) { 307 KASSERT(buf == cmdbuf); 308 whichbuf++; 309 buf = databuf; 310 len = datalen; 311 if (len) 312 goto flood_again; 313 } 314 315 do { 316 s = bus_space_read_4(sc->sc_iot, sc->sc_ioh, BSC_S); 317 } while ((s & BSC_S_TA) != 0); 318 319 s = bus_space_read_4(sc->sc_iot, sc->sc_ioh, BSC_S); 320 s &= BSC_S_CLKT|BSC_S_ERR|BSC_S_DONE; 321 KASSERT((s & BSC_S_DONE) != 0); 322 if (s != 0) 323 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BSC_S, s); 324 325 if (error == 0 && (s & (BSC_S_CLKT|BSC_S_ERR)) != 0) 326 error = EIO; 327 328 if (!isread) 329 goto done; 330 331 only_read: 332 c |= BSC_C_READ; 333 334 buf = databuf; 335 len = datalen; 336 dlen = datalen; 337 338 dlen = __SHIFTIN(dlen, BSC_DLEN_DLEN); 339 #if 0 340 KASSERT(dlen >= 1); 341 #endif 342 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BSC_DLEN, dlen); 343 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BSC_A, a); 344 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BSC_C, c | BSC_C_ST); 345 346 do { 347 s = bus_space_read_4(sc->sc_iot, sc->sc_ioh, BSC_S); 348 } while ((s & BSC_S_TA) == 0); 349 350 KERNHIST_LOG(bsciichist, "drain top %#jx %ju", 351 (uintptr_t)buf, len, 0, 0); 352 j = 10000000; 353 for (pos = 0; pos < len; ) { 354 if (--j == 0) 355 return -1; 356 s = bus_space_read_4(sc->sc_iot, sc->sc_ioh, BSC_S); 357 KERNHIST_LOG(bsciichist, "r s %08jx", s, 0, 0, 0); 358 if ((s & BSC_S_CLKT) != 0) { 359 error = EIO; 360 goto done; 361 } 362 if ((s & BSC_S_ERR) != 0) { 363 error = EIO; 364 goto done; 365 } 366 if ((s & BSC_S_DONE) != 0) 367 break; 368 if ((s & BSC_S_RXD) == 0) 369 continue; 370 j = 10000000; 371 buf[pos] = bus_space_read_4(sc->sc_iot, sc->sc_ioh, BSC_FIFO); 372 KERNHIST_LOG(bsciichist, "r %#jx %#jx %02jx", 373 (uintptr_t)buf, (uintptr_t)&buf[pos], 374 buf[pos], 0); 375 pos++; 376 } 377 KERNHIST_LOG(bsciichist, "drain bot %#jx %ju", (uintptr_t)buf, len, 378 0, 0); 379 380 do { 381 s = bus_space_read_4(sc->sc_iot, sc->sc_ioh, BSC_S); 382 } while ((s & BSC_S_TA) != 0); 383 384 s = bus_space_read_4(sc->sc_iot, sc->sc_ioh, BSC_S); 385 s &= BSC_S_CLKT|BSC_S_ERR|BSC_S_DONE; 386 KASSERT((s & BSC_S_DONE) != 0); 387 if (s != 0) 388 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BSC_S, s); 389 390 done: 391 bsciic_dump_regs(sc); 392 393 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BSC_DLEN, 0); 394 395 do { 396 s = bus_space_read_4(sc->sc_iot, sc->sc_ioh, BSC_S); 397 } while ((s & BSC_S_TA) != 0); 398 399 bsciic_dump_regs(sc); 400 401 s = bus_space_read_4(sc->sc_iot, sc->sc_ioh, BSC_S); 402 s &= BSC_S_CLKT|BSC_S_ERR|BSC_S_DONE; 403 if (s != 0) 404 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BSC_S, s); 405 406 bsciic_dump_regs(sc); 407 408 if (error == 0 && (s & (BSC_S_CLKT|BSC_S_ERR)) != 0) 409 error = EIO; 410 411 return error; 412 } 413
Indexes created Tue Oct 21 12:09:54 GMT 2025