bcm2835_bsc.c revision 1.8
1 /* $NetBSD: bcm2835_bsc.c,v 1.8 2017/12/10 21:38:26 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2012 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: bcm2835_bsc.c,v 1.8 2017/12/10 21:38:26 skrll Exp $"); 31 32 #if defined(_KERNEL_OPT) 33 #include "opt_kernhist.h" 34 #endif 35 36 #include <sys/param.h> 37 #include <sys/bus.h> 38 #include <sys/device.h> 39 #include <sys/kernhist.h> 40 #include <sys/intr.h> 41 #include <sys/mutex.h> 42 #include <sys/once.h> 43 #include <sys/systm.h> 44 45 #include <dev/i2c/i2cvar.h> 46 47 #include <arm/broadcom/bcm2835reg.h> 48 #include <arm/broadcom/bcm2835_bscreg.h> 49 50 #include <dev/fdt/fdtvar.h> 51 52 KERNHIST_DEFINE(bsciichist); 53 54 struct bsciic_softc { 55 device_t sc_dev; 56 bus_space_tag_t sc_iot; 57 bus_space_handle_t sc_ioh; 58 struct i2c_controller sc_i2c; 59 kmutex_t sc_buslock; 60 void *sc_inth; 61 62 struct clk *sc_clk; 63 u_int sc_frequency; 64 u_int sc_clkrate; 65 }; 66 67 static int bsciic_match(device_t, cfdata_t, void *); 68 static void bsciic_attach(device_t, device_t, void *); 69 70 void bsciic_dump_regs(struct bsciic_softc * const); 71 72 static int bsciic_acquire_bus(void *, int); 73 static void bsciic_release_bus(void *, int); 74 static int bsciic_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t, 75 void *, size_t, int); 76 77 CFATTACH_DECL_NEW(bsciic, sizeof(struct bsciic_softc), 78 bsciic_match, bsciic_attach, NULL, NULL); 79 80 static int 81 bsciic_init(void) 82 { 83 84 KERNHIST_INIT(bsciichist, 512); 85 86 return 0; 87 } 88 89 static int 90 bsciic_match(device_t parent, cfdata_t match, void *aux) 91 { 92 const char * const compatible[] = { "brcm,bcm2835-i2c", NULL }; 93 struct fdt_attach_args * const faa = aux; 94 95 return of_match_compatible(faa->faa_phandle, compatible); 96 } 97 98 static void 99 bsciic_attach(device_t parent, device_t self, void *aux) 100 { 101 struct bsciic_softc * const sc = device_private(self); 102 struct fdt_attach_args * const faa = aux; 103 const int phandle = faa->faa_phandle; 104 prop_dictionary_t prop = device_properties(self); 105 struct i2cbus_attach_args iba; 106 bool disable = false; 107 108 static ONCE_DECL(control); 109 RUN_ONCE(&control, bsciic_init); 110 111 bus_addr_t addr; 112 bus_size_t size; 113 114 sc->sc_dev = self; 115 sc->sc_iot = faa->faa_bst; 116 117 int error = fdtbus_get_reg(phandle, 0, &addr, &size); 118 if (error) { 119 aprint_error(": unable to get device registers\n"); 120 return; 121 } 122 123 prop_dictionary_get_bool(prop, "disable", &disable); 124 if (disable) { 125 aprint_naive(": disabled\n"); 126 aprint_normal(": disabled\n"); 127 return; 128 } 129 130 /* Enable clock */ 131 sc->sc_clk = fdtbus_clock_get_index(phandle, 0); 132 if (sc->sc_clk == NULL) { 133 aprint_error(": couldn't acquire clock\n"); 134 return; 135 } 136 137 if (clk_enable(sc->sc_clk) != 0) { 138 aprint_error(": failed to enable clock\n"); 139 return; 140 } 141 142 sc->sc_frequency = clk_get_rate(sc->sc_clk); 143 144 if (of_getprop_uint32(phandle, "clock-frequency", 145 &sc->sc_clkrate) != 0) { 146 sc->sc_clkrate = 100000; 147 } 148 149 if (bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh)) { 150 aprint_error_dev(sc->sc_dev, "unable to map device\n"); 151 return; 152 } 153 154 aprint_naive("\n"); 155 aprint_normal(": Broadcom Serial Controller\n"); 156 157 mutex_init(&sc->sc_buslock, MUTEX_DEFAULT, IPL_NONE); 158 159 /* clear FIFO, disable controller */ 160 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BSC_C, BSC_C_CLEAR_CLEAR); 161 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BSC_S, BSC_S_CLKT | 162 BSC_S_ERR | BSC_S_DONE); 163 164 u_int divider = howmany(sc->sc_frequency, sc->sc_clkrate); 165 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BSC_DIV, 166 __SHIFTIN(divider, BSC_DIV_CDIV)); 167 168 sc->sc_i2c.ic_cookie = sc; 169 sc->sc_i2c.ic_acquire_bus = bsciic_acquire_bus; 170 sc->sc_i2c.ic_release_bus = bsciic_release_bus; 171 sc->sc_i2c.ic_exec = bsciic_exec; 172 173 memset(&iba, 0, sizeof(iba)); 174 175 iba.iba_tag = &sc->sc_i2c; 176 iba.iba_type = 0; 177 config_found_ia(self, "i2cbus", &iba, iicbus_print); 178 } 179 180 void 181 bsciic_dump_regs(struct bsciic_softc * const sc) 182 { 183 KERNHIST_FUNC(__func__); 184 KERNHIST_CALLED(bsciichist); 185 186 KERNHIST_LOG(bsciichist, "C %08jx S %08jx D %08jx A %08jx", 187 bus_space_read_4(sc->sc_iot, sc->sc_ioh, BSC_C), 188 bus_space_read_4(sc->sc_iot, sc->sc_ioh, BSC_S), 189 bus_space_read_4(sc->sc_iot, sc->sc_ioh, BSC_DLEN), 190 bus_space_read_4(sc->sc_iot, sc->sc_ioh, BSC_A) 191 ); 192 } 193 194 static int 195 bsciic_acquire_bus(void *v, int flags) 196 { 197 struct bsciic_softc * const sc = v; 198 uint32_t s __diagused; 199 200 mutex_enter(&sc->sc_buslock); 201 202 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BSC_S, BSC_S_CLKT | 203 BSC_S_ERR | BSC_S_DONE); 204 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BSC_C, BSC_C_I2CEN | 205 BSC_C_CLEAR_CLEAR); 206 s = bus_space_read_4(sc->sc_iot, sc->sc_ioh, BSC_S); 207 KASSERT((s & BSC_S_TA) == 0); 208 209 return 0; 210 } 211 212 static void 213 bsciic_release_bus(void *v, int flags) 214 { 215 struct bsciic_softc * const sc = v; 216 217 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BSC_C, BSC_C_CLEAR_CLEAR); 218 219 mutex_exit(&sc->sc_buslock); 220 } 221 222 static int 223 bsciic_exec(void *v, i2c_op_t op, i2c_addr_t addr, const void *cmdbuf, 224 size_t cmdlen, void *databuf, size_t datalen, int flags) 225 { 226 KERNHIST_FUNC(__func__); KERNHIST_CALLED(bsciichist); 227 struct bsciic_softc * const sc = v; 228 uint32_t c, s, dlen, a; 229 uint32_t j; 230 uint8_t *buf; 231 size_t len; 232 size_t pos; 233 int error = 0; 234 const bool isread = I2C_OP_READ_P(op); 235 236 flags |= I2C_F_POLL; 237 238 #if 0 239 device_printf(sc->sc_dev, "exec: op %d, addr 0x%x, cmdbuf %p, " 240 "cmdlen %zu, databuf %p, datalen %zu, flags 0x%x\n", 241 op, addr, cmdbuf, cmdlen, databuf, datalen, flags); 242 #endif 243 244 a = __SHIFTIN(addr, BSC_A_ADDR); 245 c = BSC_C_I2CEN | BSC_C_CLEAR_CLEAR; 246 #if notyet 247 c |= BSC_C_INTR | BSC_C_INTT | BSC_C_INTD; 248 #endif 249 250 if (isread && cmdlen == 0) 251 goto only_read; 252 253 buf = __UNCONST(cmdbuf); 254 len = cmdlen; 255 256 if (isread) 257 dlen = cmdlen; 258 else 259 dlen = cmdlen + datalen; 260 dlen = __SHIFTIN(dlen, BSC_DLEN_DLEN); 261 262 s = bus_space_read_4(sc->sc_iot, sc->sc_ioh, BSC_S); 263 if ((s & BSC_S_TA) != 0) 264 bsciic_dump_regs(sc); 265 KASSERT((s & BSC_S_TA) == 0); 266 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BSC_DLEN, dlen); 267 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BSC_A, a); 268 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BSC_C, c | BSC_C_ST); 269 270 do { 271 s = bus_space_read_4(sc->sc_iot, sc->sc_ioh, BSC_S); 272 } while ((s & BSC_S_TA) == 0); 273 274 flood_again: 275 KERNHIST_LOG(bsciichist, "flood top %#jx %ju", 276 (uintptr_t)buf, len, 0, 0); 277 j = 10000000; 278 for (pos = 0; pos < len; ) { 279 if (--j == 0) 280 return -1; 281 s = bus_space_read_4(sc->sc_iot, sc->sc_ioh, BSC_S); 282 KERNHIST_LOG(bsciichist, "w s %08jx", s, 0, 0, 0); 283 if ((s & BSC_S_CLKT) != 0) { 284 error = EIO; 285 goto done; 286 } 287 if ((s & BSC_S_ERR) != 0) { 288 error = EIO; 289 goto done; 290 } 291 if ((s & BSC_S_DONE) != 0) 292 break; 293 if ((s & BSC_S_TXD) == 0) 294 continue; 295 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BSC_FIFO, buf[pos]); 296 KERNHIST_LOG(bsciichist, "w %#jx %#jx %02jx", 297 (uintptr_t)buf, (uintptr_t)&buf[pos], 298 buf[pos], 0); 299 pos++; 300 } 301 KERNHIST_LOG(bsciichist, "flood bot %#jx %ju", 302 (uintptr_t)buf, len, 0, 0); 303 304 if (buf == cmdbuf && !isread) { 305 buf = databuf; 306 len = datalen; 307 goto flood_again; 308 } 309 310 do { 311 s = bus_space_read_4(sc->sc_iot, sc->sc_ioh, BSC_S); 312 } while ((s & BSC_S_TA) != 0); 313 314 s = bus_space_read_4(sc->sc_iot, sc->sc_ioh, BSC_S); 315 s &= BSC_S_CLKT|BSC_S_ERR|BSC_S_DONE; 316 KASSERT((s & BSC_S_DONE) != 0); 317 if (s != 0) 318 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BSC_S, s); 319 320 if (error == 0 && (s & (BSC_S_CLKT|BSC_S_ERR)) != 0) 321 error = EIO; 322 323 if (!isread) 324 goto done; 325 326 only_read: 327 c |= BSC_C_READ; 328 329 buf = databuf; 330 len = datalen; 331 dlen = datalen; 332 333 dlen = __SHIFTIN(dlen, BSC_DLEN_DLEN); 334 KASSERT(dlen >= 1); 335 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BSC_DLEN, dlen); 336 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BSC_A, a); 337 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BSC_C, c | BSC_C_ST); 338 339 do { 340 s = bus_space_read_4(sc->sc_iot, sc->sc_ioh, BSC_S); 341 } while ((s & BSC_S_TA) == 0); 342 343 KERNHIST_LOG(bsciichist, "drain top %#jx %ju", 344 (uintptr_t)buf, len, 0, 0); 345 j = 10000000; 346 for (pos = 0; pos < len; ) { 347 if (--j == 0) 348 return -1; 349 s = bus_space_read_4(sc->sc_iot, sc->sc_ioh, BSC_S); 350 KERNHIST_LOG(bsciichist, "r s %08jx", s, 0, 0, 0); 351 if ((s & BSC_S_CLKT) != 0) { 352 error = EIO; 353 goto done; 354 } 355 if ((s & BSC_S_ERR) != 0) { 356 error = EIO; 357 goto done; 358 } 359 if ((s & BSC_S_DONE) != 0) 360 break; 361 if ((s & BSC_S_RXD) == 0) 362 continue; 363 j = 10000000; 364 buf[pos] = bus_space_read_4(sc->sc_iot, sc->sc_ioh, BSC_FIFO); 365 KERNHIST_LOG(bsciichist, "r %#jx %#jx %02jx", 366 (uintptr_t)buf, (uintptr_t)&buf[pos], 367 buf[pos], 0); 368 pos++; 369 } 370 KERNHIST_LOG(bsciichist, "drain bot %#jx %ju", (uintptr_t)buf, len, 371 0, 0); 372 373 do { 374 s = bus_space_read_4(sc->sc_iot, sc->sc_ioh, BSC_S); 375 } while ((s & BSC_S_TA) != 0); 376 377 s = bus_space_read_4(sc->sc_iot, sc->sc_ioh, BSC_S); 378 s &= BSC_S_CLKT|BSC_S_ERR|BSC_S_DONE; 379 KASSERT((s & BSC_S_DONE) != 0); 380 if (s != 0) 381 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BSC_S, s); 382 383 done: 384 bsciic_dump_regs(sc); 385 386 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BSC_DLEN, 0); 387 388 do { 389 s = bus_space_read_4(sc->sc_iot, sc->sc_ioh, BSC_S); 390 } while ((s & BSC_S_TA) != 0); 391 392 bsciic_dump_regs(sc); 393 394 s = bus_space_read_4(sc->sc_iot, sc->sc_ioh, BSC_S); 395 s &= BSC_S_CLKT|BSC_S_ERR|BSC_S_DONE; 396 if (s != 0) 397 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BSC_S, s); 398 399 bsciic_dump_regs(sc); 400 401 if (error == 0 && (s & (BSC_S_CLKT|BSC_S_ERR)) != 0) 402 error = EIO; 403 404 return error; 405 } 406
Indexes created Tue Sep 30 11:09:46 GMT 2025