1 /* $NetBSD: bcm2835_emmc.c,v 1.44 2025/09/25 01:19:15 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Nick Hudson 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: bcm2835_emmc.c,v 1.44 2025/09/25 01:19:15 jmcneill Exp $"); 34 35 #include "bcmdmac.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/device.h> 40 #include <sys/bus.h> 41 #include <sys/condvar.h> 42 #include <sys/mutex.h> 43 #include <sys/kernel.h> 44 45 #include <arm/broadcom/bcm2835reg.h> 46 #include <arm/broadcom/bcm2835_dmac.h> 47 48 #include <dev/sdmmc/sdhcreg.h> 49 #include <dev/sdmmc/sdhcvar.h> 50 #include <dev/sdmmc/sdmmcvar.h> 51 52 #include <dev/fdt/fdtvar.h> 53 54 #include <arm/fdt/arm_fdtvar.h> 55 56 enum bcmemmc_dma_state { 57 EMMC_DMA_STATE_IDLE, 58 EMMC_DMA_STATE_BUSY, 59 }; 60 61 struct bcmemmc_softc { 62 struct sdhc_softc sc; 63 64 bus_space_tag_t sc_iot; 65 bus_space_handle_t sc_ioh; 66 bus_addr_t sc_iob; 67 bus_size_t sc_ios; 68 struct sdhc_host *sc_hosts[1]; 69 void *sc_ih; 70 int sc_phandle; 71 72 kcondvar_t sc_cv; 73 74 enum bcmemmc_dma_state sc_state; 75 76 struct bcm_dmac_channel *sc_dmac; 77 78 bus_dmamap_t sc_dmamap; 79 bus_dma_segment_t sc_segs[1]; /* XXX assumes enough descriptors fit in one page */ 80 struct bcm_dmac_conblk *sc_cblk; 81 }; 82 83 static int bcmemmc_match(device_t, struct cfdata *, void *); 84 static void bcmemmc_attach(device_t, device_t, void *); 85 static void bcmemmc_attach_i(device_t); 86 #if NBCMDMAC > 0 87 static int bcmemmc_xfer_data_dma(struct sdhc_softc *, struct sdmmc_command *); 88 static void bcmemmc_dma_done(uint32_t, uint32_t, void *); 89 #endif 90 91 CFATTACH_DECL_NEW(bcmemmc, sizeof(struct bcmemmc_softc), 92 bcmemmc_match, bcmemmc_attach, NULL, NULL); 93 94 enum bcmemmc_type { 95 BCM2835_SDHCI, 96 BCM2711_EMMC2, 97 }; 98 99 static const struct device_compatible_entry compat_data[] = { 100 { .compat = "brcm,bcm2835-sdhci", .value = BCM2835_SDHCI }, 101 { .compat = "brcm,bcm2711-emmc2", .value = BCM2711_EMMC2 }, 102 DEVICE_COMPAT_EOL 103 }; 104 105 /* ARGSUSED */ 106 static int 107 bcmemmc_match(device_t parent, struct cfdata *match, void *aux) 108 { 109 struct fdt_attach_args * const faa = aux; 110 111 return of_compatible_match(faa->faa_phandle, compat_data); 112 } 113 114 /* ARGSUSED */ 115 static void 116 bcmemmc_attach(device_t parent, device_t self, void *aux) 117 { 118 struct bcmemmc_softc *sc = device_private(self); 119 struct fdt_attach_args * const faa = aux; 120 const int phandle = faa->faa_phandle; 121 int error; 122 123 sc->sc.sc_dev = self; 124 sc->sc.sc_dmat = faa->faa_dmat; 125 sc->sc.sc_flags = 0; 126 sc->sc.sc_flags |= SDHC_FLAG_32BIT_ACCESS; 127 sc->sc.sc_flags |= SDHC_FLAG_NO_PWR0; 128 sc->sc.sc_flags |= SDHC_FLAG_HOSTCAPS; 129 sc->sc.sc_flags |= SDHC_FLAG_NO_HS_BIT; 130 sc->sc.sc_caps = SDHC_VOLTAGE_SUPP_3_3V | SDHC_HIGH_SPEED_SUPP | 131 (SDHC_MAX_BLK_LEN_1024 << SDHC_MAX_BLK_LEN_SHIFT); 132 133 sc->sc.sc_host = sc->sc_hosts; 134 sc->sc.sc_clkbase = 50000; /* Default to 50MHz */ 135 sc->sc_iot = faa->faa_bst; 136 137 bus_addr_t addr; 138 bus_size_t size; 139 140 error = fdtbus_get_reg(phandle, 0, &addr, &size); 141 if (error) { 142 aprint_error_dev(sc->sc.sc_dev, "unable to map device\n"); 143 return; 144 } 145 sc->sc_phandle = phandle; 146 147 /* Enable clocks */ 148 struct clk *clk; 149 for (int i = 0; (clk = fdtbus_clock_get_index(phandle, i)); i++) { 150 if (clk_enable(clk) != 0) { 151 aprint_error(": failed to enable clock #%d\n", i); 152 return; 153 } 154 if (i == 0) 155 sc->sc.sc_clkbase = clk_get_rate(clk) / 1000; 156 } 157 aprint_debug_dev(self, "ref freq %u kHz\n", sc->sc.sc_clkbase); 158 159 error = bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh); 160 if (error) { 161 aprint_error_dev(sc->sc.sc_dev, "unable to map device\n"); 162 return; 163 } 164 sc->sc_iob = addr; 165 sc->sc_ios = size; 166 167 aprint_naive(": SDHC controller\n"); 168 aprint_normal(": SDHC controller\n"); 169 170 char intrstr[128]; 171 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 172 aprint_error(": failed to decode interrupt\n"); 173 return; 174 } 175 176 sc->sc_ih = fdtbus_intr_establish_xname(phandle, 0, IPL_SDMMC, 0, 177 sdhc_intr, &sc->sc, device_xname(self)); 178 179 if (sc->sc_ih == NULL) { 180 aprint_error_dev(self, "failed to establish interrupt %s\n", 181 intrstr); 182 goto fail; 183 } 184 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 185 186 #if NBCMDMAC > 0 187 enum bcmemmc_type type = 188 of_compatible_lookup(phandle, compat_data)->value; 189 190 if (type != BCM2835_SDHCI) 191 goto done; 192 193 sc->sc_dmac = bcm_dmac_alloc(BCM_DMAC_TYPE_NORMAL, IPL_SDMMC, 194 bcmemmc_dma_done, sc); 195 if (sc->sc_dmac == NULL) 196 goto done; 197 198 sc->sc.sc_flags |= SDHC_FLAG_USE_DMA; 199 sc->sc.sc_flags |= SDHC_FLAG_EXTERNAL_DMA; 200 sc->sc.sc_caps |= SDHC_DMA_SUPPORT; 201 sc->sc.sc_vendor_transfer_data_dma = bcmemmc_xfer_data_dma; 202 203 sc->sc_state = EMMC_DMA_STATE_IDLE; 204 cv_init(&sc->sc_cv, "bcmemmcdma"); 205 206 int rseg; 207 error = bus_dmamem_alloc(sc->sc.sc_dmat, PAGE_SIZE, PAGE_SIZE, 208 PAGE_SIZE, sc->sc_segs, 1, &rseg, BUS_DMA_WAITOK); 209 if (error) { 210 aprint_error_dev(self, "dmamem_alloc failed (%d)\n", error); 211 goto fail; 212 } 213 214 error = bus_dmamem_map(sc->sc.sc_dmat, sc->sc_segs, rseg, PAGE_SIZE, 215 (void **)&sc->sc_cblk, BUS_DMA_WAITOK); 216 if (error) { 217 aprint_error_dev(self, "dmamem_map failed (%d)\n", error); 218 goto fail; 219 } 220 KASSERT(sc->sc_cblk != NULL); 221 222 memset(sc->sc_cblk, 0, PAGE_SIZE); 223 224 error = bus_dmamap_create(sc->sc.sc_dmat, PAGE_SIZE, 1, PAGE_SIZE, 0, 225 BUS_DMA_WAITOK, &sc->sc_dmamap); 226 if (error) { 227 aprint_error_dev(self, "dmamap_create failed (%d)\n", error); 228 goto fail; 229 } 230 231 error = bus_dmamap_load(sc->sc.sc_dmat, sc->sc_dmamap, sc->sc_cblk, 232 PAGE_SIZE, NULL, BUS_DMA_WAITOK|BUS_DMA_WRITE); 233 if (error) { 234 aprint_error_dev(self, "dmamap_load failed (%d)\n", error); 235 goto fail; 236 } 237 238 done: 239 #endif 240 config_interrupts(self, bcmemmc_attach_i); 241 return; 242 243 fail: 244 /* XXX add bus_dma failure cleanup */ 245 if (sc->sc_ih) { 246 fdtbus_intr_disestablish(sc->sc_phandle, sc->sc_ih); 247 sc->sc_ih = NULL; 248 } 249 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios); 250 } 251 252 static void 253 bcmemmc_attach_i(device_t self) 254 { 255 struct bcmemmc_softc * const sc = device_private(self); 256 int error; 257 258 error = sdhc_host_found(&sc->sc, sc->sc_iot, sc->sc_ioh, sc->sc_ios); 259 if (error != 0) { 260 aprint_error_dev(self, "couldn't initialize host, error=%d\n", 261 error); 262 goto fail; 263 } 264 return; 265 266 fail: 267 /* XXX add bus_dma failure cleanup */ 268 if (sc->sc_ih) { 269 fdtbus_intr_disestablish(sc->sc_phandle, sc->sc_ih); 270 sc->sc_ih = NULL; 271 } 272 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios); 273 } 274 275 #if NBCMDMAC > 0 276 static int 277 bcmemmc_xfer_data_dma(struct sdhc_softc *sdhc_sc, struct sdmmc_command *cmd) 278 { 279 struct bcmemmc_softc * const sc = device_private(sdhc_sc->sc_dev); 280 kmutex_t *plock = sdhc_host_lock(sc->sc_hosts[0]); 281 const bus_addr_t ad_sdhcdata = sc->sc_iob + SDHC_DATA; 282 size_t seg; 283 int error; 284 285 KASSERT(mutex_owned(plock)); 286 287 for (seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) { 288 sc->sc_cblk[seg].cb_ti = 289 __SHIFTIN(11, DMAC_TI_PERMAP); /* e.MMC */ 290 sc->sc_cblk[seg].cb_txfr_len = 291 cmd->c_dmamap->dm_segs[seg].ds_len; 292 /* 293 * All transfers are assumed to be multiples of 32-bits. 294 */ 295 KASSERTMSG((sc->sc_cblk[seg].cb_txfr_len & 0x3) == 0, 296 "seg %zu len %d", seg, sc->sc_cblk[seg].cb_txfr_len); 297 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 298 sc->sc_cblk[seg].cb_ti |= DMAC_TI_DEST_INC; 299 /* 300 * Use 128-bit mode if transfer is a multiple of 301 * 16-bytes. 302 */ 303 if ((sc->sc_cblk[seg].cb_txfr_len & 0xf) == 0) 304 sc->sc_cblk[seg].cb_ti |= DMAC_TI_DEST_WIDTH; 305 sc->sc_cblk[seg].cb_ti |= DMAC_TI_SRC_DREQ; 306 sc->sc_cblk[seg].cb_source_ad = ad_sdhcdata; 307 sc->sc_cblk[seg].cb_dest_ad = 308 cmd->c_dmamap->dm_segs[seg].ds_addr; 309 } else { 310 sc->sc_cblk[seg].cb_ti |= DMAC_TI_SRC_INC; 311 /* 312 * Use 128-bit mode if transfer is a multiple of 313 * 16-bytes. 314 */ 315 if ((sc->sc_cblk[seg].cb_txfr_len & 0xf) == 0) 316 sc->sc_cblk[seg].cb_ti |= DMAC_TI_SRC_WIDTH; 317 sc->sc_cblk[seg].cb_ti |= DMAC_TI_DEST_DREQ; 318 sc->sc_cblk[seg].cb_ti |= DMAC_TI_WAIT_RESP; 319 sc->sc_cblk[seg].cb_source_ad = 320 cmd->c_dmamap->dm_segs[seg].ds_addr; 321 sc->sc_cblk[seg].cb_dest_ad = ad_sdhcdata; 322 } 323 sc->sc_cblk[seg].cb_stride = 0; 324 if (seg == cmd->c_dmamap->dm_nsegs - 1) { 325 sc->sc_cblk[seg].cb_ti |= DMAC_TI_INTEN; 326 sc->sc_cblk[seg].cb_nextconbk = 0; 327 } else { 328 sc->sc_cblk[seg].cb_nextconbk = 329 sc->sc_dmamap->dm_segs[0].ds_addr + 330 sizeof(struct bcm_dmac_conblk) * (seg+1); 331 } 332 bcm_dmac_swap_conblk(&sc->sc_cblk[seg]); 333 sc->sc_cblk[seg].cb_padding[0] = 0; 334 sc->sc_cblk[seg].cb_padding[1] = 0; 335 } 336 337 bus_dmamap_sync(sc->sc.sc_dmat, sc->sc_dmamap, 0, 338 sc->sc_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 339 340 error = 0; 341 342 KASSERT(sc->sc_state == EMMC_DMA_STATE_IDLE); 343 sc->sc_state = EMMC_DMA_STATE_BUSY; 344 bcm_dmac_set_conblk_addr(sc->sc_dmac, 345 sc->sc_dmamap->dm_segs[0].ds_addr); 346 error = bcm_dmac_transfer(sc->sc_dmac); 347 if (error) 348 return error; 349 350 while (sc->sc_state == EMMC_DMA_STATE_BUSY) { 351 error = cv_timedwait(&sc->sc_cv, plock, hz * 10); 352 if (error == EWOULDBLOCK) { 353 device_printf(sc->sc.sc_dev, "transfer timeout!\n"); 354 bcm_dmac_halt(sc->sc_dmac); 355 sc->sc_state = EMMC_DMA_STATE_IDLE; 356 error = ETIMEDOUT; 357 break; 358 } 359 } 360 361 bus_dmamap_sync(sc->sc.sc_dmat, sc->sc_dmamap, 0, 362 sc->sc_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 363 364 return error; 365 } 366 367 static void 368 bcmemmc_dma_done(uint32_t status, uint32_t error, void *arg) 369 { 370 struct bcmemmc_softc * const sc = arg; 371 kmutex_t *plock = sdhc_host_lock(sc->sc_hosts[0]); 372 373 if (status != (DMAC_CS_INT|DMAC_CS_END)) 374 device_printf(sc->sc.sc_dev, "status %#x error %#x\n", 375 status,error); 376 377 mutex_enter(plock); 378 KASSERT(sc->sc_state == EMMC_DMA_STATE_BUSY); 379 if (status & DMAC_CS_END) 380 sc->sc_state = EMMC_DMA_STATE_IDLE; 381 cv_broadcast(&sc->sc_cv); 382 mutex_exit(plock); 383 } 384 #endif 385
Indexes created Fri Sep 26 20:09:58 GMT 2025