bcm2835_emmc.c revision 1.1.4.5
1 /* $NetBSD: bcm2835_emmc.c,v 1.1.4.5 2017/12/03 11:35:52 jdolecek Exp $ */ 2 3 /*- 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Nick Hudson 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: bcm2835_emmc.c,v 1.1.4.5 2017/12/03 11:35:52 jdolecek Exp $"); 34 35 #include "bcmdmac.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/device.h> 40 #include <sys/bus.h> 41 #include <sys/condvar.h> 42 #include <sys/mutex.h> 43 #include <sys/kernel.h> 44 45 #include <arm/broadcom/bcm2835reg.h> 46 #include <arm/broadcom/bcm_amba.h> 47 #include <arm/broadcom/bcm2835_dmac.h> 48 49 #include <dev/sdmmc/sdhcreg.h> 50 #include <dev/sdmmc/sdhcvar.h> 51 #include <dev/sdmmc/sdmmcvar.h> 52 53 enum bcmemmc_dma_state { 54 EMMC_DMA_STATE_IDLE, 55 EMMC_DMA_STATE_BUSY, 56 }; 57 58 struct bcmemmc_softc { 59 struct sdhc_softc sc; 60 61 bus_space_tag_t sc_iot; 62 bus_space_handle_t sc_ioh; 63 bus_addr_t sc_iob; 64 bus_size_t sc_ios; 65 struct sdhc_host *sc_hosts[1]; 66 void *sc_ih; 67 68 kcondvar_t sc_cv; 69 70 enum bcmemmc_dma_state sc_state; 71 72 struct bcm_dmac_channel *sc_dmac; 73 74 bus_dmamap_t sc_dmamap; 75 bus_dma_segment_t sc_segs[1]; /* XXX assumes enough descriptors fit in one page */ 76 struct bcm_dmac_conblk *sc_cblk; 77 }; 78 79 static int bcmemmc_match(device_t, struct cfdata *, void *); 80 static void bcmemmc_attach(device_t, device_t, void *); 81 static void bcmemmc_attach_i(device_t); 82 #if NBCMDMAC > 0 83 static int bcmemmc_xfer_data_dma(struct sdhc_softc *, struct sdmmc_command *); 84 static void bcmemmc_dma_done(uint32_t, uint32_t, void *); 85 #endif 86 87 CFATTACH_DECL_NEW(bcmemmc, sizeof(struct bcmemmc_softc), 88 bcmemmc_match, bcmemmc_attach, NULL, NULL); 89 90 /* ARGSUSED */ 91 static int 92 bcmemmc_match(device_t parent, struct cfdata *match, void *aux) 93 { 94 struct amba_attach_args *aaa = aux; 95 96 if (strcmp(aaa->aaa_name, "emmc") != 0) 97 return 0; 98 99 return 1; 100 } 101 102 /* ARGSUSED */ 103 static void 104 bcmemmc_attach(device_t parent, device_t self, void *aux) 105 { 106 struct bcmemmc_softc *sc = device_private(self); 107 prop_dictionary_t dict = device_properties(self); 108 struct amba_attach_args *aaa = aux; 109 prop_number_t frequency; 110 bool disable = false; 111 int error; 112 113 sc->sc.sc_dev = self; 114 sc->sc.sc_dmat = aaa->aaa_dmat; 115 sc->sc.sc_flags = 0; 116 sc->sc.sc_flags |= SDHC_FLAG_32BIT_ACCESS; 117 sc->sc.sc_flags |= SDHC_FLAG_HOSTCAPS; 118 sc->sc.sc_flags |= SDHC_FLAG_NO_HS_BIT; 119 sc->sc.sc_caps = SDHC_VOLTAGE_SUPP_3_3V | SDHC_HIGH_SPEED_SUPP | 120 (SDHC_MAX_BLK_LEN_1024 << SDHC_MAX_BLK_LEN_SHIFT); 121 122 sc->sc.sc_host = sc->sc_hosts; 123 sc->sc.sc_clkbase = 50000; /* Default to 50MHz */ 124 sc->sc_iot = aaa->aaa_iot; 125 126 prop_dictionary_get_bool(dict, "disable", &disable); 127 if (disable) { 128 aprint_naive(": disabled\n"); 129 aprint_normal(": disabled\n"); 130 return; 131 } 132 133 /* Fetch the EMMC clock frequency from property if set. */ 134 frequency = prop_dictionary_get(dict, "frequency"); 135 if (frequency != NULL) { 136 sc->sc.sc_clkbase = prop_number_integer_value(frequency) / 1000; 137 } 138 139 error = bus_space_map(sc->sc_iot, aaa->aaa_addr, aaa->aaa_size, 0, 140 &sc->sc_ioh); 141 if (error) { 142 aprint_error(": can't map registers for %s: %d\n", 143 aaa->aaa_name, error); 144 return; 145 } 146 sc->sc_iob = aaa->aaa_addr; 147 sc->sc_ios = aaa->aaa_size; 148 149 aprint_naive(": SDHC controller\n"); 150 aprint_normal(": SDHC controller\n"); 151 152 sc->sc_ih = intr_establish(aaa->aaa_intr, IPL_SDMMC, IST_LEVEL, sdhc_intr, 153 &sc->sc); 154 155 if (sc->sc_ih == NULL) { 156 aprint_error_dev(self, "failed to establish interrupt %d\n", 157 aaa->aaa_intr); 158 goto fail; 159 } 160 aprint_normal_dev(self, "interrupting on intr %d\n", aaa->aaa_intr); 161 162 #if NBCMDMAC > 0 163 sc->sc_dmac = bcm_dmac_alloc(BCM_DMAC_TYPE_NORMAL, IPL_SDMMC, 164 bcmemmc_dma_done, sc); 165 if (sc->sc_dmac == NULL) 166 goto done; 167 168 sc->sc.sc_flags |= SDHC_FLAG_USE_DMA; 169 sc->sc.sc_flags |= SDHC_FLAG_EXTERNAL_DMA; 170 sc->sc.sc_caps |= SDHC_DMA_SUPPORT; 171 sc->sc.sc_vendor_transfer_data_dma = bcmemmc_xfer_data_dma; 172 173 sc->sc_state = EMMC_DMA_STATE_IDLE; 174 cv_init(&sc->sc_cv, "bcmemmcdma"); 175 176 int rseg; 177 error = bus_dmamem_alloc(sc->sc.sc_dmat, PAGE_SIZE, PAGE_SIZE, 178 PAGE_SIZE, sc->sc_segs, 1, &rseg, BUS_DMA_WAITOK); 179 if (error) { 180 aprint_error_dev(self, "dmamem_alloc failed (%d)\n", error); 181 goto fail; 182 } 183 184 error = bus_dmamem_map(sc->sc.sc_dmat, sc->sc_segs, rseg, PAGE_SIZE, 185 (void **)&sc->sc_cblk, BUS_DMA_WAITOK); 186 if (error) { 187 aprint_error_dev(self, "dmamem_map failed (%d)\n", error); 188 goto fail; 189 } 190 KASSERT(sc->sc_cblk != NULL); 191 192 memset(sc->sc_cblk, 0, PAGE_SIZE); 193 194 error = bus_dmamap_create(sc->sc.sc_dmat, PAGE_SIZE, 1, PAGE_SIZE, 0, 195 BUS_DMA_WAITOK, &sc->sc_dmamap); 196 if (error) { 197 aprint_error_dev(self, "dmamap_create failed (%d)\n", error); 198 goto fail; 199 } 200 201 error = bus_dmamap_load(sc->sc.sc_dmat, sc->sc_dmamap, sc->sc_cblk, 202 PAGE_SIZE, NULL, BUS_DMA_WAITOK|BUS_DMA_WRITE); 203 if (error) { 204 aprint_error_dev(self, "dmamap_load failed (%d)\n", error); 205 goto fail; 206 } 207 208 done: 209 #endif 210 config_interrupts(self, bcmemmc_attach_i); 211 return; 212 213 fail: 214 /* XXX add bus_dma failure cleanup */ 215 if (sc->sc_ih) { 216 intr_disestablish(sc->sc_ih); 217 sc->sc_ih = NULL; 218 } 219 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios); 220 } 221 222 static void 223 bcmemmc_attach_i(device_t self) 224 { 225 struct bcmemmc_softc * const sc = device_private(self); 226 int error; 227 228 error = sdhc_host_found(&sc->sc, sc->sc_iot, sc->sc_ioh, sc->sc_ios); 229 if (error != 0) { 230 aprint_error_dev(self, "couldn't initialize host, error=%d\n", 231 error); 232 goto fail; 233 } 234 return; 235 236 fail: 237 /* XXX add bus_dma failure cleanup */ 238 if (sc->sc_ih) { 239 intr_disestablish(sc->sc_ih); 240 sc->sc_ih = NULL; 241 } 242 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios); 243 } 244 245 #if NBCMDMAC > 0 246 static int 247 bcmemmc_xfer_data_dma(struct sdhc_softc *sdhc_sc, struct sdmmc_command *cmd) 248 { 249 struct bcmemmc_softc * const sc = device_private(sdhc_sc->sc_dev); 250 kmutex_t *plock = sdhc_host_lock(sc->sc_hosts[0]); 251 size_t seg; 252 int error; 253 254 KASSERT(mutex_owned(plock)); 255 256 for (seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) { 257 sc->sc_cblk[seg].cb_ti = 258 __SHIFTIN(11, DMAC_TI_PERMAP); /* e.MMC */ 259 sc->sc_cblk[seg].cb_txfr_len = 260 cmd->c_dmamap->dm_segs[seg].ds_len; 261 /* 262 * All transfers are assumed to be multiples of 32-bits. 263 */ 264 KASSERTMSG((sc->sc_cblk[seg].cb_txfr_len & 0x3) == 0, 265 "seg %zu len %d", seg, sc->sc_cblk[seg].cb_txfr_len); 266 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 267 sc->sc_cblk[seg].cb_ti |= DMAC_TI_DEST_INC; 268 /* 269 * Use 128-bit mode if transfer is a multiple of 270 * 16-bytes. 271 */ 272 if ((sc->sc_cblk[seg].cb_txfr_len & 0xf) == 0) 273 sc->sc_cblk[seg].cb_ti |= DMAC_TI_DEST_WIDTH; 274 sc->sc_cblk[seg].cb_ti |= DMAC_TI_SRC_DREQ; 275 sc->sc_cblk[seg].cb_source_ad = 276 sc->sc_iob + SDHC_DATA; 277 sc->sc_cblk[seg].cb_dest_ad = 278 cmd->c_dmamap->dm_segs[seg].ds_addr; 279 } else { 280 sc->sc_cblk[seg].cb_ti |= DMAC_TI_SRC_INC; 281 /* 282 * Use 128-bit mode if transfer is a multiple of 283 * 16-bytes. 284 */ 285 if ((sc->sc_cblk[seg].cb_txfr_len & 0xf) == 0) 286 sc->sc_cblk[seg].cb_ti |= DMAC_TI_SRC_WIDTH; 287 sc->sc_cblk[seg].cb_ti |= DMAC_TI_DEST_DREQ; 288 sc->sc_cblk[seg].cb_ti |= DMAC_TI_WAIT_RESP; 289 sc->sc_cblk[seg].cb_source_ad = 290 cmd->c_dmamap->dm_segs[seg].ds_addr; 291 sc->sc_cblk[seg].cb_dest_ad = 292 sc->sc_iob + SDHC_DATA; 293 } 294 sc->sc_cblk[seg].cb_stride = 0; 295 if (seg == cmd->c_dmamap->dm_nsegs - 1) { 296 sc->sc_cblk[seg].cb_ti |= DMAC_TI_INTEN; 297 sc->sc_cblk[seg].cb_nextconbk = 0; 298 } else { 299 sc->sc_cblk[seg].cb_nextconbk = 300 sc->sc_dmamap->dm_segs[0].ds_addr + 301 sizeof(struct bcm_dmac_conblk) * (seg+1); 302 } 303 sc->sc_cblk[seg].cb_padding[0] = 0; 304 sc->sc_cblk[seg].cb_padding[1] = 0; 305 } 306 307 bus_dmamap_sync(sc->sc.sc_dmat, sc->sc_dmamap, 0, 308 sc->sc_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 309 310 error = 0; 311 312 KASSERT(sc->sc_state == EMMC_DMA_STATE_IDLE); 313 sc->sc_state = EMMC_DMA_STATE_BUSY; 314 bcm_dmac_set_conblk_addr(sc->sc_dmac, 315 sc->sc_dmamap->dm_segs[0].ds_addr); 316 error = bcm_dmac_transfer(sc->sc_dmac); 317 if (error) 318 return error; 319 320 while (sc->sc_state == EMMC_DMA_STATE_BUSY) { 321 error = cv_timedwait(&sc->sc_cv, plock, hz * 10); 322 if (error == EWOULDBLOCK) { 323 device_printf(sc->sc.sc_dev, "transfer timeout!\n"); 324 bcm_dmac_halt(sc->sc_dmac); 325 sc->sc_state = EMMC_DMA_STATE_IDLE; 326 error = ETIMEDOUT; 327 break; 328 } 329 } 330 331 bus_dmamap_sync(sc->sc.sc_dmat, sc->sc_dmamap, 0, 332 sc->sc_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 333 334 return error; 335 } 336 337 static void 338 bcmemmc_dma_done(uint32_t status, uint32_t error, void *arg) 339 { 340 struct bcmemmc_softc * const sc = arg; 341 kmutex_t *plock = sdhc_host_lock(sc->sc_hosts[0]); 342 343 if (status != (DMAC_CS_INT|DMAC_CS_END)) 344 device_printf(sc->sc.sc_dev, "status %#x error %#x\n", 345 status,error); 346 347 mutex_enter(plock); 348 KASSERT(sc->sc_state == EMMC_DMA_STATE_BUSY); 349 if (status & DMAC_CS_END) 350 sc->sc_state = EMMC_DMA_STATE_IDLE; 351 cv_broadcast(&sc->sc_cv); 352 mutex_exit(plock); 353 } 354 #endif 355
Indexes created Wed Oct 15 16:09:53 GMT 2025