bcm2835_emmc.c revision 1.13
1 /* $NetBSD: bcm2835_emmc.c,v 1.13 2014/09/12 21:00:11 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Nick Hudson 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: bcm2835_emmc.c,v 1.13 2014/09/12 21:00:11 jmcneill Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/device.h> 38 #include <sys/bus.h> 39 #include <sys/condvar.h> 40 #include <sys/mutex.h> 41 #include <sys/kernel.h> 42 43 #include <arm/broadcom/bcm2835reg.h> 44 #include <arm/broadcom/bcm_amba.h> 45 #include <arm/broadcom/bcm2835_dmac.h> 46 47 #include <dev/sdmmc/sdhcreg.h> 48 #include <dev/sdmmc/sdhcvar.h> 49 #include <dev/sdmmc/sdmmcvar.h> 50 51 enum bcmemmc_dma_state { 52 EMMC_DMA_STATE_IDLE, 53 EMMC_DMA_STATE_BUSY, 54 }; 55 56 struct bcmemmc_softc { 57 struct sdhc_softc sc; 58 59 bus_space_tag_t sc_iot; 60 bus_space_handle_t sc_ioh; 61 bus_size_t sc_ios; 62 struct sdhc_host *sc_hosts[1]; 63 void *sc_ih; 64 65 kmutex_t sc_lock; 66 kcondvar_t sc_cv; 67 68 enum bcmemmc_dma_state sc_state; 69 70 struct bcm_dmac_channel *sc_dmac; 71 72 bus_dmamap_t sc_dmamap; 73 bus_dma_segment_t sc_segs[1]; /* XXX assumes enough descriptors fit in one page */ 74 struct bcm_dmac_conblk *sc_cblk; 75 76 uint32_t sc_physaddr; 77 }; 78 79 static int bcmemmc_match(device_t, struct cfdata *, void *); 80 static void bcmemmc_attach(device_t, device_t, void *); 81 static void bcmemmc_attach_i(device_t); 82 static int bcmemmc_xfer_data_dma(struct sdhc_host *, struct sdmmc_command *); 83 static void bcmemmc_dma_done(void *); 84 85 CFATTACH_DECL_NEW(bcmemmc, sizeof(struct bcmemmc_softc), 86 bcmemmc_match, bcmemmc_attach, NULL, NULL); 87 88 /* ARGSUSED */ 89 static int 90 bcmemmc_match(device_t parent, struct cfdata *match, void *aux) 91 { 92 struct amba_attach_args *aaa = aux; 93 94 if (strcmp(aaa->aaa_name, "emmc") != 0) 95 return 0; 96 97 return 1; 98 } 99 100 /* ARGSUSED */ 101 static void 102 bcmemmc_attach(device_t parent, device_t self, void *aux) 103 { 104 struct bcmemmc_softc *sc = device_private(self); 105 prop_dictionary_t dict = device_properties(self); 106 struct amba_attach_args *aaa = aux; 107 prop_number_t frequency; 108 int error; 109 int rseg; 110 111 sc->sc.sc_dev = self; 112 sc->sc.sc_dmat = aaa->aaa_dmat; 113 sc->sc.sc_flags = 0; 114 sc->sc.sc_flags |= SDHC_FLAG_32BIT_ACCESS; 115 sc->sc.sc_flags |= SDHC_FLAG_HOSTCAPS; 116 sc->sc.sc_flags |= SDHC_FLAG_NO_HS_BIT; 117 sc->sc.sc_caps = SDHC_VOLTAGE_SUPP_3_3V | SDHC_HIGH_SPEED_SUPP | 118 SDHC_MAX_BLK_LEN_1024; 119 sc->sc.sc_flags |= SDHC_FLAG_USE_DMA; 120 sc->sc.sc_flags |= SDHC_FLAG_EXTERNAL_DMA; 121 sc->sc.sc_caps |= SDHC_DMA_SUPPORT; 122 123 sc->sc.sc_host = sc->sc_hosts; 124 sc->sc.sc_clkbase = 50000; /* Default to 50MHz */ 125 sc->sc_iot = aaa->aaa_iot; 126 sc->sc.sc_vendor_transfer_data_dma = bcmemmc_xfer_data_dma; 127 128 /* Fetch the EMMC clock frequency from property if set. */ 129 frequency = prop_dictionary_get(dict, "frequency"); 130 if (frequency != NULL) { 131 sc->sc.sc_clkbase = prop_number_integer_value(frequency) / 1000; 132 } 133 134 error = bus_space_map(sc->sc_iot, aaa->aaa_addr, aaa->aaa_size, 0, 135 &sc->sc_ioh); 136 if (error) { 137 aprint_error_dev(self, 138 "can't map registers for %s: %d\n", aaa->aaa_name, error); 139 return; 140 } 141 sc->sc_ios = aaa->aaa_size; 142 sc->sc_physaddr = aaa->aaa_addr; 143 144 aprint_naive(": SDHC controller\n"); 145 aprint_normal(": SDHC controller\n"); 146 147 sc->sc_ih = bcm2835_intr_establish(aaa->aaa_intr, IPL_SDMMC, sdhc_intr, 148 &sc->sc); 149 150 if (sc->sc_ih == NULL) { 151 aprint_error_dev(self, "failed to establish interrupt %d\n", 152 aaa->aaa_intr); 153 goto fail; 154 } 155 aprint_normal_dev(self, "interrupting on intr %d\n", aaa->aaa_intr); 156 157 sc->sc_dmac = bcm_dmac_alloc(BCM_DMAC_TYPE_NORMAL, IPL_SDMMC, 158 bcmemmc_dma_done, sc); 159 if (sc->sc_dmac == NULL) 160 goto fail; 161 162 sc->sc_state = EMMC_DMA_STATE_IDLE; 163 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SDMMC); 164 cv_init(&sc->sc_cv, "bcmemmcdma"); 165 166 error = bus_dmamem_alloc(sc->sc.sc_dmat, PAGE_SIZE, PAGE_SIZE, 167 PAGE_SIZE, sc->sc_segs, 1, &rseg, BUS_DMA_WAITOK); 168 if (error) { 169 aprint_error_dev(self, "dmamem_alloc failed (%d)\n", error); 170 goto fail; 171 } 172 173 error = bus_dmamem_map(sc->sc.sc_dmat, sc->sc_segs, rseg, PAGE_SIZE, 174 (void **)&sc->sc_cblk, BUS_DMA_WAITOK); 175 if (error) { 176 aprint_error_dev(self, "dmamem_map failed (%d)\n", error); 177 goto fail; 178 } 179 KASSERT(sc->sc_cblk != NULL); 180 181 memset(sc->sc_cblk, 0, PAGE_SIZE); 182 183 error = bus_dmamap_create(sc->sc.sc_dmat, PAGE_SIZE, 1, PAGE_SIZE, 0, 184 BUS_DMA_WAITOK, &sc->sc_dmamap); 185 if (error) { 186 aprint_error_dev(self, "dmamap_create failed (%d)\n", error); 187 goto fail; 188 } 189 190 error = bus_dmamap_load(sc->sc.sc_dmat, sc->sc_dmamap, sc->sc_cblk, 191 PAGE_SIZE, NULL, BUS_DMA_WAITOK|BUS_DMA_WRITE); 192 if (error) { 193 aprint_error_dev(self, "dmamap_load failed (%d)\n", error); 194 goto fail; 195 } 196 197 config_interrupts(self, bcmemmc_attach_i); 198 return; 199 200 fail: 201 /* XXX add bus_dma failure cleanup */ 202 if (sc->sc_ih) { 203 intr_disestablish(sc->sc_ih); 204 sc->sc_ih = NULL; 205 } 206 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios); 207 } 208 209 static void 210 bcmemmc_attach_i(device_t self) 211 { 212 struct bcmemmc_softc * const sc = device_private(self); 213 int error; 214 215 error = sdhc_host_found(&sc->sc, sc->sc_iot, sc->sc_ioh, sc->sc_ios); 216 if (error != 0) { 217 aprint_error_dev(self, "couldn't initialize host, error=%d\n", 218 error); 219 goto fail; 220 } 221 return; 222 223 fail: 224 /* XXX add bus_dma failure cleanup */ 225 if (sc->sc_ih) { 226 intr_disestablish(sc->sc_ih); 227 sc->sc_ih = NULL; 228 } 229 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios); 230 } 231 232 static int 233 bcmemmc_xfer_data_dma(struct sdhc_host *hp, struct sdmmc_command *cmd) 234 { 235 struct bcmemmc_softc * const sc = *(void **)hp; /* XXX XXX XXX */ 236 size_t seg; 237 int error; 238 239 for (seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) { 240 sc->sc_cblk[seg].cb_ti = 241 __SHIFTIN(11, DMAC_TI_PERMAP); /* e.MMC */ 242 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 243 sc->sc_cblk[seg].cb_ti |= DMAC_TI_DEST_INC; 244 sc->sc_cblk[seg].cb_ti |= DMAC_TI_DEST_WIDTH; 245 sc->sc_cblk[seg].cb_ti |= DMAC_TI_SRC_DREQ; 246 sc->sc_cblk[seg].cb_source_ad = 247 BCM2835_PERIPHERALS_TO_BUS(sc->sc_physaddr + 248 SDHC_DATA); 249 sc->sc_cblk[seg].cb_dest_ad = 250 cmd->c_dmamap->dm_segs[seg].ds_addr; 251 } else { 252 sc->sc_cblk[seg].cb_ti |= DMAC_TI_SRC_INC; 253 sc->sc_cblk[seg].cb_ti |= DMAC_TI_SRC_WIDTH; 254 sc->sc_cblk[seg].cb_ti |= DMAC_TI_DEST_DREQ; 255 sc->sc_cblk[seg].cb_source_ad = 256 cmd->c_dmamap->dm_segs[seg].ds_addr; 257 sc->sc_cblk[seg].cb_dest_ad = 258 BCM2835_PERIPHERALS_TO_BUS(sc->sc_physaddr + 259 SDHC_DATA); 260 } 261 sc->sc_cblk[seg].cb_txfr_len = 262 cmd->c_dmamap->dm_segs[seg].ds_len; 263 sc->sc_cblk[seg].cb_stride = 0; 264 if (seg == cmd->c_dmamap->dm_nsegs - 1) { 265 sc->sc_cblk[seg].cb_ti |= DMAC_TI_WAIT_RESP; 266 sc->sc_cblk[seg].cb_ti |= DMAC_TI_INTEN; 267 sc->sc_cblk[seg].cb_nextconbk = 0; 268 } else { 269 sc->sc_cblk[seg].cb_nextconbk = 270 sc->sc_dmamap->dm_segs[0].ds_addr + 271 sizeof(struct bcm_dmac_conblk) * (seg+1); 272 } 273 sc->sc_cblk[seg].cb_padding[0] = 0; 274 sc->sc_cblk[seg].cb_padding[1] = 0; 275 } 276 277 bus_dmamap_sync(sc->sc.sc_dmat, sc->sc_dmamap, 0, 278 sc->sc_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 279 280 error = 0; 281 282 mutex_enter(&sc->sc_lock); 283 KASSERT(sc->sc_state == EMMC_DMA_STATE_IDLE); 284 sc->sc_state = EMMC_DMA_STATE_BUSY; 285 bcm_dmac_set_conblk_addr(sc->sc_dmac, 286 sc->sc_dmamap->dm_segs[0].ds_addr); 287 bcm_dmac_transfer(sc->sc_dmac); 288 while (sc->sc_state == EMMC_DMA_STATE_BUSY) { 289 error = cv_timedwait(&sc->sc_cv, &sc->sc_lock, hz * 10); 290 if (error == EWOULDBLOCK) { 291 device_printf(sc->sc.sc_dev, "transfer timeout!\n"); 292 bcm_dmac_halt(sc->sc_dmac); 293 sc->sc_state = EMMC_DMA_STATE_IDLE; 294 error = ETIMEDOUT; 295 break; 296 } 297 } 298 mutex_exit(&sc->sc_lock); 299 300 bus_dmamap_sync(sc->sc.sc_dmat, sc->sc_dmamap, 0, 301 sc->sc_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 302 303 return error; 304 } 305 306 static void 307 bcmemmc_dma_done(void *arg) 308 { 309 struct bcmemmc_softc * const sc = arg; 310 311 mutex_enter(&sc->sc_lock); 312 KASSERT(sc->sc_state == EMMC_DMA_STATE_BUSY); 313 sc->sc_state = EMMC_DMA_STATE_IDLE; 314 cv_broadcast(&sc->sc_cv); 315 mutex_exit(&sc->sc_lock); 316 317 } 318
Indexes created Tue Sep 30 11:09:46 GMT 2025