bcm2835_emmc.c revision 1.20.2.3
1 /* $NetBSD: bcm2835_emmc.c,v 1.20.2.3 2016/03/19 11:29:55 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Nick Hudson 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: bcm2835_emmc.c,v 1.20.2.3 2016/03/19 11:29:55 skrll Exp $"); 34 35 #include "bcmdmac.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/device.h> 40 #include <sys/bus.h> 41 #include <sys/condvar.h> 42 #include <sys/mutex.h> 43 #include <sys/kernel.h> 44 45 #include <arm/broadcom/bcm2835reg.h> 46 #include <arm/broadcom/bcm_amba.h> 47 #include <arm/broadcom/bcm2835_dmac.h> 48 49 #include <dev/sdmmc/sdhcreg.h> 50 #include <dev/sdmmc/sdhcvar.h> 51 #include <dev/sdmmc/sdmmcvar.h> 52 53 enum bcmemmc_dma_state { 54 EMMC_DMA_STATE_IDLE, 55 EMMC_DMA_STATE_BUSY, 56 }; 57 58 struct bcmemmc_softc { 59 struct sdhc_softc sc; 60 61 bus_space_tag_t sc_iot; 62 bus_space_handle_t sc_ioh; 63 bus_addr_t sc_iob; 64 bus_size_t sc_ios; 65 struct sdhc_host *sc_hosts[1]; 66 void *sc_ih; 67 68 kcondvar_t sc_cv; 69 70 enum bcmemmc_dma_state sc_state; 71 72 struct bcm_dmac_channel *sc_dmac; 73 74 bus_dmamap_t sc_dmamap; 75 bus_dma_segment_t sc_segs[1]; /* XXX assumes enough descriptors fit in one page */ 76 struct bcm_dmac_conblk *sc_cblk; 77 }; 78 79 static int bcmemmc_match(device_t, struct cfdata *, void *); 80 static void bcmemmc_attach(device_t, device_t, void *); 81 static void bcmemmc_attach_i(device_t); 82 #if NBCMDMAC > 0 83 static int bcmemmc_xfer_data_dma(struct sdhc_softc *, struct sdmmc_command *); 84 static void bcmemmc_dma_done(uint32_t, uint32_t, void *); 85 #endif 86 87 CFATTACH_DECL_NEW(bcmemmc, sizeof(struct bcmemmc_softc), 88 bcmemmc_match, bcmemmc_attach, NULL, NULL); 89 90 /* ARGSUSED */ 91 static int 92 bcmemmc_match(device_t parent, struct cfdata *match, void *aux) 93 { 94 struct amba_attach_args *aaa = aux; 95 96 if (strcmp(aaa->aaa_name, "emmc") != 0) 97 return 0; 98 99 return 1; 100 } 101 102 /* ARGSUSED */ 103 static void 104 bcmemmc_attach(device_t parent, device_t self, void *aux) 105 { 106 struct bcmemmc_softc *sc = device_private(self); 107 prop_dictionary_t dict = device_properties(self); 108 struct amba_attach_args *aaa = aux; 109 prop_number_t frequency; 110 int error; 111 112 sc->sc.sc_dev = self; 113 sc->sc.sc_dmat = aaa->aaa_dmat; 114 sc->sc.sc_flags = 0; 115 sc->sc.sc_flags |= SDHC_FLAG_32BIT_ACCESS; 116 sc->sc.sc_flags |= SDHC_FLAG_HOSTCAPS; 117 sc->sc.sc_flags |= SDHC_FLAG_NO_HS_BIT; 118 sc->sc.sc_caps = SDHC_VOLTAGE_SUPP_3_3V | SDHC_HIGH_SPEED_SUPP | 119 (SDHC_MAX_BLK_LEN_1024 << SDHC_MAX_BLK_LEN_SHIFT); 120 sc->sc.sc_caps2 = SDHC_SDR50_SUPP; 121 122 sc->sc.sc_host = sc->sc_hosts; 123 sc->sc.sc_clkbase = 50000; /* Default to 50MHz */ 124 sc->sc_iot = aaa->aaa_iot; 125 126 /* Fetch the EMMC clock frequency from property if set. */ 127 frequency = prop_dictionary_get(dict, "frequency"); 128 if (frequency != NULL) { 129 sc->sc.sc_clkbase = prop_number_integer_value(frequency) / 1000; 130 } 131 132 error = bus_space_map(sc->sc_iot, aaa->aaa_addr, aaa->aaa_size, 0, 133 &sc->sc_ioh); 134 if (error) { 135 aprint_error_dev(self, 136 "can't map registers for %s: %d\n", aaa->aaa_name, error); 137 return; 138 } 139 sc->sc_iob = aaa->aaa_addr; 140 sc->sc_ios = aaa->aaa_size; 141 142 aprint_naive(": SDHC controller\n"); 143 aprint_normal(": SDHC controller\n"); 144 145 sc->sc_ih = intr_establish(aaa->aaa_intr, IPL_SDMMC, IST_LEVEL, sdhc_intr, 146 &sc->sc); 147 148 if (sc->sc_ih == NULL) { 149 aprint_error_dev(self, "failed to establish interrupt %d\n", 150 aaa->aaa_intr); 151 goto fail; 152 } 153 aprint_normal_dev(self, "interrupting on intr %d\n", aaa->aaa_intr); 154 155 #if NBCMDMAC > 0 156 sc->sc_dmac = bcm_dmac_alloc(BCM_DMAC_TYPE_NORMAL, IPL_SDMMC, 157 bcmemmc_dma_done, sc); 158 if (sc->sc_dmac == NULL) 159 goto done; 160 161 sc->sc.sc_flags |= SDHC_FLAG_USE_DMA; 162 sc->sc.sc_flags |= SDHC_FLAG_EXTERNAL_DMA; 163 sc->sc.sc_caps |= SDHC_DMA_SUPPORT; 164 sc->sc.sc_vendor_transfer_data_dma = bcmemmc_xfer_data_dma; 165 166 sc->sc_state = EMMC_DMA_STATE_IDLE; 167 cv_init(&sc->sc_cv, "bcmemmcdma"); 168 169 int rseg; 170 error = bus_dmamem_alloc(sc->sc.sc_dmat, PAGE_SIZE, PAGE_SIZE, 171 PAGE_SIZE, sc->sc_segs, 1, &rseg, BUS_DMA_WAITOK); 172 if (error) { 173 aprint_error_dev(self, "dmamem_alloc failed (%d)\n", error); 174 goto fail; 175 } 176 177 error = bus_dmamem_map(sc->sc.sc_dmat, sc->sc_segs, rseg, PAGE_SIZE, 178 (void **)&sc->sc_cblk, BUS_DMA_WAITOK); 179 if (error) { 180 aprint_error_dev(self, "dmamem_map failed (%d)\n", error); 181 goto fail; 182 } 183 KASSERT(sc->sc_cblk != NULL); 184 185 memset(sc->sc_cblk, 0, PAGE_SIZE); 186 187 error = bus_dmamap_create(sc->sc.sc_dmat, PAGE_SIZE, 1, PAGE_SIZE, 0, 188 BUS_DMA_WAITOK, &sc->sc_dmamap); 189 if (error) { 190 aprint_error_dev(self, "dmamap_create failed (%d)\n", error); 191 goto fail; 192 } 193 194 error = bus_dmamap_load(sc->sc.sc_dmat, sc->sc_dmamap, sc->sc_cblk, 195 PAGE_SIZE, NULL, BUS_DMA_WAITOK|BUS_DMA_WRITE); 196 if (error) { 197 aprint_error_dev(self, "dmamap_load failed (%d)\n", error); 198 goto fail; 199 } 200 201 done: 202 #endif 203 config_interrupts(self, bcmemmc_attach_i); 204 return; 205 206 fail: 207 /* XXX add bus_dma failure cleanup */ 208 if (sc->sc_ih) { 209 intr_disestablish(sc->sc_ih); 210 sc->sc_ih = NULL; 211 } 212 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios); 213 } 214 215 static void 216 bcmemmc_attach_i(device_t self) 217 { 218 struct bcmemmc_softc * const sc = device_private(self); 219 int error; 220 221 error = sdhc_host_found(&sc->sc, sc->sc_iot, sc->sc_ioh, sc->sc_ios); 222 if (error != 0) { 223 aprint_error_dev(self, "couldn't initialize host, error=%d\n", 224 error); 225 goto fail; 226 } 227 return; 228 229 fail: 230 /* XXX add bus_dma failure cleanup */ 231 if (sc->sc_ih) { 232 intr_disestablish(sc->sc_ih); 233 sc->sc_ih = NULL; 234 } 235 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios); 236 } 237 238 #if NBCMDMAC > 0 239 static int 240 bcmemmc_xfer_data_dma(struct sdhc_softc *sdhc_sc, struct sdmmc_command *cmd) 241 { 242 struct bcmemmc_softc * const sc = device_private(sdhc_sc->sc_dev); 243 kmutex_t *plock = sdhc_host_lock(sc->sc_hosts[0]); 244 size_t seg; 245 int error; 246 247 KASSERT(mutex_owned(plock)); 248 249 for (seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) { 250 sc->sc_cblk[seg].cb_ti = 251 __SHIFTIN(11, DMAC_TI_PERMAP); /* e.MMC */ 252 sc->sc_cblk[seg].cb_txfr_len = 253 cmd->c_dmamap->dm_segs[seg].ds_len; 254 /* 255 * All transfers are assumed to be multiples of 32-bits. 256 */ 257 KASSERTMSG((sc->sc_cblk[seg].cb_txfr_len & 0x3) == 0, 258 "seg %zu len %d", seg, sc->sc_cblk[seg].cb_txfr_len); 259 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 260 sc->sc_cblk[seg].cb_ti |= DMAC_TI_DEST_INC; 261 /* 262 * Use 128-bit mode if transfer is a multiple of 263 * 16-bytes. 264 */ 265 if ((sc->sc_cblk[seg].cb_txfr_len & 0xf) == 0) 266 sc->sc_cblk[seg].cb_ti |= DMAC_TI_DEST_WIDTH; 267 sc->sc_cblk[seg].cb_ti |= DMAC_TI_SRC_DREQ; 268 sc->sc_cblk[seg].cb_source_ad = 269 sc->sc_iob + SDHC_DATA; 270 sc->sc_cblk[seg].cb_dest_ad = 271 cmd->c_dmamap->dm_segs[seg].ds_addr; 272 } else { 273 sc->sc_cblk[seg].cb_ti |= DMAC_TI_SRC_INC; 274 /* 275 * Use 128-bit mode if transfer is a multiple of 276 * 16-bytes. 277 */ 278 if ((sc->sc_cblk[seg].cb_txfr_len & 0xf) == 0) 279 sc->sc_cblk[seg].cb_ti |= DMAC_TI_SRC_WIDTH; 280 sc->sc_cblk[seg].cb_ti |= DMAC_TI_DEST_DREQ; 281 sc->sc_cblk[seg].cb_ti |= DMAC_TI_WAIT_RESP; 282 sc->sc_cblk[seg].cb_source_ad = 283 cmd->c_dmamap->dm_segs[seg].ds_addr; 284 sc->sc_cblk[seg].cb_dest_ad = 285 sc->sc_iob + SDHC_DATA; 286 } 287 sc->sc_cblk[seg].cb_stride = 0; 288 if (seg == cmd->c_dmamap->dm_nsegs - 1) { 289 sc->sc_cblk[seg].cb_ti |= DMAC_TI_INTEN; 290 sc->sc_cblk[seg].cb_nextconbk = 0; 291 } else { 292 sc->sc_cblk[seg].cb_nextconbk = 293 sc->sc_dmamap->dm_segs[0].ds_addr + 294 sizeof(struct bcm_dmac_conblk) * (seg+1); 295 } 296 sc->sc_cblk[seg].cb_padding[0] = 0; 297 sc->sc_cblk[seg].cb_padding[1] = 0; 298 } 299 300 bus_dmamap_sync(sc->sc.sc_dmat, sc->sc_dmamap, 0, 301 sc->sc_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 302 303 error = 0; 304 305 KASSERT(sc->sc_state == EMMC_DMA_STATE_IDLE); 306 sc->sc_state = EMMC_DMA_STATE_BUSY; 307 bcm_dmac_set_conblk_addr(sc->sc_dmac, 308 sc->sc_dmamap->dm_segs[0].ds_addr); 309 error = bcm_dmac_transfer(sc->sc_dmac); 310 if (error) 311 return error; 312 313 while (sc->sc_state == EMMC_DMA_STATE_BUSY) { 314 error = cv_timedwait(&sc->sc_cv, plock, hz * 10); 315 if (error == EWOULDBLOCK) { 316 device_printf(sc->sc.sc_dev, "transfer timeout!\n"); 317 bcm_dmac_halt(sc->sc_dmac); 318 sc->sc_state = EMMC_DMA_STATE_IDLE; 319 error = ETIMEDOUT; 320 break; 321 } 322 } 323 324 bus_dmamap_sync(sc->sc.sc_dmat, sc->sc_dmamap, 0, 325 sc->sc_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 326 327 return error; 328 } 329 330 static void 331 bcmemmc_dma_done(uint32_t status, uint32_t error, void *arg) 332 { 333 struct bcmemmc_softc * const sc = arg; 334 kmutex_t *plock = sdhc_host_lock(sc->sc_hosts[0]); 335 336 if (status != (DMAC_CS_INT|DMAC_CS_END)) 337 device_printf(sc->sc.sc_dev, "status %#x error %#x\n", 338 status,error); 339 340 mutex_enter(plock); 341 KASSERT(sc->sc_state == EMMC_DMA_STATE_BUSY); 342 if (status & DMAC_CS_END) 343 sc->sc_state = EMMC_DMA_STATE_IDLE; 344 cv_broadcast(&sc->sc_cv); 345 mutex_exit(plock); 346 } 347 #endif 348
Indexes created Thu Oct 16 14:10:15 GMT 2025