bcm2835_emmc.c revision 1.25
1 /* $NetBSD: bcm2835_emmc.c,v 1.25 2015/08/02 22:09:43 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Nick Hudson 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: bcm2835_emmc.c,v 1.25 2015/08/02 22:09:43 jmcneill Exp $"); 34 35 #include "bcmdmac.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/device.h> 40 #include <sys/bus.h> 41 #include <sys/condvar.h> 42 #include <sys/mutex.h> 43 #include <sys/kernel.h> 44 45 #include <arm/broadcom/bcm2835reg.h> 46 #include <arm/broadcom/bcm_amba.h> 47 #include <arm/broadcom/bcm2835_dmac.h> 48 49 #include <dev/sdmmc/sdhcreg.h> 50 #include <dev/sdmmc/sdhcvar.h> 51 #include <dev/sdmmc/sdmmcvar.h> 52 53 enum bcmemmc_dma_state { 54 EMMC_DMA_STATE_IDLE, 55 EMMC_DMA_STATE_BUSY, 56 }; 57 58 struct bcmemmc_softc { 59 struct sdhc_softc sc; 60 61 bus_space_tag_t sc_iot; 62 bus_space_handle_t sc_ioh; 63 bus_size_t sc_ios; 64 struct sdhc_host *sc_hosts[1]; 65 void *sc_ih; 66 67 kcondvar_t sc_cv; 68 69 enum bcmemmc_dma_state sc_state; 70 71 struct bcm_dmac_channel *sc_dmac; 72 73 bus_dmamap_t sc_dmamap; 74 bus_dma_segment_t sc_segs[1]; /* XXX assumes enough descriptors fit in one page */ 75 struct bcm_dmac_conblk *sc_cblk; 76 77 uint32_t sc_physaddr; 78 }; 79 80 static int bcmemmc_match(device_t, struct cfdata *, void *); 81 static void bcmemmc_attach(device_t, device_t, void *); 82 static void bcmemmc_attach_i(device_t); 83 #if NBCMDMAC > 0 84 static int bcmemmc_xfer_data_dma(struct sdhc_softc *, struct sdmmc_command *); 85 static void bcmemmc_dma_done(void *); 86 #endif 87 88 CFATTACH_DECL_NEW(bcmemmc, sizeof(struct bcmemmc_softc), 89 bcmemmc_match, bcmemmc_attach, NULL, NULL); 90 91 /* ARGSUSED */ 92 static int 93 bcmemmc_match(device_t parent, struct cfdata *match, void *aux) 94 { 95 struct amba_attach_args *aaa = aux; 96 97 if (strcmp(aaa->aaa_name, "emmc") != 0) 98 return 0; 99 100 return 1; 101 } 102 103 /* ARGSUSED */ 104 static void 105 bcmemmc_attach(device_t parent, device_t self, void *aux) 106 { 107 struct bcmemmc_softc *sc = device_private(self); 108 prop_dictionary_t dict = device_properties(self); 109 struct amba_attach_args *aaa = aux; 110 prop_number_t frequency; 111 int error; 112 113 sc->sc.sc_dev = self; 114 sc->sc.sc_dmat = aaa->aaa_dmat; 115 sc->sc.sc_flags = 0; 116 sc->sc.sc_flags |= SDHC_FLAG_32BIT_ACCESS; 117 sc->sc.sc_flags |= SDHC_FLAG_HOSTCAPS; 118 sc->sc.sc_flags |= SDHC_FLAG_NO_HS_BIT; 119 sc->sc.sc_caps = SDHC_VOLTAGE_SUPP_3_3V | SDHC_VOLTAGE_SUPP_1_8V | 120 SDHC_HIGH_SPEED_SUPP | 121 (SDHC_MAX_BLK_LEN_1024 << SDHC_MAX_BLK_LEN_SHIFT); 122 sc->sc.sc_caps2 = SDHC_SDR50_SUPP | SDHC_SDR104_SUPP | SDHC_DDR50_SUPP; 123 124 sc->sc.sc_host = sc->sc_hosts; 125 sc->sc.sc_clkbase = 50000; /* Default to 50MHz */ 126 sc->sc_iot = aaa->aaa_iot; 127 128 /* Fetch the EMMC clock frequency from property if set. */ 129 frequency = prop_dictionary_get(dict, "frequency"); 130 if (frequency != NULL) { 131 sc->sc.sc_clkbase = prop_number_integer_value(frequency) / 1000; 132 } 133 134 error = bus_space_map(sc->sc_iot, aaa->aaa_addr, aaa->aaa_size, 0, 135 &sc->sc_ioh); 136 if (error) { 137 aprint_error_dev(self, 138 "can't map registers for %s: %d\n", aaa->aaa_name, error); 139 return; 140 } 141 sc->sc_ios = aaa->aaa_size; 142 sc->sc_physaddr = aaa->aaa_addr; 143 144 aprint_naive(": SDHC controller\n"); 145 aprint_normal(": SDHC controller\n"); 146 147 sc->sc_ih = intr_establish(aaa->aaa_intr, IPL_SDMMC, IST_LEVEL, sdhc_intr, 148 &sc->sc); 149 150 if (sc->sc_ih == NULL) { 151 aprint_error_dev(self, "failed to establish interrupt %d\n", 152 aaa->aaa_intr); 153 goto fail; 154 } 155 aprint_normal_dev(self, "interrupting on intr %d\n", aaa->aaa_intr); 156 157 #if NBCMDMAC > 0 158 sc->sc_dmac = bcm_dmac_alloc(BCM_DMAC_TYPE_NORMAL, IPL_SDMMC, 159 bcmemmc_dma_done, sc); 160 if (sc->sc_dmac == NULL) 161 goto done; 162 163 sc->sc.sc_flags |= SDHC_FLAG_USE_DMA; 164 sc->sc.sc_flags |= SDHC_FLAG_EXTERNAL_DMA; 165 sc->sc.sc_caps |= SDHC_DMA_SUPPORT; 166 sc->sc.sc_vendor_transfer_data_dma = bcmemmc_xfer_data_dma; 167 168 sc->sc_state = EMMC_DMA_STATE_IDLE; 169 cv_init(&sc->sc_cv, "bcmemmcdma"); 170 171 int rseg; 172 error = bus_dmamem_alloc(sc->sc.sc_dmat, PAGE_SIZE, PAGE_SIZE, 173 PAGE_SIZE, sc->sc_segs, 1, &rseg, BUS_DMA_WAITOK); 174 if (error) { 175 aprint_error_dev(self, "dmamem_alloc failed (%d)\n", error); 176 goto fail; 177 } 178 179 error = bus_dmamem_map(sc->sc.sc_dmat, sc->sc_segs, rseg, PAGE_SIZE, 180 (void **)&sc->sc_cblk, BUS_DMA_WAITOK); 181 if (error) { 182 aprint_error_dev(self, "dmamem_map failed (%d)\n", error); 183 goto fail; 184 } 185 KASSERT(sc->sc_cblk != NULL); 186 187 memset(sc->sc_cblk, 0, PAGE_SIZE); 188 189 error = bus_dmamap_create(sc->sc.sc_dmat, PAGE_SIZE, 1, PAGE_SIZE, 0, 190 BUS_DMA_WAITOK, &sc->sc_dmamap); 191 if (error) { 192 aprint_error_dev(self, "dmamap_create failed (%d)\n", error); 193 goto fail; 194 } 195 196 error = bus_dmamap_load(sc->sc.sc_dmat, sc->sc_dmamap, sc->sc_cblk, 197 PAGE_SIZE, NULL, BUS_DMA_WAITOK|BUS_DMA_WRITE); 198 if (error) { 199 aprint_error_dev(self, "dmamap_load failed (%d)\n", error); 200 goto fail; 201 } 202 203 done: 204 #endif 205 config_interrupts(self, bcmemmc_attach_i); 206 return; 207 208 fail: 209 /* XXX add bus_dma failure cleanup */ 210 if (sc->sc_ih) { 211 intr_disestablish(sc->sc_ih); 212 sc->sc_ih = NULL; 213 } 214 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios); 215 } 216 217 static void 218 bcmemmc_attach_i(device_t self) 219 { 220 struct bcmemmc_softc * const sc = device_private(self); 221 int error; 222 223 error = sdhc_host_found(&sc->sc, sc->sc_iot, sc->sc_ioh, sc->sc_ios); 224 if (error != 0) { 225 aprint_error_dev(self, "couldn't initialize host, error=%d\n", 226 error); 227 goto fail; 228 } 229 return; 230 231 fail: 232 /* XXX add bus_dma failure cleanup */ 233 if (sc->sc_ih) { 234 intr_disestablish(sc->sc_ih); 235 sc->sc_ih = NULL; 236 } 237 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios); 238 } 239 240 #if NBCMDMAC > 0 241 static int 242 bcmemmc_xfer_data_dma(struct sdhc_softc *sdhc_sc, struct sdmmc_command *cmd) 243 { 244 struct bcmemmc_softc * const sc = device_private(sdhc_sc->sc_dev); 245 kmutex_t *plock = sdhc_host_lock(sc->sc_hosts[0]); 246 size_t seg; 247 int error; 248 249 KASSERT(mutex_owned(plock)); 250 251 for (seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) { 252 sc->sc_cblk[seg].cb_ti = 253 __SHIFTIN(11, DMAC_TI_PERMAP); /* e.MMC */ 254 sc->sc_cblk[seg].cb_txfr_len = 255 cmd->c_dmamap->dm_segs[seg].ds_len; 256 /* 257 * All transfers are assumed to be multiples of 32-bits. 258 */ 259 KASSERTMSG((sc->sc_cblk[seg].cb_txfr_len & 0x3) == 0, 260 "seg %zu len %d", seg, sc->sc_cblk[seg].cb_txfr_len); 261 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 262 sc->sc_cblk[seg].cb_ti |= DMAC_TI_DEST_INC; 263 /* 264 * Use 128-bit mode if transfer is a multiple of 265 * 16-bytes. 266 */ 267 if ((sc->sc_cblk[seg].cb_txfr_len & 0xf) == 0) 268 sc->sc_cblk[seg].cb_ti |= DMAC_TI_DEST_WIDTH; 269 sc->sc_cblk[seg].cb_ti |= DMAC_TI_SRC_DREQ; 270 sc->sc_cblk[seg].cb_source_ad = 271 BCM2835_PERIPHERALS_TO_BUS(sc->sc_physaddr + 272 SDHC_DATA); 273 sc->sc_cblk[seg].cb_dest_ad = 274 cmd->c_dmamap->dm_segs[seg].ds_addr; 275 } else { 276 sc->sc_cblk[seg].cb_ti |= DMAC_TI_SRC_INC; 277 /* 278 * Use 128-bit mode if transfer is a multiple of 279 * 16-bytes. 280 */ 281 if ((sc->sc_cblk[seg].cb_txfr_len & 0xf) == 0) 282 sc->sc_cblk[seg].cb_ti |= DMAC_TI_SRC_WIDTH; 283 sc->sc_cblk[seg].cb_ti |= DMAC_TI_DEST_DREQ; 284 sc->sc_cblk[seg].cb_ti |= DMAC_TI_WAIT_RESP; 285 sc->sc_cblk[seg].cb_source_ad = 286 cmd->c_dmamap->dm_segs[seg].ds_addr; 287 sc->sc_cblk[seg].cb_dest_ad = 288 BCM2835_PERIPHERALS_TO_BUS(sc->sc_physaddr + 289 SDHC_DATA); 290 } 291 sc->sc_cblk[seg].cb_stride = 0; 292 if (seg == cmd->c_dmamap->dm_nsegs - 1) { 293 sc->sc_cblk[seg].cb_ti |= DMAC_TI_INTEN; 294 sc->sc_cblk[seg].cb_nextconbk = 0; 295 } else { 296 sc->sc_cblk[seg].cb_nextconbk = 297 sc->sc_dmamap->dm_segs[0].ds_addr + 298 sizeof(struct bcm_dmac_conblk) * (seg+1); 299 } 300 sc->sc_cblk[seg].cb_padding[0] = 0; 301 sc->sc_cblk[seg].cb_padding[1] = 0; 302 } 303 304 bus_dmamap_sync(sc->sc.sc_dmat, sc->sc_dmamap, 0, 305 sc->sc_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 306 307 error = 0; 308 309 KASSERT(sc->sc_state == EMMC_DMA_STATE_IDLE); 310 sc->sc_state = EMMC_DMA_STATE_BUSY; 311 bcm_dmac_set_conblk_addr(sc->sc_dmac, 312 sc->sc_dmamap->dm_segs[0].ds_addr); 313 bcm_dmac_transfer(sc->sc_dmac); 314 while (sc->sc_state == EMMC_DMA_STATE_BUSY) { 315 error = cv_timedwait(&sc->sc_cv, plock, hz * 10); 316 if (error == EWOULDBLOCK) { 317 device_printf(sc->sc.sc_dev, "transfer timeout!\n"); 318 bcm_dmac_halt(sc->sc_dmac); 319 sc->sc_state = EMMC_DMA_STATE_IDLE; 320 error = ETIMEDOUT; 321 break; 322 } 323 } 324 325 bus_dmamap_sync(sc->sc.sc_dmat, sc->sc_dmamap, 0, 326 sc->sc_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 327 328 return error; 329 } 330 331 static void 332 bcmemmc_dma_done(void *arg) 333 { 334 struct bcmemmc_softc * const sc = arg; 335 kmutex_t *plock = sdhc_host_lock(sc->sc_hosts[0]); 336 337 mutex_enter(plock); 338 KASSERT(sc->sc_state == EMMC_DMA_STATE_BUSY); 339 sc->sc_state = EMMC_DMA_STATE_IDLE; 340 cv_broadcast(&sc->sc_cv); 341 mutex_exit(plock); 342 } 343 #endif 344
Indexes created Wed Oct 15 07:09:58 GMT 2025