bcm2835_emmc.c revision 1.33
1 /* $NetBSD: bcm2835_emmc.c,v 1.33 2018/08/19 09:18:48 rin Exp $ */ 2 3 /*- 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Nick Hudson 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: bcm2835_emmc.c,v 1.33 2018/08/19 09:18:48 rin Exp $"); 34 35 #include "bcmdmac.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/device.h> 40 #include <sys/bus.h> 41 #include <sys/condvar.h> 42 #include <sys/mutex.h> 43 #include <sys/kernel.h> 44 45 #include <arm/broadcom/bcm2835reg.h> 46 #include <arm/broadcom/bcm2835_dmac.h> 47 48 #include <dev/sdmmc/sdhcreg.h> 49 #include <dev/sdmmc/sdhcvar.h> 50 #include <dev/sdmmc/sdmmcvar.h> 51 52 #include <dev/fdt/fdtvar.h> 53 54 #include <arm/fdt/arm_fdtvar.h> 55 56 enum bcmemmc_dma_state { 57 EMMC_DMA_STATE_IDLE, 58 EMMC_DMA_STATE_BUSY, 59 }; 60 61 struct bcmemmc_softc { 62 struct sdhc_softc sc; 63 64 bus_space_tag_t sc_iot; 65 bus_space_handle_t sc_ioh; 66 bus_addr_t sc_iob; 67 bus_size_t sc_ios; 68 struct sdhc_host *sc_hosts[1]; 69 void *sc_ih; 70 int sc_phandle; 71 72 kcondvar_t sc_cv; 73 74 enum bcmemmc_dma_state sc_state; 75 76 struct bcm_dmac_channel *sc_dmac; 77 78 bus_dmamap_t sc_dmamap; 79 bus_dma_segment_t sc_segs[1]; /* XXX assumes enough descriptors fit in one page */ 80 struct bcm_dmac_conblk *sc_cblk; 81 }; 82 83 static int bcmemmc_match(device_t, struct cfdata *, void *); 84 static void bcmemmc_attach(device_t, device_t, void *); 85 static void bcmemmc_attach_i(device_t); 86 #if NBCMDMAC > 0 87 static int bcmemmc_xfer_data_dma(struct sdhc_softc *, struct sdmmc_command *); 88 static void bcmemmc_dma_done(uint32_t, uint32_t, void *); 89 #endif 90 91 CFATTACH_DECL_NEW(bcmemmc, sizeof(struct bcmemmc_softc), 92 bcmemmc_match, bcmemmc_attach, NULL, NULL); 93 94 /* ARGSUSED */ 95 static int 96 bcmemmc_match(device_t parent, struct cfdata *match, void *aux) 97 { 98 const char * const compatible[] = { 99 "brcm,bcm2835-sdhci", 100 NULL 101 }; 102 struct fdt_attach_args * const faa = aux; 103 104 return of_match_compatible(faa->faa_phandle, compatible); 105 } 106 107 /* ARGSUSED */ 108 static void 109 bcmemmc_attach(device_t parent, device_t self, void *aux) 110 { 111 struct bcmemmc_softc *sc = device_private(self); 112 struct fdt_attach_args * const faa = aux; 113 prop_dictionary_t dict = device_properties(self); 114 bool disable = false; 115 int error; 116 117 sc->sc.sc_dev = self; 118 sc->sc.sc_dmat = faa->faa_dmat; 119 sc->sc.sc_flags = 0; 120 sc->sc.sc_flags |= SDHC_FLAG_32BIT_ACCESS; 121 sc->sc.sc_flags |= SDHC_FLAG_HOSTCAPS; 122 sc->sc.sc_flags |= SDHC_FLAG_NO_HS_BIT; 123 sc->sc.sc_caps = SDHC_VOLTAGE_SUPP_3_3V | SDHC_HIGH_SPEED_SUPP | 124 (SDHC_MAX_BLK_LEN_1024 << SDHC_MAX_BLK_LEN_SHIFT); 125 126 sc->sc.sc_host = sc->sc_hosts; 127 sc->sc.sc_clkbase = 50000; /* Default to 50MHz */ 128 sc->sc_iot = faa->faa_bst; 129 130 prop_dictionary_get_bool(dict, "disable", &disable); 131 if (disable) { 132 aprint_naive(": disabled\n"); 133 aprint_normal(": disabled\n"); 134 return; 135 } 136 137 bus_addr_t addr; 138 bus_size_t size; 139 140 const int phandle = faa->faa_phandle; 141 error = fdtbus_get_reg(phandle, 0, &addr, &size); 142 if (error) { 143 aprint_error_dev(sc->sc.sc_dev, "unable to map device\n"); 144 return; 145 } 146 sc->sc_phandle = phandle; 147 148 /* Enable clocks */ 149 struct clk *clk; 150 for (int i = 0; (clk = fdtbus_clock_get_index(phandle, i)); i++) { 151 if (clk_enable(clk) != 0) { 152 aprint_error(": failed to enable clock #%d\n", i); 153 return; 154 } 155 if (i == 0) 156 sc->sc.sc_clkbase = clk_get_rate(clk) / 1000; 157 } 158 aprint_debug_dev(self, "ref freq %u kHz\n", sc->sc.sc_clkbase); 159 160 error = bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh); 161 if (error) { 162 aprint_error_dev(sc->sc.sc_dev, "unable to map device\n"); 163 return; 164 } 165 sc->sc_iob = addr; 166 sc->sc_ios = size; 167 168 aprint_naive(": SDHC controller\n"); 169 aprint_normal(": SDHC controller\n"); 170 171 char intrstr[128]; 172 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 173 aprint_error(": failed to decode interrupt\n"); 174 return; 175 } 176 177 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_SDMMC, 0, 178 sdhc_intr, &sc->sc); 179 180 if (sc->sc_ih == NULL) { 181 aprint_error_dev(self, "failed to establish interrupt %s\n", 182 intrstr); 183 goto fail; 184 } 185 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 186 187 #if NBCMDMAC > 0 188 sc->sc_dmac = bcm_dmac_alloc(BCM_DMAC_TYPE_NORMAL, IPL_SDMMC, 189 bcmemmc_dma_done, sc); 190 if (sc->sc_dmac == NULL) 191 goto done; 192 193 sc->sc.sc_flags |= SDHC_FLAG_USE_DMA; 194 sc->sc.sc_flags |= SDHC_FLAG_EXTERNAL_DMA; 195 sc->sc.sc_caps |= SDHC_DMA_SUPPORT; 196 sc->sc.sc_vendor_transfer_data_dma = bcmemmc_xfer_data_dma; 197 198 sc->sc_state = EMMC_DMA_STATE_IDLE; 199 cv_init(&sc->sc_cv, "bcmemmcdma"); 200 201 int rseg; 202 error = bus_dmamem_alloc(sc->sc.sc_dmat, PAGE_SIZE, PAGE_SIZE, 203 PAGE_SIZE, sc->sc_segs, 1, &rseg, BUS_DMA_WAITOK); 204 if (error) { 205 aprint_error_dev(self, "dmamem_alloc failed (%d)\n", error); 206 goto fail; 207 } 208 209 error = bus_dmamem_map(sc->sc.sc_dmat, sc->sc_segs, rseg, PAGE_SIZE, 210 (void **)&sc->sc_cblk, BUS_DMA_WAITOK); 211 if (error) { 212 aprint_error_dev(self, "dmamem_map failed (%d)\n", error); 213 goto fail; 214 } 215 KASSERT(sc->sc_cblk != NULL); 216 217 memset(sc->sc_cblk, 0, PAGE_SIZE); 218 219 error = bus_dmamap_create(sc->sc.sc_dmat, PAGE_SIZE, 1, PAGE_SIZE, 0, 220 BUS_DMA_WAITOK, &sc->sc_dmamap); 221 if (error) { 222 aprint_error_dev(self, "dmamap_create failed (%d)\n", error); 223 goto fail; 224 } 225 226 error = bus_dmamap_load(sc->sc.sc_dmat, sc->sc_dmamap, sc->sc_cblk, 227 PAGE_SIZE, NULL, BUS_DMA_WAITOK|BUS_DMA_WRITE); 228 if (error) { 229 aprint_error_dev(self, "dmamap_load failed (%d)\n", error); 230 goto fail; 231 } 232 233 done: 234 #endif 235 config_interrupts(self, bcmemmc_attach_i); 236 return; 237 238 fail: 239 /* XXX add bus_dma failure cleanup */ 240 if (sc->sc_ih) { 241 fdtbus_intr_disestablish(sc->sc_phandle, sc->sc_ih); 242 sc->sc_ih = NULL; 243 } 244 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios); 245 } 246 247 static void 248 bcmemmc_attach_i(device_t self) 249 { 250 struct bcmemmc_softc * const sc = device_private(self); 251 int error; 252 253 error = sdhc_host_found(&sc->sc, sc->sc_iot, sc->sc_ioh, sc->sc_ios); 254 if (error != 0) { 255 aprint_error_dev(self, "couldn't initialize host, error=%d\n", 256 error); 257 goto fail; 258 } 259 return; 260 261 fail: 262 /* XXX add bus_dma failure cleanup */ 263 if (sc->sc_ih) { 264 fdtbus_intr_disestablish(sc->sc_phandle, sc->sc_ih); 265 sc->sc_ih = NULL; 266 } 267 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios); 268 } 269 270 #if NBCMDMAC > 0 271 static int 272 bcmemmc_xfer_data_dma(struct sdhc_softc *sdhc_sc, struct sdmmc_command *cmd) 273 { 274 struct bcmemmc_softc * const sc = device_private(sdhc_sc->sc_dev); 275 kmutex_t *plock = sdhc_host_lock(sc->sc_hosts[0]); 276 const bus_addr_t ad_sdhcdata = sc->sc_iob + SDHC_DATA; 277 size_t seg; 278 int error; 279 280 KASSERT(mutex_owned(plock)); 281 282 for (seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) { 283 sc->sc_cblk[seg].cb_ti = 284 __SHIFTIN(11, DMAC_TI_PERMAP); /* e.MMC */ 285 sc->sc_cblk[seg].cb_txfr_len = 286 cmd->c_dmamap->dm_segs[seg].ds_len; 287 /* 288 * All transfers are assumed to be multiples of 32-bits. 289 */ 290 KASSERTMSG((sc->sc_cblk[seg].cb_txfr_len & 0x3) == 0, 291 "seg %zu len %d", seg, sc->sc_cblk[seg].cb_txfr_len); 292 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 293 sc->sc_cblk[seg].cb_ti |= DMAC_TI_DEST_INC; 294 /* 295 * Use 128-bit mode if transfer is a multiple of 296 * 16-bytes. 297 */ 298 if ((sc->sc_cblk[seg].cb_txfr_len & 0xf) == 0) 299 sc->sc_cblk[seg].cb_ti |= DMAC_TI_DEST_WIDTH; 300 sc->sc_cblk[seg].cb_ti |= DMAC_TI_SRC_DREQ; 301 sc->sc_cblk[seg].cb_source_ad = ad_sdhcdata; 302 sc->sc_cblk[seg].cb_dest_ad = 303 cmd->c_dmamap->dm_segs[seg].ds_addr; 304 } else { 305 sc->sc_cblk[seg].cb_ti |= DMAC_TI_SRC_INC; 306 /* 307 * Use 128-bit mode if transfer is a multiple of 308 * 16-bytes. 309 */ 310 if ((sc->sc_cblk[seg].cb_txfr_len & 0xf) == 0) 311 sc->sc_cblk[seg].cb_ti |= DMAC_TI_SRC_WIDTH; 312 sc->sc_cblk[seg].cb_ti |= DMAC_TI_DEST_DREQ; 313 sc->sc_cblk[seg].cb_ti |= DMAC_TI_WAIT_RESP; 314 sc->sc_cblk[seg].cb_source_ad = 315 cmd->c_dmamap->dm_segs[seg].ds_addr; 316 sc->sc_cblk[seg].cb_dest_ad = ad_sdhcdata; 317 } 318 sc->sc_cblk[seg].cb_stride = 0; 319 if (seg == cmd->c_dmamap->dm_nsegs - 1) { 320 sc->sc_cblk[seg].cb_ti |= DMAC_TI_INTEN; 321 sc->sc_cblk[seg].cb_nextconbk = 0; 322 } else { 323 sc->sc_cblk[seg].cb_nextconbk = 324 sc->sc_dmamap->dm_segs[0].ds_addr + 325 sizeof(struct bcm_dmac_conblk) * (seg+1); 326 } 327 sc->sc_cblk[seg].cb_padding[0] = 0; 328 sc->sc_cblk[seg].cb_padding[1] = 0; 329 } 330 331 bus_dmamap_sync(sc->sc.sc_dmat, sc->sc_dmamap, 0, 332 sc->sc_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 333 334 error = 0; 335 336 KASSERT(sc->sc_state == EMMC_DMA_STATE_IDLE); 337 sc->sc_state = EMMC_DMA_STATE_BUSY; 338 bcm_dmac_set_conblk_addr(sc->sc_dmac, 339 sc->sc_dmamap->dm_segs[0].ds_addr); 340 error = bcm_dmac_transfer(sc->sc_dmac); 341 if (error) 342 return error; 343 344 while (sc->sc_state == EMMC_DMA_STATE_BUSY) { 345 error = cv_timedwait(&sc->sc_cv, plock, hz * 10); 346 if (error == EWOULDBLOCK) { 347 device_printf(sc->sc.sc_dev, "transfer timeout!\n"); 348 bcm_dmac_halt(sc->sc_dmac); 349 sc->sc_state = EMMC_DMA_STATE_IDLE; 350 error = ETIMEDOUT; 351 break; 352 } 353 } 354 355 bus_dmamap_sync(sc->sc.sc_dmat, sc->sc_dmamap, 0, 356 sc->sc_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 357 358 return error; 359 } 360 361 static void 362 bcmemmc_dma_done(uint32_t status, uint32_t error, void *arg) 363 { 364 struct bcmemmc_softc * const sc = arg; 365 kmutex_t *plock = sdhc_host_lock(sc->sc_hosts[0]); 366 367 if (status != (DMAC_CS_INT|DMAC_CS_END)) 368 device_printf(sc->sc.sc_dev, "status %#x error %#x\n", 369 status,error); 370 371 mutex_enter(plock); 372 KASSERT(sc->sc_state == EMMC_DMA_STATE_BUSY); 373 if (status & DMAC_CS_END) 374 sc->sc_state = EMMC_DMA_STATE_IDLE; 375 cv_broadcast(&sc->sc_cv); 376 mutex_exit(plock); 377 } 378 #endif 379
Indexes created Thu Oct 02 01:09:59 GMT 2025