bcm2835_emmc.c revision 1.36
1 /* $NetBSD: bcm2835_emmc.c,v 1.36 2020/02/20 01:44:06 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Nick Hudson 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: bcm2835_emmc.c,v 1.36 2020/02/20 01:44:06 jmcneill Exp $"); 34 35 #include "bcmdmac.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/device.h> 40 #include <sys/bus.h> 41 #include <sys/condvar.h> 42 #include <sys/mutex.h> 43 #include <sys/kernel.h> 44 45 #include <arm/broadcom/bcm2835reg.h> 46 #include <arm/broadcom/bcm2835_dmac.h> 47 48 #include <dev/sdmmc/sdhcreg.h> 49 #include <dev/sdmmc/sdhcvar.h> 50 #include <dev/sdmmc/sdmmcvar.h> 51 52 #include <dev/fdt/fdtvar.h> 53 54 #include <arm/fdt/arm_fdtvar.h> 55 56 enum bcmemmc_dma_state { 57 EMMC_DMA_STATE_IDLE, 58 EMMC_DMA_STATE_BUSY, 59 }; 60 61 struct bcmemmc_softc { 62 struct sdhc_softc sc; 63 64 bus_space_tag_t sc_iot; 65 bus_space_handle_t sc_ioh; 66 bus_addr_t sc_iob; 67 bus_size_t sc_ios; 68 struct sdhc_host *sc_hosts[1]; 69 void *sc_ih; 70 int sc_phandle; 71 72 kcondvar_t sc_cv; 73 74 enum bcmemmc_dma_state sc_state; 75 76 struct bcm_dmac_channel *sc_dmac; 77 78 bus_dmamap_t sc_dmamap; 79 bus_dma_segment_t sc_segs[1]; /* XXX assumes enough descriptors fit in one page */ 80 struct bcm_dmac_conblk *sc_cblk; 81 }; 82 83 static int bcmemmc_match(device_t, struct cfdata *, void *); 84 static void bcmemmc_attach(device_t, device_t, void *); 85 static void bcmemmc_attach_i(device_t); 86 #if NBCMDMAC > 0 87 static int bcmemmc_xfer_data_dma(struct sdhc_softc *, struct sdmmc_command *); 88 static void bcmemmc_dma_done(uint32_t, uint32_t, void *); 89 #endif 90 91 CFATTACH_DECL_NEW(bcmemmc, sizeof(struct bcmemmc_softc), 92 bcmemmc_match, bcmemmc_attach, NULL, NULL); 93 94 enum bcmemmc_type { 95 BCM2835_SDHCI, 96 BCM2711_EMMC2, 97 }; 98 99 static const struct of_compat_data compat_data[] = { 100 { "brcm,bcm2835-sdhci", BCM2835_SDHCI }, 101 { "brcm,bcm2711-emmc2", BCM2711_EMMC2 }, 102 { NULL } 103 }; 104 105 /* ARGSUSED */ 106 static int 107 bcmemmc_match(device_t parent, struct cfdata *match, void *aux) 108 { 109 struct fdt_attach_args * const faa = aux; 110 111 return of_match_compat_data(faa->faa_phandle, compat_data); 112 } 113 114 /* ARGSUSED */ 115 static void 116 bcmemmc_attach(device_t parent, device_t self, void *aux) 117 { 118 struct bcmemmc_softc *sc = device_private(self); 119 struct fdt_attach_args * const faa = aux; 120 prop_dictionary_t dict = device_properties(self); 121 const int phandle = faa->faa_phandle; 122 bool disable = false; 123 enum bcmemmc_type type; 124 int error; 125 126 type = of_search_compatible(phandle, compat_data)->data; 127 128 sc->sc.sc_dev = self; 129 sc->sc.sc_dmat = faa->faa_dmat; 130 sc->sc.sc_flags = 0; 131 sc->sc.sc_flags |= SDHC_FLAG_32BIT_ACCESS; 132 sc->sc.sc_flags |= SDHC_FLAG_HOSTCAPS; 133 sc->sc.sc_flags |= SDHC_FLAG_NO_HS_BIT; 134 sc->sc.sc_caps = SDHC_VOLTAGE_SUPP_3_3V | SDHC_HIGH_SPEED_SUPP | 135 (SDHC_MAX_BLK_LEN_1024 << SDHC_MAX_BLK_LEN_SHIFT); 136 137 sc->sc.sc_host = sc->sc_hosts; 138 sc->sc.sc_clkbase = 50000; /* Default to 50MHz */ 139 sc->sc_iot = faa->faa_bst; 140 141 prop_dictionary_get_bool(dict, "disable", &disable); 142 if (disable) { 143 aprint_naive(": disabled\n"); 144 aprint_normal(": disabled\n"); 145 return; 146 } 147 148 bus_addr_t addr; 149 bus_size_t size; 150 151 error = fdtbus_get_reg(phandle, 0, &addr, &size); 152 if (error) { 153 aprint_error_dev(sc->sc.sc_dev, "unable to map device\n"); 154 return; 155 } 156 sc->sc_phandle = phandle; 157 158 /* Enable clocks */ 159 struct clk *clk; 160 for (int i = 0; (clk = fdtbus_clock_get_index(phandle, i)); i++) { 161 if (clk_enable(clk) != 0) { 162 aprint_error(": failed to enable clock #%d\n", i); 163 return; 164 } 165 if (i == 0) 166 sc->sc.sc_clkbase = clk_get_rate(clk) / 1000; 167 } 168 aprint_debug_dev(self, "ref freq %u kHz\n", sc->sc.sc_clkbase); 169 170 error = bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh); 171 if (error) { 172 aprint_error_dev(sc->sc.sc_dev, "unable to map device\n"); 173 return; 174 } 175 sc->sc_iob = addr; 176 sc->sc_ios = size; 177 178 aprint_naive(": SDHC controller\n"); 179 aprint_normal(": SDHC controller\n"); 180 181 char intrstr[128]; 182 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 183 aprint_error(": failed to decode interrupt\n"); 184 return; 185 } 186 187 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_SDMMC, 0, 188 sdhc_intr, &sc->sc); 189 190 if (sc->sc_ih == NULL) { 191 aprint_error_dev(self, "failed to establish interrupt %s\n", 192 intrstr); 193 goto fail; 194 } 195 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 196 197 #if NBCMDMAC > 0 198 if (type != BCM2835_SDHCI) 199 goto done; 200 201 sc->sc_dmac = bcm_dmac_alloc(BCM_DMAC_TYPE_NORMAL, IPL_SDMMC, 202 bcmemmc_dma_done, sc); 203 if (sc->sc_dmac == NULL) 204 goto done; 205 206 sc->sc.sc_flags |= SDHC_FLAG_USE_DMA; 207 sc->sc.sc_flags |= SDHC_FLAG_EXTERNAL_DMA; 208 sc->sc.sc_caps |= SDHC_DMA_SUPPORT; 209 sc->sc.sc_vendor_transfer_data_dma = bcmemmc_xfer_data_dma; 210 211 sc->sc_state = EMMC_DMA_STATE_IDLE; 212 cv_init(&sc->sc_cv, "bcmemmcdma"); 213 214 int rseg; 215 error = bus_dmamem_alloc(sc->sc.sc_dmat, PAGE_SIZE, PAGE_SIZE, 216 PAGE_SIZE, sc->sc_segs, 1, &rseg, BUS_DMA_WAITOK); 217 if (error) { 218 aprint_error_dev(self, "dmamem_alloc failed (%d)\n", error); 219 goto fail; 220 } 221 222 error = bus_dmamem_map(sc->sc.sc_dmat, sc->sc_segs, rseg, PAGE_SIZE, 223 (void **)&sc->sc_cblk, BUS_DMA_WAITOK); 224 if (error) { 225 aprint_error_dev(self, "dmamem_map failed (%d)\n", error); 226 goto fail; 227 } 228 KASSERT(sc->sc_cblk != NULL); 229 230 memset(sc->sc_cblk, 0, PAGE_SIZE); 231 232 error = bus_dmamap_create(sc->sc.sc_dmat, PAGE_SIZE, 1, PAGE_SIZE, 0, 233 BUS_DMA_WAITOK, &sc->sc_dmamap); 234 if (error) { 235 aprint_error_dev(self, "dmamap_create failed (%d)\n", error); 236 goto fail; 237 } 238 239 error = bus_dmamap_load(sc->sc.sc_dmat, sc->sc_dmamap, sc->sc_cblk, 240 PAGE_SIZE, NULL, BUS_DMA_WAITOK|BUS_DMA_WRITE); 241 if (error) { 242 aprint_error_dev(self, "dmamap_load failed (%d)\n", error); 243 goto fail; 244 } 245 246 done: 247 #endif 248 config_interrupts(self, bcmemmc_attach_i); 249 return; 250 251 fail: 252 /* XXX add bus_dma failure cleanup */ 253 if (sc->sc_ih) { 254 fdtbus_intr_disestablish(sc->sc_phandle, sc->sc_ih); 255 sc->sc_ih = NULL; 256 } 257 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios); 258 } 259 260 static void 261 bcmemmc_attach_i(device_t self) 262 { 263 struct bcmemmc_softc * const sc = device_private(self); 264 int error; 265 266 error = sdhc_host_found(&sc->sc, sc->sc_iot, sc->sc_ioh, sc->sc_ios); 267 if (error != 0) { 268 aprint_error_dev(self, "couldn't initialize host, error=%d\n", 269 error); 270 goto fail; 271 } 272 return; 273 274 fail: 275 /* XXX add bus_dma failure cleanup */ 276 if (sc->sc_ih) { 277 fdtbus_intr_disestablish(sc->sc_phandle, sc->sc_ih); 278 sc->sc_ih = NULL; 279 } 280 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios); 281 } 282 283 #if NBCMDMAC > 0 284 static int 285 bcmemmc_xfer_data_dma(struct sdhc_softc *sdhc_sc, struct sdmmc_command *cmd) 286 { 287 struct bcmemmc_softc * const sc = device_private(sdhc_sc->sc_dev); 288 kmutex_t *plock = sdhc_host_lock(sc->sc_hosts[0]); 289 const bus_addr_t ad_sdhcdata = sc->sc_iob + SDHC_DATA; 290 size_t seg; 291 int error; 292 293 KASSERT(mutex_owned(plock)); 294 295 for (seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) { 296 sc->sc_cblk[seg].cb_ti = 297 __SHIFTIN(11, DMAC_TI_PERMAP); /* e.MMC */ 298 sc->sc_cblk[seg].cb_txfr_len = 299 cmd->c_dmamap->dm_segs[seg].ds_len; 300 /* 301 * All transfers are assumed to be multiples of 32-bits. 302 */ 303 KASSERTMSG((sc->sc_cblk[seg].cb_txfr_len & 0x3) == 0, 304 "seg %zu len %d", seg, sc->sc_cblk[seg].cb_txfr_len); 305 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 306 sc->sc_cblk[seg].cb_ti |= DMAC_TI_DEST_INC; 307 /* 308 * Use 128-bit mode if transfer is a multiple of 309 * 16-bytes. 310 */ 311 if ((sc->sc_cblk[seg].cb_txfr_len & 0xf) == 0) 312 sc->sc_cblk[seg].cb_ti |= DMAC_TI_DEST_WIDTH; 313 sc->sc_cblk[seg].cb_ti |= DMAC_TI_SRC_DREQ; 314 sc->sc_cblk[seg].cb_source_ad = ad_sdhcdata; 315 sc->sc_cblk[seg].cb_dest_ad = 316 cmd->c_dmamap->dm_segs[seg].ds_addr; 317 } else { 318 sc->sc_cblk[seg].cb_ti |= DMAC_TI_SRC_INC; 319 /* 320 * Use 128-bit mode if transfer is a multiple of 321 * 16-bytes. 322 */ 323 if ((sc->sc_cblk[seg].cb_txfr_len & 0xf) == 0) 324 sc->sc_cblk[seg].cb_ti |= DMAC_TI_SRC_WIDTH; 325 sc->sc_cblk[seg].cb_ti |= DMAC_TI_DEST_DREQ; 326 sc->sc_cblk[seg].cb_ti |= DMAC_TI_WAIT_RESP; 327 sc->sc_cblk[seg].cb_source_ad = 328 cmd->c_dmamap->dm_segs[seg].ds_addr; 329 sc->sc_cblk[seg].cb_dest_ad = ad_sdhcdata; 330 } 331 sc->sc_cblk[seg].cb_stride = 0; 332 if (seg == cmd->c_dmamap->dm_nsegs - 1) { 333 sc->sc_cblk[seg].cb_ti |= DMAC_TI_INTEN; 334 sc->sc_cblk[seg].cb_nextconbk = 0; 335 } else { 336 sc->sc_cblk[seg].cb_nextconbk = 337 sc->sc_dmamap->dm_segs[0].ds_addr + 338 sizeof(struct bcm_dmac_conblk) * (seg+1); 339 } 340 sc->sc_cblk[seg].cb_padding[0] = 0; 341 sc->sc_cblk[seg].cb_padding[1] = 0; 342 } 343 344 bus_dmamap_sync(sc->sc.sc_dmat, sc->sc_dmamap, 0, 345 sc->sc_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 346 347 error = 0; 348 349 KASSERT(sc->sc_state == EMMC_DMA_STATE_IDLE); 350 sc->sc_state = EMMC_DMA_STATE_BUSY; 351 bcm_dmac_set_conblk_addr(sc->sc_dmac, 352 sc->sc_dmamap->dm_segs[0].ds_addr); 353 error = bcm_dmac_transfer(sc->sc_dmac); 354 if (error) 355 return error; 356 357 while (sc->sc_state == EMMC_DMA_STATE_BUSY) { 358 error = cv_timedwait(&sc->sc_cv, plock, hz * 10); 359 if (error == EWOULDBLOCK) { 360 device_printf(sc->sc.sc_dev, "transfer timeout!\n"); 361 bcm_dmac_halt(sc->sc_dmac); 362 sc->sc_state = EMMC_DMA_STATE_IDLE; 363 error = ETIMEDOUT; 364 break; 365 } 366 } 367 368 bus_dmamap_sync(sc->sc.sc_dmat, sc->sc_dmamap, 0, 369 sc->sc_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 370 371 return error; 372 } 373 374 static void 375 bcmemmc_dma_done(uint32_t status, uint32_t error, void *arg) 376 { 377 struct bcmemmc_softc * const sc = arg; 378 kmutex_t *plock = sdhc_host_lock(sc->sc_hosts[0]); 379 380 if (status != (DMAC_CS_INT|DMAC_CS_END)) 381 device_printf(sc->sc.sc_dev, "status %#x error %#x\n", 382 status,error); 383 384 mutex_enter(plock); 385 KASSERT(sc->sc_state == EMMC_DMA_STATE_BUSY); 386 if (status & DMAC_CS_END) 387 sc->sc_state = EMMC_DMA_STATE_IDLE; 388 cv_broadcast(&sc->sc_cv); 389 mutex_exit(plock); 390 } 391 #endif 392
Indexes created Tue Sep 30 11:09:46 GMT 2025