bcm2835_emmc.c revision 1.42
1 /* $NetBSD: bcm2835_emmc.c,v 1.42 2021/01/27 03:10:19 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Nick Hudson 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: bcm2835_emmc.c,v 1.42 2021/01/27 03:10:19 thorpej Exp $"); 34 35 #include "bcmdmac.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/device.h> 40 #include <sys/bus.h> 41 #include <sys/condvar.h> 42 #include <sys/mutex.h> 43 #include <sys/kernel.h> 44 45 #include <arm/broadcom/bcm2835reg.h> 46 #include <arm/broadcom/bcm2835_dmac.h> 47 48 #include <dev/sdmmc/sdhcreg.h> 49 #include <dev/sdmmc/sdhcvar.h> 50 #include <dev/sdmmc/sdmmcvar.h> 51 52 #include <dev/fdt/fdtvar.h> 53 54 #include <arm/fdt/arm_fdtvar.h> 55 56 enum bcmemmc_dma_state { 57 EMMC_DMA_STATE_IDLE, 58 EMMC_DMA_STATE_BUSY, 59 }; 60 61 struct bcmemmc_softc { 62 struct sdhc_softc sc; 63 64 bus_space_tag_t sc_iot; 65 bus_space_handle_t sc_ioh; 66 bus_addr_t sc_iob; 67 bus_size_t sc_ios; 68 struct sdhc_host *sc_hosts[1]; 69 void *sc_ih; 70 int sc_phandle; 71 72 kcondvar_t sc_cv; 73 74 enum bcmemmc_dma_state sc_state; 75 76 struct bcm_dmac_channel *sc_dmac; 77 78 bus_dmamap_t sc_dmamap; 79 bus_dma_segment_t sc_segs[1]; /* XXX assumes enough descriptors fit in one page */ 80 struct bcm_dmac_conblk *sc_cblk; 81 }; 82 83 static int bcmemmc_match(device_t, struct cfdata *, void *); 84 static void bcmemmc_attach(device_t, device_t, void *); 85 static void bcmemmc_attach_i(device_t); 86 #if NBCMDMAC > 0 87 static int bcmemmc_xfer_data_dma(struct sdhc_softc *, struct sdmmc_command *); 88 static void bcmemmc_dma_done(uint32_t, uint32_t, void *); 89 #endif 90 91 CFATTACH_DECL_NEW(bcmemmc, sizeof(struct bcmemmc_softc), 92 bcmemmc_match, bcmemmc_attach, NULL, NULL); 93 94 enum bcmemmc_type { 95 BCM2835_SDHCI, 96 BCM2711_EMMC2, 97 }; 98 99 static const struct device_compatible_entry compat_data[] = { 100 { .compat = "brcm,bcm2835-sdhci", .value = BCM2835_SDHCI }, 101 { .compat = "brcm,bcm2711-emmc2", .value = BCM2711_EMMC2 }, 102 DEVICE_COMPAT_EOL 103 }; 104 105 /* ARGSUSED */ 106 static int 107 bcmemmc_match(device_t parent, struct cfdata *match, void *aux) 108 { 109 struct fdt_attach_args * const faa = aux; 110 111 return of_compatible_match(faa->faa_phandle, compat_data); 112 } 113 114 /* ARGSUSED */ 115 static void 116 bcmemmc_attach(device_t parent, device_t self, void *aux) 117 { 118 struct bcmemmc_softc *sc = device_private(self); 119 struct fdt_attach_args * const faa = aux; 120 const int phandle = faa->faa_phandle; 121 int error; 122 123 sc->sc.sc_dev = self; 124 sc->sc.sc_dmat = faa->faa_dmat; 125 sc->sc.sc_flags = 0; 126 sc->sc.sc_flags |= SDHC_FLAG_32BIT_ACCESS; 127 sc->sc.sc_flags |= SDHC_FLAG_HOSTCAPS; 128 sc->sc.sc_flags |= SDHC_FLAG_NO_HS_BIT; 129 sc->sc.sc_caps = SDHC_VOLTAGE_SUPP_3_3V | SDHC_HIGH_SPEED_SUPP | 130 (SDHC_MAX_BLK_LEN_1024 << SDHC_MAX_BLK_LEN_SHIFT); 131 132 sc->sc.sc_host = sc->sc_hosts; 133 sc->sc.sc_clkbase = 50000; /* Default to 50MHz */ 134 sc->sc_iot = faa->faa_bst; 135 136 bus_addr_t addr; 137 bus_size_t size; 138 139 error = fdtbus_get_reg(phandle, 0, &addr, &size); 140 if (error) { 141 aprint_error_dev(sc->sc.sc_dev, "unable to map device\n"); 142 return; 143 } 144 sc->sc_phandle = phandle; 145 146 /* Enable clocks */ 147 struct clk *clk; 148 for (int i = 0; (clk = fdtbus_clock_get_index(phandle, i)); i++) { 149 if (clk_enable(clk) != 0) { 150 aprint_error(": failed to enable clock #%d\n", i); 151 return; 152 } 153 if (i == 0) 154 sc->sc.sc_clkbase = clk_get_rate(clk) / 1000; 155 } 156 aprint_debug_dev(self, "ref freq %u kHz\n", sc->sc.sc_clkbase); 157 158 error = bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh); 159 if (error) { 160 aprint_error_dev(sc->sc.sc_dev, "unable to map device\n"); 161 return; 162 } 163 sc->sc_iob = addr; 164 sc->sc_ios = size; 165 166 aprint_naive(": SDHC controller\n"); 167 aprint_normal(": SDHC controller\n"); 168 169 char intrstr[128]; 170 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 171 aprint_error(": failed to decode interrupt\n"); 172 return; 173 } 174 175 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_SDMMC, 0, 176 sdhc_intr, &sc->sc); 177 178 if (sc->sc_ih == NULL) { 179 aprint_error_dev(self, "failed to establish interrupt %s\n", 180 intrstr); 181 goto fail; 182 } 183 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 184 185 #if NBCMDMAC > 0 186 enum bcmemmc_type type = 187 of_compatible_lookup(phandle, compat_data)->value; 188 189 if (type != BCM2835_SDHCI) 190 goto done; 191 192 sc->sc_dmac = bcm_dmac_alloc(BCM_DMAC_TYPE_NORMAL, IPL_SDMMC, 193 bcmemmc_dma_done, sc); 194 if (sc->sc_dmac == NULL) 195 goto done; 196 197 sc->sc.sc_flags |= SDHC_FLAG_USE_DMA; 198 sc->sc.sc_flags |= SDHC_FLAG_EXTERNAL_DMA; 199 sc->sc.sc_caps |= SDHC_DMA_SUPPORT; 200 sc->sc.sc_vendor_transfer_data_dma = bcmemmc_xfer_data_dma; 201 202 sc->sc_state = EMMC_DMA_STATE_IDLE; 203 cv_init(&sc->sc_cv, "bcmemmcdma"); 204 205 int rseg; 206 error = bus_dmamem_alloc(sc->sc.sc_dmat, PAGE_SIZE, PAGE_SIZE, 207 PAGE_SIZE, sc->sc_segs, 1, &rseg, BUS_DMA_WAITOK); 208 if (error) { 209 aprint_error_dev(self, "dmamem_alloc failed (%d)\n", error); 210 goto fail; 211 } 212 213 error = bus_dmamem_map(sc->sc.sc_dmat, sc->sc_segs, rseg, PAGE_SIZE, 214 (void **)&sc->sc_cblk, BUS_DMA_WAITOK); 215 if (error) { 216 aprint_error_dev(self, "dmamem_map failed (%d)\n", error); 217 goto fail; 218 } 219 KASSERT(sc->sc_cblk != NULL); 220 221 memset(sc->sc_cblk, 0, PAGE_SIZE); 222 223 error = bus_dmamap_create(sc->sc.sc_dmat, PAGE_SIZE, 1, PAGE_SIZE, 0, 224 BUS_DMA_WAITOK, &sc->sc_dmamap); 225 if (error) { 226 aprint_error_dev(self, "dmamap_create failed (%d)\n", error); 227 goto fail; 228 } 229 230 error = bus_dmamap_load(sc->sc.sc_dmat, sc->sc_dmamap, sc->sc_cblk, 231 PAGE_SIZE, NULL, BUS_DMA_WAITOK|BUS_DMA_WRITE); 232 if (error) { 233 aprint_error_dev(self, "dmamap_load failed (%d)\n", error); 234 goto fail; 235 } 236 237 done: 238 #endif 239 config_interrupts(self, bcmemmc_attach_i); 240 return; 241 242 fail: 243 /* XXX add bus_dma failure cleanup */ 244 if (sc->sc_ih) { 245 fdtbus_intr_disestablish(sc->sc_phandle, sc->sc_ih); 246 sc->sc_ih = NULL; 247 } 248 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios); 249 } 250 251 static void 252 bcmemmc_attach_i(device_t self) 253 { 254 struct bcmemmc_softc * const sc = device_private(self); 255 int error; 256 257 error = sdhc_host_found(&sc->sc, sc->sc_iot, sc->sc_ioh, sc->sc_ios); 258 if (error != 0) { 259 aprint_error_dev(self, "couldn't initialize host, error=%d\n", 260 error); 261 goto fail; 262 } 263 return; 264 265 fail: 266 /* XXX add bus_dma failure cleanup */ 267 if (sc->sc_ih) { 268 fdtbus_intr_disestablish(sc->sc_phandle, sc->sc_ih); 269 sc->sc_ih = NULL; 270 } 271 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios); 272 } 273 274 #if NBCMDMAC > 0 275 static int 276 bcmemmc_xfer_data_dma(struct sdhc_softc *sdhc_sc, struct sdmmc_command *cmd) 277 { 278 struct bcmemmc_softc * const sc = device_private(sdhc_sc->sc_dev); 279 kmutex_t *plock = sdhc_host_lock(sc->sc_hosts[0]); 280 const bus_addr_t ad_sdhcdata = sc->sc_iob + SDHC_DATA; 281 size_t seg; 282 int error; 283 284 KASSERT(mutex_owned(plock)); 285 286 for (seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) { 287 sc->sc_cblk[seg].cb_ti = 288 __SHIFTIN(11, DMAC_TI_PERMAP); /* e.MMC */ 289 sc->sc_cblk[seg].cb_txfr_len = 290 cmd->c_dmamap->dm_segs[seg].ds_len; 291 /* 292 * All transfers are assumed to be multiples of 32-bits. 293 */ 294 KASSERTMSG((sc->sc_cblk[seg].cb_txfr_len & 0x3) == 0, 295 "seg %zu len %d", seg, sc->sc_cblk[seg].cb_txfr_len); 296 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 297 sc->sc_cblk[seg].cb_ti |= DMAC_TI_DEST_INC; 298 /* 299 * Use 128-bit mode if transfer is a multiple of 300 * 16-bytes. 301 */ 302 if ((sc->sc_cblk[seg].cb_txfr_len & 0xf) == 0) 303 sc->sc_cblk[seg].cb_ti |= DMAC_TI_DEST_WIDTH; 304 sc->sc_cblk[seg].cb_ti |= DMAC_TI_SRC_DREQ; 305 sc->sc_cblk[seg].cb_source_ad = ad_sdhcdata; 306 sc->sc_cblk[seg].cb_dest_ad = 307 cmd->c_dmamap->dm_segs[seg].ds_addr; 308 } else { 309 sc->sc_cblk[seg].cb_ti |= DMAC_TI_SRC_INC; 310 /* 311 * Use 128-bit mode if transfer is a multiple of 312 * 16-bytes. 313 */ 314 if ((sc->sc_cblk[seg].cb_txfr_len & 0xf) == 0) 315 sc->sc_cblk[seg].cb_ti |= DMAC_TI_SRC_WIDTH; 316 sc->sc_cblk[seg].cb_ti |= DMAC_TI_DEST_DREQ; 317 sc->sc_cblk[seg].cb_ti |= DMAC_TI_WAIT_RESP; 318 sc->sc_cblk[seg].cb_source_ad = 319 cmd->c_dmamap->dm_segs[seg].ds_addr; 320 sc->sc_cblk[seg].cb_dest_ad = ad_sdhcdata; 321 } 322 sc->sc_cblk[seg].cb_stride = 0; 323 if (seg == cmd->c_dmamap->dm_nsegs - 1) { 324 sc->sc_cblk[seg].cb_ti |= DMAC_TI_INTEN; 325 sc->sc_cblk[seg].cb_nextconbk = 0; 326 } else { 327 sc->sc_cblk[seg].cb_nextconbk = 328 sc->sc_dmamap->dm_segs[0].ds_addr + 329 sizeof(struct bcm_dmac_conblk) * (seg+1); 330 } 331 bcm_dmac_swap_conblk(&sc->sc_cblk[seg]); 332 sc->sc_cblk[seg].cb_padding[0] = 0; 333 sc->sc_cblk[seg].cb_padding[1] = 0; 334 } 335 336 bus_dmamap_sync(sc->sc.sc_dmat, sc->sc_dmamap, 0, 337 sc->sc_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 338 339 error = 0; 340 341 KASSERT(sc->sc_state == EMMC_DMA_STATE_IDLE); 342 sc->sc_state = EMMC_DMA_STATE_BUSY; 343 bcm_dmac_set_conblk_addr(sc->sc_dmac, 344 sc->sc_dmamap->dm_segs[0].ds_addr); 345 error = bcm_dmac_transfer(sc->sc_dmac); 346 if (error) 347 return error; 348 349 while (sc->sc_state == EMMC_DMA_STATE_BUSY) { 350 error = cv_timedwait(&sc->sc_cv, plock, hz * 10); 351 if (error == EWOULDBLOCK) { 352 device_printf(sc->sc.sc_dev, "transfer timeout!\n"); 353 bcm_dmac_halt(sc->sc_dmac); 354 sc->sc_state = EMMC_DMA_STATE_IDLE; 355 error = ETIMEDOUT; 356 break; 357 } 358 } 359 360 bus_dmamap_sync(sc->sc.sc_dmat, sc->sc_dmamap, 0, 361 sc->sc_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 362 363 return error; 364 } 365 366 static void 367 bcmemmc_dma_done(uint32_t status, uint32_t error, void *arg) 368 { 369 struct bcmemmc_softc * const sc = arg; 370 kmutex_t *plock = sdhc_host_lock(sc->sc_hosts[0]); 371 372 if (status != (DMAC_CS_INT|DMAC_CS_END)) 373 device_printf(sc->sc.sc_dev, "status %#x error %#x\n", 374 status,error); 375 376 mutex_enter(plock); 377 KASSERT(sc->sc_state == EMMC_DMA_STATE_BUSY); 378 if (status & DMAC_CS_END) 379 sc->sc_state = EMMC_DMA_STATE_IDLE; 380 cv_broadcast(&sc->sc_cv); 381 mutex_exit(plock); 382 } 383 #endif 384
Indexes created Tue Sep 30 17:09:57 GMT 2025