1 /* $NetBSD: bcm2835_sdhost.c,v 1.10 2021/08/07 16:18:43 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: bcm2835_sdhost.c,v 1.10 2021/08/07 16:18:43 thorpej Exp $"); 31 32 #include "bcmdmac.h" 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/intr.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/gpio.h> 41 42 #include <arm/broadcom/bcm2835reg.h> 43 #include <arm/broadcom/bcm2835_dmac.h> 44 45 #include <dev/sdmmc/sdmmcvar.h> 46 #include <dev/sdmmc/sdmmcchip.h> 47 #include <dev/sdmmc/sdmmc_ioreg.h> 48 49 #include <dev/fdt/fdtvar.h> 50 51 #include <arm/fdt/arm_fdtvar.h> 52 53 #define SDCMD 0x00 54 #define SDCMD_NEW __BIT(15) 55 #define SDCMD_FAIL __BIT(14) 56 #define SDCMD_BUSY __BIT(11) 57 #define SDCMD_NORESP __BIT(10) 58 #define SDCMD_LONGRESP __BIT(9) 59 #define SDCMD_WRITE __BIT(7) 60 #define SDCMD_READ __BIT(6) 61 #define SDARG 0x04 62 #define SDTOUT 0x08 63 #define SDTOUT_DEFAULT 0xf00000 64 #define SDCDIV 0x0c 65 #define SDCDIV_MASK __BITS(10,0) 66 #define SDRSP0 0x10 67 #define SDRSP1 0x14 68 #define SDRSP2 0x18 69 #define SDRSP3 0x1c 70 #define SDHSTS 0x20 71 #define SDHSTS_BUSY __BIT(10) 72 #define SDHSTS_BLOCK __BIT(9) 73 #define SDHSTS_SDIO __BIT(8) 74 #define SDHSTS_REW_TO __BIT(7) 75 #define SDHSTS_CMD_TO __BIT(6) 76 #define SDHSTS_CRC16_E __BIT(5) 77 #define SDHSTS_CRC7_E __BIT(4) 78 #define SDHSTS_FIFO_E __BIT(3) 79 #define SDHSTS_DATA __BIT(0) 80 #define SDVDD 0x30 81 #define SDVDD_POWER __BIT(0) 82 #define SDEDM 0x34 83 #define SDEDM_RD_FIFO __BITS(18,14) 84 #define SDEDM_WR_FIFO __BITS(13,9) 85 #define SDHCFG 0x38 86 #define SDHCFG_BUSY_EN __BIT(10) 87 #define SDHCFG_BLOCK_EN __BIT(8) 88 #define SDHCFG_SDIO_EN __BIT(5) 89 #define SDHCFG_DATA_EN __BIT(4) 90 #define SDHCFG_SLOW __BIT(3) 91 #define SDHCFG_WIDE_EXT __BIT(2) 92 #define SDHCFG_WIDE_INT __BIT(1) 93 #define SDHCFG_REL_CMD __BIT(0) 94 #define SDHBCT 0x3c 95 #define SDDATA 0x40 96 #define SDHBLC 0x50 97 98 struct sdhost_softc; 99 100 static int sdhost_match(device_t, cfdata_t, void *); 101 static void sdhost_attach(device_t, device_t, void *); 102 static void sdhost_attach_i(device_t); 103 104 static int sdhost_intr(void *); 105 static int sdhost_dma_setup(struct sdhost_softc *); 106 static void sdhost_dma_done(uint32_t, uint32_t, void *); 107 108 static int sdhost_host_reset(sdmmc_chipset_handle_t); 109 static uint32_t sdhost_host_ocr(sdmmc_chipset_handle_t); 110 static int sdhost_host_maxblklen(sdmmc_chipset_handle_t); 111 static int sdhost_card_detect(sdmmc_chipset_handle_t); 112 static int sdhost_write_protect(sdmmc_chipset_handle_t); 113 static int sdhost_bus_power(sdmmc_chipset_handle_t, uint32_t); 114 static int sdhost_bus_clock(sdmmc_chipset_handle_t, int, bool); 115 static int sdhost_bus_width(sdmmc_chipset_handle_t, int); 116 static int sdhost_bus_rod(sdmmc_chipset_handle_t, int); 117 static void sdhost_exec_command(sdmmc_chipset_handle_t, 118 struct sdmmc_command *); 119 static void sdhost_card_enable_intr(sdmmc_chipset_handle_t, int); 120 static void sdhost_card_intr_ack(sdmmc_chipset_handle_t); 121 122 static struct sdmmc_chip_functions sdhost_chip_functions = { 123 .host_reset = sdhost_host_reset, 124 .host_ocr = sdhost_host_ocr, 125 .host_maxblklen = sdhost_host_maxblklen, 126 .card_detect = sdhost_card_detect, 127 .write_protect = sdhost_write_protect, 128 .bus_power = sdhost_bus_power, 129 .bus_clock_ddr = sdhost_bus_clock, 130 .bus_width = sdhost_bus_width, 131 .bus_rod = sdhost_bus_rod, 132 .exec_command = sdhost_exec_command, 133 .card_enable_intr = sdhost_card_enable_intr, 134 .card_intr_ack = sdhost_card_intr_ack, 135 }; 136 137 struct sdhost_softc { 138 device_t sc_dev; 139 bus_space_tag_t sc_bst; 140 bus_space_handle_t sc_bsh; 141 bus_dma_tag_t sc_dmat; 142 143 bus_addr_t sc_addr; 144 145 void *sc_ih; 146 kmutex_t sc_intr_lock; 147 kcondvar_t sc_intr_cv; 148 kcondvar_t sc_dma_cv; 149 150 u_int sc_rate; 151 152 int sc_mmc_width; 153 int sc_mmc_present; 154 155 device_t sc_sdmmc_dev; 156 157 struct bcm_dmac_channel *sc_dmac; 158 159 bus_dmamap_t sc_dmamap; 160 bus_dma_segment_t sc_segs[1]; 161 struct bcm_dmac_conblk *sc_cblk; 162 163 uint32_t sc_intr_hsts; 164 165 uint32_t sc_dma_status; 166 uint32_t sc_dma_error; 167 }; 168 169 CFATTACH_DECL_NEW(bcmsdhost, sizeof(struct sdhost_softc), 170 sdhost_match, sdhost_attach, NULL, NULL); 171 172 #define SDHOST_WRITE(sc, reg, val) \ 173 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 174 #define SDHOST_READ(sc, reg) \ 175 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 176 177 static const struct device_compatible_entry compat_data[] = { 178 { .compat = "brcm,bcm2835-sdhost" }, 179 DEVICE_COMPAT_EOL 180 }; 181 182 static int 183 sdhost_match(device_t parent, cfdata_t cf, void *aux) 184 { 185 struct fdt_attach_args * const faa = aux; 186 187 return of_compatible_match(faa->faa_phandle, compat_data); 188 } 189 190 static void 191 sdhost_attach(device_t parent, device_t self, void *aux) 192 { 193 struct sdhost_softc * const sc = device_private(self); 194 struct fdt_attach_args * const faa = aux; 195 196 sc->sc_dev = self; 197 sc->sc_bst = faa->faa_bst; 198 sc->sc_dmat = faa->faa_dmat; 199 200 const int phandle = faa->faa_phandle; 201 bus_addr_t addr; 202 bus_size_t size; 203 204 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 205 aprint_error(": missing 'reg' property\n"); 206 return; 207 } 208 209 sc->sc_addr = addr; 210 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_BIO); 211 cv_init(&sc->sc_intr_cv, "sdhostintr"); 212 cv_init(&sc->sc_dma_cv, "sdhostdma"); 213 214 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 215 aprint_error(": couldn't map registers\n"); 216 return; 217 } 218 219 aprint_naive("\n"); 220 aprint_normal(": SD HOST controller\n"); 221 222 /* Enable clocks */ 223 struct clk *clk; 224 for (int i = 0; (clk = fdtbus_clock_get_index(phandle, i)); i++) { 225 if (clk_enable(clk) != 0) { 226 aprint_error(": failed to enable clock #%d\n", i); 227 return; 228 } 229 if (i == 0) 230 sc->sc_rate = clk_get_rate(clk); 231 } 232 233 aprint_debug_dev(self, "ref freq %u Hz\n", sc->sc_rate); 234 235 if (sdhost_dma_setup(sc) != 0) { 236 aprint_error_dev(self, "failed to setup DMA\n"); 237 return; 238 } 239 240 char intrstr[128]; 241 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 242 aprint_error(": failed to decode interrupt\n"); 243 return; 244 } 245 246 sc->sc_ih = fdtbus_intr_establish_xname(phandle, 0, IPL_SDMMC, 247 FDT_INTR_MPSAFE, sdhost_intr, sc, device_xname(self)); 248 if (sc->sc_ih == NULL) { 249 aprint_error_dev(self, "failed to establish interrupt %s\n", 250 intrstr); 251 return; 252 } 253 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 254 255 config_interrupts(self, sdhost_attach_i); 256 } 257 258 static int 259 sdhost_dma_setup(struct sdhost_softc *sc) 260 { 261 int error, rseg; 262 263 sc->sc_dmac = bcm_dmac_alloc(BCM_DMAC_TYPE_NORMAL, IPL_SDMMC, 264 sdhost_dma_done, sc); 265 if (sc->sc_dmac == NULL) 266 return ENXIO; 267 268 error = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, PAGE_SIZE, 269 PAGE_SIZE, sc->sc_segs, 1, &rseg, BUS_DMA_WAITOK); 270 if (error) 271 return error; 272 273 error = bus_dmamem_map(sc->sc_dmat, sc->sc_segs, rseg, PAGE_SIZE, 274 (void **)&sc->sc_cblk, BUS_DMA_WAITOK); 275 if (error) 276 return error; 277 278 memset(sc->sc_cblk, 0, PAGE_SIZE); 279 280 error = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1, PAGE_SIZE, 0, 281 BUS_DMA_WAITOK, &sc->sc_dmamap); 282 if (error) 283 return error; 284 285 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, sc->sc_cblk, 286 PAGE_SIZE, NULL, BUS_DMA_WAITOK|BUS_DMA_WRITE); 287 if (error) 288 return error; 289 290 return 0; 291 } 292 293 static void 294 sdhost_attach_i(device_t self) 295 { 296 struct sdhost_softc *sc = device_private(self); 297 struct sdmmcbus_attach_args saa; 298 299 sdhost_host_reset(sc); 300 sdhost_bus_width(sc, 1); 301 sdhost_bus_clock(sc, 400, false); 302 303 memset(&saa, 0, sizeof(saa)); 304 saa.saa_busname = "sdmmc"; 305 saa.saa_sct = &sdhost_chip_functions; 306 saa.saa_sch = sc; 307 saa.saa_dmat = sc->sc_dmat; 308 saa.saa_clkmin = 400; 309 saa.saa_clkmax = 50000; 310 saa.saa_caps = SMC_CAPS_DMA | 311 SMC_CAPS_MULTI_SEG_DMA | 312 SMC_CAPS_SD_HIGHSPEED | 313 SMC_CAPS_MMC_HIGHSPEED | 314 SMC_CAPS_4BIT_MODE; 315 316 sc->sc_sdmmc_dev = config_found(self, &saa, NULL, CFARGS_NONE); 317 } 318 319 static int 320 sdhost_intr(void *priv) 321 { 322 struct sdhost_softc * const sc = priv; 323 324 mutex_enter(&sc->sc_intr_lock); 325 const uint32_t hsts = SDHOST_READ(sc, SDHSTS); 326 if (!hsts) { 327 mutex_exit(&sc->sc_intr_lock); 328 return 0; 329 } 330 SDHOST_WRITE(sc, SDHSTS, hsts); 331 332 #ifdef SDHOST_DEBUG 333 device_printf(sc->sc_dev, "mmc intr hsts %#x\n", hsts); 334 #endif 335 336 if (hsts) { 337 sc->sc_intr_hsts |= hsts; 338 cv_broadcast(&sc->sc_intr_cv); 339 } 340 341 mutex_exit(&sc->sc_intr_lock); 342 343 return 1; 344 } 345 346 static int 347 sdhost_dma_transfer(struct sdhost_softc *sc, struct sdmmc_command *cmd) 348 { 349 size_t seg; 350 int error; 351 352 KASSERT(mutex_owned(&sc->sc_intr_lock)); 353 354 for (seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) { 355 sc->sc_cblk[seg].cb_ti = 356 __SHIFTIN(13, DMAC_TI_PERMAP); /* SD HOST */ 357 sc->sc_cblk[seg].cb_txfr_len = 358 cmd->c_dmamap->dm_segs[seg].ds_len; 359 const bus_addr_t ad_sddata = sc->sc_addr + SDDATA; 360 361 /* 362 * All transfers are assumed to be multiples of 32-bits. 363 */ 364 KASSERTMSG((sc->sc_cblk[seg].cb_txfr_len & 0x3) == 0, 365 "seg %zu len %d", seg, sc->sc_cblk[seg].cb_txfr_len); 366 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 367 sc->sc_cblk[seg].cb_ti |= DMAC_TI_DEST_INC; 368 /* 369 * Use 128-bit mode if transfer is a multiple of 370 * 16-bytes. 371 */ 372 if ((sc->sc_cblk[seg].cb_txfr_len & 0xf) == 0) 373 sc->sc_cblk[seg].cb_ti |= DMAC_TI_DEST_WIDTH; 374 sc->sc_cblk[seg].cb_ti |= DMAC_TI_SRC_DREQ; 375 sc->sc_cblk[seg].cb_source_ad = ad_sddata; 376 sc->sc_cblk[seg].cb_dest_ad = 377 cmd->c_dmamap->dm_segs[seg].ds_addr; 378 } else { 379 sc->sc_cblk[seg].cb_ti |= DMAC_TI_SRC_INC; 380 /* 381 * Use 128-bit mode if transfer is a multiple of 382 * 16-bytes. 383 */ 384 if ((sc->sc_cblk[seg].cb_txfr_len & 0xf) == 0) 385 sc->sc_cblk[seg].cb_ti |= DMAC_TI_SRC_WIDTH; 386 sc->sc_cblk[seg].cb_ti |= DMAC_TI_DEST_DREQ; 387 sc->sc_cblk[seg].cb_ti |= DMAC_TI_WAIT_RESP; 388 sc->sc_cblk[seg].cb_source_ad = 389 cmd->c_dmamap->dm_segs[seg].ds_addr; 390 sc->sc_cblk[seg].cb_dest_ad = ad_sddata; 391 } 392 sc->sc_cblk[seg].cb_stride = 0; 393 if (seg == cmd->c_dmamap->dm_nsegs - 1) { 394 sc->sc_cblk[seg].cb_ti |= DMAC_TI_INTEN; 395 sc->sc_cblk[seg].cb_nextconbk = 0; 396 } else { 397 sc->sc_cblk[seg].cb_nextconbk = 398 sc->sc_dmamap->dm_segs[0].ds_addr + 399 sizeof(struct bcm_dmac_conblk) * (seg+1); 400 } 401 bcm_dmac_swap_conblk(&sc->sc_cblk[seg]); 402 sc->sc_cblk[seg].cb_padding[0] = 0; 403 sc->sc_cblk[seg].cb_padding[1] = 0; 404 } 405 406 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 0, 407 sc->sc_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 408 409 error = 0; 410 411 sc->sc_dma_status = 0; 412 sc->sc_dma_error = 0; 413 414 bcm_dmac_set_conblk_addr(sc->sc_dmac, 415 sc->sc_dmamap->dm_segs[0].ds_addr); 416 error = bcm_dmac_transfer(sc->sc_dmac); 417 if (error) 418 return error; 419 420 return 0; 421 } 422 423 static int 424 sdhost_dma_wait(struct sdhost_softc *sc, struct sdmmc_command *cmd) 425 { 426 int error = 0; 427 428 while (sc->sc_dma_status == 0 && sc->sc_dma_error == 0) { 429 error = cv_timedwait(&sc->sc_dma_cv, &sc->sc_intr_lock, hz*5); 430 if (error == EWOULDBLOCK) { 431 device_printf(sc->sc_dev, "transfer timeout!\n"); 432 bcm_dmac_halt(sc->sc_dmac); 433 error = ETIMEDOUT; 434 break; 435 } 436 } 437 438 if (sc->sc_dma_status & DMAC_CS_END) { 439 cmd->c_resid = 0; 440 error = 0; 441 } else { 442 error = EIO; 443 } 444 445 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 0, 446 sc->sc_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 447 448 return error; 449 } 450 451 static void 452 sdhost_dma_done(uint32_t status, uint32_t error, void *arg) 453 { 454 struct sdhost_softc * const sc = arg; 455 456 if (status != (DMAC_CS_INT|DMAC_CS_END)) 457 device_printf(sc->sc_dev, "dma status %#x error %#x\n", 458 status, error); 459 460 mutex_enter(&sc->sc_intr_lock); 461 sc->sc_dma_status = status; 462 sc->sc_dma_error = error; 463 cv_broadcast(&sc->sc_dma_cv); 464 mutex_exit(&sc->sc_intr_lock); 465 } 466 467 static int 468 sdhost_wait_idle(struct sdhost_softc *sc, int timeout) 469 { 470 int retry; 471 472 KASSERT(mutex_owned(&sc->sc_intr_lock)); 473 474 retry = timeout * 1000; 475 476 while (--retry > 0) { 477 const uint32_t cmd = SDHOST_READ(sc, SDCMD); 478 if ((cmd & SDCMD_NEW) == 0) 479 return 0; 480 delay(1); 481 } 482 483 return ETIMEDOUT; 484 } 485 486 static int 487 sdhost_host_reset(sdmmc_chipset_handle_t sch) 488 { 489 struct sdhost_softc * const sc = sch; 490 uint32_t edm; 491 492 SDHOST_WRITE(sc, SDVDD, 0); 493 SDHOST_WRITE(sc, SDCMD, 0); 494 SDHOST_WRITE(sc, SDARG, 0); 495 SDHOST_WRITE(sc, SDTOUT, SDTOUT_DEFAULT); 496 SDHOST_WRITE(sc, SDCDIV, 0); 497 SDHOST_WRITE(sc, SDHSTS, SDHOST_READ(sc, SDHSTS)); 498 SDHOST_WRITE(sc, SDHCFG, 0); 499 SDHOST_WRITE(sc, SDHBCT, 0); 500 SDHOST_WRITE(sc, SDHBLC, 0); 501 502 edm = SDHOST_READ(sc, SDEDM); 503 edm &= ~(SDEDM_RD_FIFO|SDEDM_WR_FIFO); 504 edm |= __SHIFTIN(4, SDEDM_RD_FIFO); 505 edm |= __SHIFTIN(4, SDEDM_WR_FIFO); 506 SDHOST_WRITE(sc, SDEDM, edm); 507 delay(20000); 508 SDHOST_WRITE(sc, SDVDD, SDVDD_POWER); 509 delay(20000); 510 511 SDHOST_WRITE(sc, SDHCFG, 0); 512 SDHOST_WRITE(sc, SDCDIV, SDCDIV_MASK); 513 514 return 0; 515 } 516 517 static uint32_t 518 sdhost_host_ocr(sdmmc_chipset_handle_t sch) 519 { 520 return MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V | MMC_OCR_HCS; 521 } 522 523 static int 524 sdhost_host_maxblklen(sdmmc_chipset_handle_t sch) 525 { 526 return 8192; 527 } 528 529 static int 530 sdhost_card_detect(sdmmc_chipset_handle_t sch) 531 { 532 return 1; /* XXX */ 533 } 534 535 static int 536 sdhost_write_protect(sdmmc_chipset_handle_t sch) 537 { 538 return 0; /* no write protect pin, assume rw */ 539 } 540 541 static int 542 sdhost_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 543 { 544 return 0; 545 } 546 547 static int 548 sdhost_bus_clock(sdmmc_chipset_handle_t sch, int freq, bool ddr) 549 { 550 struct sdhost_softc * const sc = sch; 551 u_int target_rate = freq * 1000; 552 int div; 553 554 if (freq == 0) 555 div = SDCDIV_MASK; 556 else { 557 div = sc->sc_rate / target_rate; 558 if (div < 2) 559 div = 2; 560 if ((sc->sc_rate / div) > target_rate) 561 div++; 562 div -= 2; 563 if (div > SDCDIV_MASK) 564 div = SDCDIV_MASK; 565 } 566 567 SDHOST_WRITE(sc, SDCDIV, div); 568 569 return 0; 570 } 571 572 static int 573 sdhost_bus_width(sdmmc_chipset_handle_t sch, int width) 574 { 575 struct sdhost_softc * const sc = sch; 576 uint32_t hcfg; 577 578 #ifdef SDHOST_DEBUG 579 aprint_normal_dev(sc->sc_dev, "width = %d\n", width); 580 #endif 581 582 hcfg = SDHOST_READ(sc, SDHCFG); 583 if (width == 4) 584 hcfg |= SDHCFG_WIDE_EXT; 585 else 586 hcfg &= ~SDHCFG_WIDE_EXT; 587 hcfg |= (SDHCFG_WIDE_INT | SDHCFG_SLOW); 588 SDHOST_WRITE(sc, SDHCFG, hcfg); 589 590 return 0; 591 } 592 593 static int 594 sdhost_bus_rod(sdmmc_chipset_handle_t sch, int on) 595 { 596 return -1; 597 } 598 599 static void 600 sdhost_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 601 { 602 struct sdhost_softc * const sc = sch; 603 uint32_t cmdval, hcfg; 604 u_int nblks; 605 606 #ifdef SDHOST_DEBUG 607 aprint_normal_dev(sc->sc_dev, 608 "opcode %d flags 0x%x data %p datalen %d blklen %d\n", 609 cmd->c_opcode, cmd->c_flags, cmd->c_data, cmd->c_datalen, 610 cmd->c_blklen); 611 #endif 612 613 mutex_enter(&sc->sc_intr_lock); 614 615 hcfg = SDHOST_READ(sc, SDHCFG); 616 SDHOST_WRITE(sc, SDHCFG, hcfg | SDHCFG_BUSY_EN); 617 618 sc->sc_intr_hsts = 0; 619 620 cmd->c_error = sdhost_wait_idle(sc, 5000); 621 if (cmd->c_error != 0) { 622 #ifdef SDHOST_DEBUG 623 device_printf(sc->sc_dev, "device is busy\n"); 624 #endif 625 goto done; 626 } 627 628 cmdval = SDCMD_NEW; 629 if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT)) 630 cmdval |= SDCMD_NORESP; 631 if (ISSET(cmd->c_flags, SCF_RSP_136)) 632 cmdval |= SDCMD_LONGRESP; 633 if (ISSET(cmd->c_flags, SCF_RSP_BSY)) 634 cmdval |= SDCMD_BUSY; 635 636 if (cmd->c_datalen > 0) { 637 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 638 cmdval |= SDCMD_READ; 639 else 640 cmdval |= SDCMD_WRITE; 641 642 nblks = cmd->c_datalen / cmd->c_blklen; 643 if (nblks == 0 || (cmd->c_datalen % cmd->c_blklen) != 0) 644 ++nblks; 645 646 SDHOST_WRITE(sc, SDHBCT, cmd->c_blklen); 647 SDHOST_WRITE(sc, SDHBLC, nblks); 648 649 cmd->c_resid = cmd->c_datalen; 650 cmd->c_error = sdhost_dma_transfer(sc, cmd); 651 if (cmd->c_error != 0) { 652 #ifdef SDHOST_DEBUG 653 device_printf(sc->sc_dev, "dma transfer failed: %d\n", 654 cmd->c_error); 655 #endif 656 goto done; 657 } 658 } 659 660 SDHOST_WRITE(sc, SDARG, cmd->c_arg); 661 SDHOST_WRITE(sc, SDCMD, cmdval | cmd->c_opcode); 662 663 if (cmd->c_datalen > 0) { 664 cmd->c_error = sdhost_dma_wait(sc, cmd); 665 if (cmd->c_error != 0) { 666 #ifdef SDHOST_DEBUG 667 device_printf(sc->sc_dev, 668 "wait dma failed: %d\n", cmd->c_error); 669 #endif 670 goto done; 671 } 672 } 673 674 cmd->c_error = sdhost_wait_idle(sc, 5000); 675 if (cmd->c_error != 0) { 676 #ifdef SDHOST_DEBUG 677 device_printf(sc->sc_dev, 678 "wait cmd idle (%#x) failed: %d\n", 679 SDHOST_READ(sc, SDCMD), cmd->c_error); 680 #endif 681 } 682 683 if ((SDHOST_READ(sc, SDCMD) & SDCMD_FAIL) != 0) { 684 #ifdef SDHOST_DEBUG 685 device_printf(sc->sc_dev, "SDCMD: %#x\n", 686 SDHOST_READ(sc, SDCMD)); 687 #endif 688 cmd->c_error = EIO; 689 goto done; 690 } 691 692 if (ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 693 if (ISSET(cmd->c_flags, SCF_RSP_136)) { 694 cmd->c_resp[0] = SDHOST_READ(sc, SDRSP0); 695 cmd->c_resp[1] = SDHOST_READ(sc, SDRSP1); 696 cmd->c_resp[2] = SDHOST_READ(sc, SDRSP2); 697 cmd->c_resp[3] = SDHOST_READ(sc, SDRSP3); 698 if (ISSET(cmd->c_flags, SCF_RSP_CRC)) { 699 cmd->c_resp[0] = (cmd->c_resp[0] >> 8) | 700 (cmd->c_resp[1] << 24); 701 cmd->c_resp[1] = (cmd->c_resp[1] >> 8) | 702 (cmd->c_resp[2] << 24); 703 cmd->c_resp[2] = (cmd->c_resp[2] >> 8) | 704 (cmd->c_resp[3] << 24); 705 cmd->c_resp[3] = (cmd->c_resp[3] >> 8); 706 } 707 } else { 708 cmd->c_resp[0] = SDHOST_READ(sc, SDRSP0); 709 } 710 } 711 712 done: 713 cmd->c_flags |= SCF_ITSDONE; 714 SDHOST_WRITE(sc, SDHCFG, hcfg); 715 SDHOST_WRITE(sc, SDHSTS, SDHOST_READ(sc, SDHSTS)); 716 mutex_exit(&sc->sc_intr_lock); 717 718 #ifdef SDHOST_DEBUG 719 if (cmd->c_error != 0) 720 device_printf(sc->sc_dev, "command failed with error %d\n", 721 cmd->c_error); 722 #endif 723 } 724 725 static void 726 sdhost_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 727 { 728 } 729 730 static void 731 sdhost_card_intr_ack(sdmmc_chipset_handle_t sch) 732 { 733 } 734
Indexes created Sat Sep 20 22:09:52 GMT 2025