a9tmr.c revision 1.1
1 /* $NetBSD: a9tmr.c,v 1.1 2012/09/01 00:03:14 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: a9tmr.c,v 1.1 2012/09/01 00:03:14 matt Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/device.h> 38 #include <sys/intr.h> 39 #include <sys/kernel.h> 40 #include <sys/proc.h> 41 #include <sys/systm.h> 42 #include <sys/timetc.h> 43 44 #include <prop/proplib.h> 45 46 #include <arm/cortex/a9tmr_reg.h> 47 #include <arm/cortex/a9tmr_var.h> 48 49 #include <arm/cortex/mpcore_var.h> 50 51 static int a9tmr_match(device_t, cfdata_t, void *); 52 static void a9tmr_attach(device_t, device_t, void *); 53 54 static int clockhandler(void *); 55 56 static u_int a9tmr_get_timecount(struct timecounter *); 57 58 static struct a9tmr_softc a9tmr_sc; 59 60 static struct timecounter a9tmr_timecounter = { 61 .tc_get_timecount = a9tmr_get_timecount, 62 .tc_poll_pps = 0, 63 .tc_counter_mask = ~0u, 64 .tc_frequency = 0, /* set by cpu_initclocks() */ 65 .tc_name = NULL, /* set by attach */ 66 .tc_quality = 500, 67 .tc_priv = &a9tmr_sc, 68 .tc_next = NULL, 69 }; 70 71 CFATTACH_DECL_NEW(a9tmr, 0, a9tmr_match, a9tmr_attach, NULL, NULL); 72 73 static inline uint32_t 74 a9tmr_global_read(struct a9tmr_softc *sc, bus_size_t o) 75 { 76 return bus_space_read_4(sc->sc_memt, sc->sc_global_memh, o); 77 } 78 79 static inline void 80 a9tmr_global_write(struct a9tmr_softc *sc, bus_size_t o, uint32_t v) 81 { 82 bus_space_write_4(sc->sc_memt, sc->sc_global_memh, o, v); 83 } 84 85 86 /* ARGSUSED */ 87 static int 88 a9tmr_match(device_t parent, cfdata_t cf, void *aux) 89 { 90 struct mpcore_attach_args * const mpcaa = aux; 91 92 if (a9tmr_sc.sc_dev != NULL) 93 return 0; 94 95 if (!CPU_ID_CORTEX_A9_P(curcpu()->ci_arm_cpuid)) 96 return 0; 97 98 if (strcmp(mpcaa->mpcaa_name, cf->cf_name) != 0) 99 return 0; 100 101 /* 102 * This isn't present on UP A9s (since CBAR isn't present). 103 */ 104 uint32_t mpidr = armreg_mpidr_read(); 105 if (mpidr == 0 || (mpidr & MPIDR_U)) 106 return 0; 107 108 return 1; 109 } 110 111 static void 112 a9tmr_attach(device_t parent, device_t self, void *aux) 113 { 114 struct a9tmr_softc *sc = &a9tmr_sc; 115 struct mpcore_attach_args * const mpcaa = aux; 116 prop_dictionary_t dict = device_properties(self); 117 char freqbuf[sizeof("XXX SHz")]; 118 119 /* 120 * This runs at the ARM PERIPHCLOCK which should be 1/2 of the CPU clock. 121 * The MD code should have setup our frequency for us. 122 */ 123 prop_number_t pn = prop_dictionary_get(dict, "frequency"); 124 KASSERT(pn != NULL); 125 sc->sc_freq = prop_number_unsigned_integer_value(pn); 126 127 humanize_number(freqbuf, sizeof(freqbuf), sc->sc_freq, "Hz", 1000); 128 129 aprint_naive("\n"); 130 aprint_normal(": A9 Global 64-bit Timer (%s)\n", freqbuf); 131 132 sc->sc_dev = self; 133 sc->sc_memt = mpcaa->mpcaa_memt; 134 sc->sc_memh = mpcaa->mpcaa_memh; 135 136 bus_space_subregion(sc->sc_memt, sc->sc_memh, 137 TMR_GLOBAL_BASE, TMR_GLOBAL_BASE, &sc->sc_global_memh); 138 bus_space_subregion(sc->sc_memt, sc->sc_memh, 139 TMR_PRIVATE_BASE, TMR_PRIVATE_SIZE, &sc->sc_private_memh); 140 bus_space_subregion(sc->sc_memt, sc->sc_memh, 141 TMR_WDOG_BASE, TMR_WDOG_SIZE, &sc->sc_wdog_memh); 142 143 sc->sc_global_ih = intr_establish(IRQ_A9TMR_PPI_GTIMER, IPL_CLOCK, 144 IST_EDGE, clockhandler, NULL); 145 if (sc->sc_global_ih == NULL) 146 panic("%s: unable to register timer interrupt", __func__); 147 aprint_normal_dev(sc->sc_dev, "interrupting on irq %d\n", 148 IRQ_A9TMR_PPI_GTIMER); 149 } 150 151 static inline uint64_t 152 a9tmr_gettime(struct a9tmr_softc *sc) 153 { 154 uint32_t lo, hi; 155 156 do { 157 hi = a9tmr_global_read(sc, TMR_GBL_CTR_U); 158 lo = a9tmr_global_read(sc, TMR_GBL_CTR_L); 159 } while (hi != a9tmr_global_read(sc, TMR_GBL_CTR_U)); 160 161 return ((uint64_t)hi << 32) | lo; 162 } 163 164 void 165 a9tmr_init_cpu_clock(struct cpu_info *ci) 166 { 167 struct a9tmr_softc * const sc = &a9tmr_sc; 168 uint64_t now = a9tmr_gettime(sc); 169 170 KASSERT(ci == curcpu()); 171 172 ci->ci_lastintr = now; 173 174 a9tmr_global_write(sc, TMR_GBL_AUTOINC, sc->sc_autoinc); 175 176 /* 177 * To update the compare register we have to disable comparisions first. 178 */ 179 uint32_t ctl = a9tmr_global_read(sc, TMR_GBL_CTL); 180 if (ctl & TMR_GBL_CTL_CMP_ENABLE) { 181 a9tmr_global_write(sc, TMR_GBL_CTL, ctl & ~TMR_GBL_CTL_CMP_ENABLE); 182 } 183 184 /* 185 * Schedule the next interrupt. 186 */ 187 now += sc->sc_autoinc; 188 a9tmr_global_write(sc, TMR_GBL_CMP_L, (uint32_t) now); 189 a9tmr_global_write(sc, TMR_GBL_CMP_H, (uint32_t) (now >> 32)); 190 191 /* 192 * Re-enable the comparator and now enable interrupts. 193 */ 194 a9tmr_global_write(sc, TMR_GBL_INT, 1); /* clear interrupt pending */ 195 ctl |= TMR_GBL_CTL_CMP_ENABLE | TMR_GBL_CTL_INT_ENABLE | TMR_GBL_CTL_AUTO_INC; 196 a9tmr_global_write(sc, TMR_GBL_CTL, ctl); 197 #if 0 198 printf("%s: %s: ctl %#x autoinc %u cmp %#x%08x now %#"PRIx64"\n", 199 __func__, ci->ci_data.cpu_name, 200 a9tmr_global_read(sc, TMR_GBL_CTL), 201 a9tmr_global_read(sc, TMR_GBL_AUTOINC), 202 a9tmr_global_read(sc, TMR_GBL_CMP_H), 203 a9tmr_global_read(sc, TMR_GBL_CMP_L), 204 a9tmr_gettime(sc)); 205 206 int s = splsched(); 207 uint64_t when = now; 208 u_int n = 0; 209 while ((now = a9tmr_gettime(sc)) < when) { 210 /* spin */ 211 n++; 212 KASSERTMSG(n <= sc->sc_autoinc, 213 "spun %u times but only %"PRIu64" has passed", 214 n, when - now); 215 } 216 printf("%s: %s: status %#x cmp %#x%08x now %#"PRIx64"\n", 217 __func__, ci->ci_data.cpu_name, 218 a9tmr_global_read(sc, TMR_GBL_INT), 219 a9tmr_global_read(sc, TMR_GBL_CMP_H), 220 a9tmr_global_read(sc, TMR_GBL_CMP_L), 221 a9tmr_gettime(sc)); 222 splx(s); 223 #elif 0 224 delay(1000000 / hz + 1000); 225 #endif 226 } 227 228 void 229 cpu_initclocks(void) 230 { 231 struct a9tmr_softc * const sc = &a9tmr_sc; 232 233 KASSERT(sc->sc_dev != NULL); 234 KASSERT(sc->sc_freq != 0); 235 236 sc->sc_autoinc = sc->sc_freq / hz; 237 238 a9tmr_init_cpu_clock(curcpu()); 239 240 a9tmr_timecounter.tc_name = device_xname(sc->sc_dev); 241 a9tmr_timecounter.tc_frequency = sc->sc_freq; 242 243 tc_init(&a9tmr_timecounter); 244 } 245 246 void 247 a9tmr_delay(unsigned int n) 248 { 249 struct a9tmr_softc * const sc = &a9tmr_sc; 250 251 KASSERT(sc != NULL); 252 253 uint32_t freq = sc->sc_freq ? sc->sc_freq : curcpu()->ci_data.cpu_cc_freq / 2; 254 KASSERT(freq != 0); 255 256 /* 257 * not quite divide by 1000000 but close enough 258 * (higher by 1.3% which means we wait 1.3% longer). 259 */ 260 const uint64_t incr_per_us = (freq >> 20) + (freq >> 24); 261 262 const uint64_t delta = n * incr_per_us; 263 const uint64_t base = a9tmr_gettime(sc); 264 const uint64_t finish = base + delta; 265 266 while (a9tmr_gettime(sc) < finish) { 267 /* spin */ 268 } 269 } 270 271 /* 272 * clockhandler: 273 * 274 * Handle the hardclock interrupt. 275 */ 276 static int 277 clockhandler(void *arg) 278 { 279 struct clockframe * const cf = arg; 280 struct a9tmr_softc * const sc = &a9tmr_sc; 281 struct cpu_info * const ci = curcpu(); 282 283 const uint64_t now = a9tmr_gettime(sc); 284 uint64_t delta = now - ci->ci_lastintr; 285 286 a9tmr_global_write(sc, TMR_GBL_INT, 1); // Ack the interrupt 287 288 #if 0 289 printf("%s(%p): %s: now %#"PRIx64" delta %"PRIu64"\n", 290 __func__, cf, ci->ci_data.cpu_name, now, delta); 291 #endif 292 KASSERTMSG(delta > sc->sc_autoinc / 100, 293 "%s: interrupting too quickly (delta=%"PRIu64")", 294 ci->ci_data.cpu_name, delta); 295 296 ci->ci_lastintr = now; 297 298 hardclock(cf); 299 300 /* 301 * Try to make up up to a seconds amount of missed clock interrupts 302 */ 303 u_int ticks = hz; 304 for (delta -= sc->sc_autoinc; 305 ticks > 0 && delta >= sc->sc_autoinc; 306 delta -= sc->sc_autoinc, ticks--) { 307 hardclock(cf); 308 } 309 310 return 1; 311 } 312 313 void 314 setstatclockrate(int newhz) 315 { 316 } 317 318 static u_int 319 a9tmr_get_timecount(struct timecounter *tc) 320 { 321 struct a9tmr_softc * const sc = tc->tc_priv; 322 323 return bus_space_read_4(sc->sc_memt, sc->sc_global_memh, TMR_GBL_CTR_L); 324 } 325
Indexes created Tue Sep 30 20:09:53 GMT 2025