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History log of /src/sys/arch/arm/cortex/a9tmr.c
RevisionDateAuthorComments
 1.22  03-Mar-2022  riastradh arm: Use device_set_private for various drivers.
 1.21  02-Dec-2020  wiz comparision -> comparison
 1.20  11-Jun-2019  skrll branches: 1.20.10;
Trailing whitespace
 1.19  22-Nov-2018  aymeric Switch the DE0 Nano SoC to the GENERIC kernel.
 1.18  28-Oct-2018  aymeric Enable the global timer at attach time, it ensures that delay() works.
 1.17  14-Oct-2018  aymeric Remove comment that the peripherals clock should be half of the cpu clock.
NFC
 1.16  20-Jun-2018  hkenken branches: 1.16.2;
Use mpcaa_off1 parameter for mapping subregion.
 1.15  05-Jun-2018  hkenken Rename ARM A9 Global Timer driver name to support fdt.

- Rename a9tmr to arma9tmr.
- Add a9tmr_fdt.c based gtmr_fdt.c.
 1.14  24-Jul-2015  ryo branches: 1.14.16;
KNF
 1.13  24-Jul-2015  ryo - fix sc_ev_missing_ticks over-counting.
- don't use 64bit division, because it has expensive cost on gcc/arm
whether it is a constant or not.

'delta' is usually taken a value around sc_autoinc depending on timing
of read. therefore 'delta / sc->sc_autoinc' would be count too much.
 1.12  04-Mar-2015  jmcneill print "A5" instead of "A9" at attach time if running on a Cortex-A5
 1.11  27-Feb-2015  jmcneill match on Cortex-A5
 1.10  08-Jan-2015  hkenken fix typo
 1.9  02-Jan-2015  jmcneill detach and re-attach timecounter when updating freq, and reinit timer on each cpu
 1.8  02-Jan-2015  jmcneill add a helper to update a9tmr frequency
 1.7  28-Mar-2014  matt branches: 1.7.4; 1.7.6;
Mark interrupt as MPSAFE.
 1.6  20-Jun-2013  matt branches: 1.6.2; 1.6.6;
Pass the offset from CBAR/PERIPHBASE in mpcore_attach_args.
Modify the list of devices to include the offset(s) from PERIPHBASE.
 1.5  12-Jun-2013  matt Don't attach a9tmr if the CPU supports the generic timer.
 1.4  29-Nov-2012  matt Make sure we enable the timer since CFE doesn't enable it by default.
 1.3  27-Sep-2012  matt branches: 1.3.2; 1.3.4;
Don't bother dealing with "extra" ticks, just count them.
 1.2  14-Sep-2012  matt Set dv_private, use a9tmr_private.
 1.1  01-Sep-2012  matt branches: 1.1.2;
Add Cortex-A9 support including the ARM Generic Interrupt Controller
and the A9 Global Timer / Watchdog.
 1.1.2.5  03-Dec-2017  jdolecek update from HEAD
 1.1.2.4  20-Aug-2014  tls Rebase to HEAD as of a few days ago.
 1.1.2.3  23-Jun-2013  tls resync from head
 1.1.2.2  25-Feb-2013  tls resync with head
 1.1.2.1  20-Nov-2012  tls Resync to 2012-11-19 00:00:00 UTC
 1.3.4.3  29-Nov-2012  matt Sync with HEAD.
 1.3.4.2  28-Nov-2012  matt Merge improved arm support (especially Cortex) from HEAD
including OMAP and BCM53xx support.
 1.3.4.1  27-Sep-2012  matt file a9tmr.c was added on branch matt-nb6-plus on 2012-11-28 22:40:25 +0000
 1.3.2.4  22-May-2014  yamt sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
 1.3.2.3  16-Jan-2013  yamt sync with (a bit old) head
 1.3.2.2  30-Oct-2012  yamt sync with head
 1.3.2.1  27-Sep-2012  yamt file a9tmr.c was added on branch yamt-pagecache on 2012-10-30 17:19:00 +0000
 1.6.6.2  15-Feb-2014  matt Merge armv7 support from HEAD, specifically support for the BCM5301X
and BCM56340 evbarm kernels.
 1.6.6.1  20-Jun-2013  matt file a9tmr.c was added on branch matt-nb5-mips64 on 2014-02-15 16:18:36 +0000
 1.6.2.1  18-May-2014  rmind sync with head
 1.7.6.2  22-Sep-2015  skrll Sync with HEAD
 1.7.6.1  06-Apr-2015  skrll Sync with HEAD
 1.7.4.1  21-Mar-2015  snj Pull up following revision(s) (requested by jmcneill in ticket #598):
sys/arch/arm/amlogic/amlogic_board.c: up to revision 1.9
sys/arch/arm/amlogic/amlogic_canvasreg.h: revision 1.1
sys/arch/arm/amlogic/amlogic_com.c: up to revision 1.4
sys/arch/arm/amlogic/amlogic_comreg.h: up to revision 1.3
sys/arch/arm/amlogic/amlogic_comvar.h: revision 1.1
sys/arch/arm/amlogic/amlogic_cpufreq.c: up to revision 1.2
sys/arch/arm/amlogic/amlogic_crureg.h: up to revision 1.7
sys/arch/arm/amlogic/amlogic_dwctwo.c: up to revision 1.2
sys/arch/arm/amlogic/amlogic_genfb.c: revision 1.1
sys/arch/arm/amlogic/amlogic_gmac.c: up to revision 1.2
sys/arch/arm/amlogic/amlogic_hdmireg.h: revision 1.1
sys/arch/arm/amlogic/amlogic_intr.h: up to revision 1.5
sys/arch/arm/amlogic/amlogic_io.c: up to revision 1.7
sys/arch/arm/amlogic/amlogic_reg.h: up to revision 1.9
sys/arch/arm/amlogic/amlogic_rng.c: revision 1.1
sys/arch/arm/amlogic/amlogic_sdhc.c: up to revision 1.3
sys/arch/arm/amlogic/amlogic_sdhcreg.h: revision 1.1
sys/arch/arm/amlogic/amlogic_space.c: revision 1.1
sys/arch/arm/amlogic/amlogic_var.h: up to revision 1.8
sys/arch/arm/amlogic/amlogic_vpureg.h: revision 1.1
sys/arch/arm/arm/bootconfig.c: revisions 1.7-1.8
sys/arch/arm/conf/files.arm: revision 1.129
sys/arch/arm/cortex/pl310.c: revisions 1.16-1.17
sys/arch/arm/cortex/a9_mpsubr.S: revisions 1.25-1.29
sys/arch/arm/cortex/a9tmr.c: revisions 1.8-1.12
sys/arch/arm/cortex/a9tmr_var.h: revision 1.4
sys/arch/arm/cortex/a9wdt.c: revisions 1.3-1.4
sys/arch/arm/cortex/armperiph.c: revisions 1.5-1.7
sys/arch/arm/arm/cpufunc.c: revision 1.151
sys/arch/arm/include/bootconfig.h: revision 1.7
sys/arch/arm/include/locore.h: revision 1.19
sys/arch/evbarm/amlogic/amlogic_machdep.c: up to revision 1.17
sys/arch/evbarm/amlogic/amlogic_start.S: up to revision 1.2
sys/arch/evbarm/amlogic/genassym.cf: revision 1.1
sys/arch/evbarm/amlogic/platform.h: revision 1.1
sys/arch/evbarm/conf/files.amlogic: up to revision 1.8
sys/arch/evbarm/conf/std.amlogic: up to revision 1.2
sys/arch/evbarm/conf/mk.amlogic: revision 1.1
sys/arch/evbarm/conf/ODROID-C1: up to revision 1.12
sys/arch/evarm/conf/ODROID-C1_INSTALL: revision 1.1
Don't use not as a variable since it's reserved in C++.
--
clean the a9 l2 cache before turning it on.
--
Add Cortex-A17 support
--
Fix CORTEXA17 support
--
Let the "cbar" device property override the cbar value, to work around
broken bootloaders
--
add a helper to update a9tmr frequency
--
detach and re-attach timecounter when updating freq, and reinit timer on
each cpu
--
fix typo
--
add BOOTOPT_TYPE_MACADDR for parsing mac address parameters
--
make sure we set ACTLR.SMP=1 for CPU_CORTEXA5 in !MP case, ok matt@
--
According to the Cortex-A5 TRM, the CBAR register is not implemented and
always reads as 0x00000000. Add ARM_CBAR option to set this in kernel
config.
--
skip a TLBIALL on Cortex-A5 that stops my odroid-c1 from booting, ok matt
--
match on Cortex-A5
--
match on Cortex-A5
--
allow arml2cc to be used on Cortex-A5 if the "offset" property is specified
--
print "A5" instead of "A9" at attach time if running on a Cortex-A5
--
Improve inline asm around dsb/dmb/isb:
- always use volatile and mark them as memory barrier
- use the common version from locore.h in all places not included from
userland
--
Work-in-progress Odroid-C1 support.
--
no need to override ARM_CBAR, remove unused COM_16750 option
--
Add basic serial console support.
--
add dwctwo and usb devices
--
ODROID-C1 SMP support.
--
auto-detect RAM size
--
ODROID-C1 onboard ethernet support.
--
add amlogicrng, add commented-out genfb placeholder
--
enable amlogicsdhc
--
add ODROID-C1 install kernel
--
Add CPUFREQ option to set boot CPU frequency. ODROID-C1 is advertised
as quad-core 1.5GHz but boots up at 1.2GHz; add CPUFREQ=1512 to config
and make sure to set the correct speed before attaching CPUs.
The speed can still be scaled down with machdep.cpu sysctls.
--
disable DEBUG, LOCKDEBUG, VERBOSE_INIT_ARM
--
Basic framebuffer console support. Work in progress.
 1.14.16.3  26-Nov-2018  pgoyette Sync with HEAD, resolve a couple of conflicts
 1.14.16.2  20-Oct-2018  pgoyette Sync with head
 1.14.16.1  25-Jun-2018  pgoyette Sync with HEAD
 1.16.2.2  13-Apr-2020  martin Mostly merge changes from HEAD upto 20200411
 1.16.2.1  10-Jun-2019  christos Sync with HEAD
 1.20.10.1  14-Dec-2020  thorpej Sync w/ HEAD.

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