a9tmr.c revision 1.6
1 /* $NetBSD: a9tmr.c,v 1.6 2013/06/20 05:30:21 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: a9tmr.c,v 1.6 2013/06/20 05:30:21 matt Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/device.h> 38 #include <sys/intr.h> 39 #include <sys/kernel.h> 40 #include <sys/proc.h> 41 #include <sys/systm.h> 42 #include <sys/timetc.h> 43 44 #include <prop/proplib.h> 45 46 #include <arm/cortex/a9tmr_reg.h> 47 #include <arm/cortex/a9tmr_var.h> 48 49 #include <arm/cortex/mpcore_var.h> 50 51 static int a9tmr_match(device_t, cfdata_t, void *); 52 static void a9tmr_attach(device_t, device_t, void *); 53 54 static int clockhandler(void *); 55 56 static u_int a9tmr_get_timecount(struct timecounter *); 57 58 static struct a9tmr_softc a9tmr_sc; 59 60 static struct timecounter a9tmr_timecounter = { 61 .tc_get_timecount = a9tmr_get_timecount, 62 .tc_poll_pps = 0, 63 .tc_counter_mask = ~0u, 64 .tc_frequency = 0, /* set by cpu_initclocks() */ 65 .tc_name = NULL, /* set by attach */ 66 .tc_quality = 500, 67 .tc_priv = &a9tmr_sc, 68 .tc_next = NULL, 69 }; 70 71 CFATTACH_DECL_NEW(a9tmr, 0, a9tmr_match, a9tmr_attach, NULL, NULL); 72 73 static inline uint32_t 74 a9tmr_global_read(struct a9tmr_softc *sc, bus_size_t o) 75 { 76 return bus_space_read_4(sc->sc_memt, sc->sc_global_memh, o); 77 } 78 79 static inline void 80 a9tmr_global_write(struct a9tmr_softc *sc, bus_size_t o, uint32_t v) 81 { 82 bus_space_write_4(sc->sc_memt, sc->sc_global_memh, o, v); 83 } 84 85 86 /* ARGSUSED */ 87 static int 88 a9tmr_match(device_t parent, cfdata_t cf, void *aux) 89 { 90 struct mpcore_attach_args * const mpcaa = aux; 91 92 if (a9tmr_sc.sc_dev != NULL) 93 return 0; 94 95 if ((armreg_pfr1_read() & ARM_PFR1_GTIMER_MASK) != 0) 96 return 0; 97 98 if (!CPU_ID_CORTEX_A9_P(curcpu()->ci_arm_cpuid)) 99 return 0; 100 101 if (strcmp(mpcaa->mpcaa_name, cf->cf_name) != 0) 102 return 0; 103 104 /* 105 * This isn't present on UP A9s (since CBAR isn't present). 106 */ 107 uint32_t mpidr = armreg_mpidr_read(); 108 if (mpidr == 0 || (mpidr & MPIDR_U)) 109 return 0; 110 111 return 1; 112 } 113 114 static void 115 a9tmr_attach(device_t parent, device_t self, void *aux) 116 { 117 struct a9tmr_softc *sc = &a9tmr_sc; 118 struct mpcore_attach_args * const mpcaa = aux; 119 prop_dictionary_t dict = device_properties(self); 120 char freqbuf[sizeof("XXX SHz")]; 121 122 /* 123 * This runs at the ARM PERIPHCLOCK which should be 1/2 of the CPU clock. 124 * The MD code should have setup our frequency for us. 125 */ 126 prop_dictionary_get_uint32(dict, "frequency", &sc->sc_freq); 127 128 humanize_number(freqbuf, sizeof(freqbuf), sc->sc_freq, "Hz", 1000); 129 130 aprint_naive("\n"); 131 aprint_normal(": A9 Global 64-bit Timer (%s)\n", freqbuf); 132 133 self->dv_private = sc; 134 sc->sc_dev = self; 135 sc->sc_memt = mpcaa->mpcaa_memt; 136 sc->sc_memh = mpcaa->mpcaa_memh; 137 138 evcnt_attach_dynamic(&sc->sc_ev_missing_ticks, EVCNT_TYPE_MISC, NULL, 139 device_xname(self), "missing interrupts"); 140 141 bus_space_subregion(sc->sc_memt, sc->sc_memh, 142 TMR_GLOBAL_BASE, TMR_GLOBAL_BASE, &sc->sc_global_memh); 143 bus_space_subregion(sc->sc_memt, sc->sc_memh, 144 TMR_PRIVATE_BASE, TMR_PRIVATE_SIZE, &sc->sc_private_memh); 145 bus_space_subregion(sc->sc_memt, sc->sc_memh, 146 TMR_WDOG_BASE, TMR_WDOG_SIZE, &sc->sc_wdog_memh); 147 148 sc->sc_global_ih = intr_establish(IRQ_A9TMR_PPI_GTIMER, IPL_CLOCK, 149 IST_EDGE, clockhandler, NULL); 150 if (sc->sc_global_ih == NULL) 151 panic("%s: unable to register timer interrupt", __func__); 152 aprint_normal_dev(sc->sc_dev, "interrupting on irq %d\n", 153 IRQ_A9TMR_PPI_GTIMER); 154 } 155 156 static inline uint64_t 157 a9tmr_gettime(struct a9tmr_softc *sc) 158 { 159 uint32_t lo, hi; 160 161 do { 162 hi = a9tmr_global_read(sc, TMR_GBL_CTR_U); 163 lo = a9tmr_global_read(sc, TMR_GBL_CTR_L); 164 } while (hi != a9tmr_global_read(sc, TMR_GBL_CTR_U)); 165 166 return ((uint64_t)hi << 32) | lo; 167 } 168 169 void 170 a9tmr_init_cpu_clock(struct cpu_info *ci) 171 { 172 struct a9tmr_softc * const sc = &a9tmr_sc; 173 uint64_t now = a9tmr_gettime(sc); 174 175 KASSERT(ci == curcpu()); 176 177 ci->ci_lastintr = now; 178 179 a9tmr_global_write(sc, TMR_GBL_AUTOINC, sc->sc_autoinc); 180 181 /* 182 * To update the compare register we have to disable comparisions first. 183 */ 184 uint32_t ctl = a9tmr_global_read(sc, TMR_GBL_CTL); 185 if (ctl & TMR_GBL_CTL_CMP_ENABLE) { 186 a9tmr_global_write(sc, TMR_GBL_CTL, ctl & ~TMR_GBL_CTL_CMP_ENABLE); 187 } 188 189 /* 190 * Schedule the next interrupt. 191 */ 192 now += sc->sc_autoinc; 193 a9tmr_global_write(sc, TMR_GBL_CMP_L, (uint32_t) now); 194 a9tmr_global_write(sc, TMR_GBL_CMP_H, (uint32_t) (now >> 32)); 195 196 /* 197 * Re-enable the comparator and now enable interrupts. 198 */ 199 a9tmr_global_write(sc, TMR_GBL_INT, 1); /* clear interrupt pending */ 200 ctl |= TMR_GBL_CTL_CMP_ENABLE | TMR_GBL_CTL_INT_ENABLE | TMR_GBL_CTL_AUTO_INC | TMR_CTL_ENABLE; 201 a9tmr_global_write(sc, TMR_GBL_CTL, ctl); 202 #if 0 203 printf("%s: %s: ctl %#x autoinc %u cmp %#x%08x now %#"PRIx64"\n", 204 __func__, ci->ci_data.cpu_name, 205 a9tmr_global_read(sc, TMR_GBL_CTL), 206 a9tmr_global_read(sc, TMR_GBL_AUTOINC), 207 a9tmr_global_read(sc, TMR_GBL_CMP_H), 208 a9tmr_global_read(sc, TMR_GBL_CMP_L), 209 a9tmr_gettime(sc)); 210 211 int s = splsched(); 212 uint64_t when = now; 213 u_int n = 0; 214 while ((now = a9tmr_gettime(sc)) < when) { 215 /* spin */ 216 n++; 217 KASSERTMSG(n <= sc->sc_autoinc, 218 "spun %u times but only %"PRIu64" has passed", 219 n, when - now); 220 } 221 printf("%s: %s: status %#x cmp %#x%08x now %#"PRIx64"\n", 222 __func__, ci->ci_data.cpu_name, 223 a9tmr_global_read(sc, TMR_GBL_INT), 224 a9tmr_global_read(sc, TMR_GBL_CMP_H), 225 a9tmr_global_read(sc, TMR_GBL_CMP_L), 226 a9tmr_gettime(sc)); 227 splx(s); 228 #elif 0 229 delay(1000000 / hz + 1000); 230 #endif 231 } 232 233 void 234 cpu_initclocks(void) 235 { 236 struct a9tmr_softc * const sc = &a9tmr_sc; 237 238 KASSERT(sc->sc_dev != NULL); 239 KASSERT(sc->sc_freq != 0); 240 241 sc->sc_autoinc = sc->sc_freq / hz; 242 243 a9tmr_init_cpu_clock(curcpu()); 244 245 a9tmr_timecounter.tc_name = device_xname(sc->sc_dev); 246 a9tmr_timecounter.tc_frequency = sc->sc_freq; 247 248 tc_init(&a9tmr_timecounter); 249 } 250 251 void 252 a9tmr_delay(unsigned int n) 253 { 254 struct a9tmr_softc * const sc = &a9tmr_sc; 255 256 KASSERT(sc != NULL); 257 258 uint32_t freq = sc->sc_freq ? sc->sc_freq : curcpu()->ci_data.cpu_cc_freq / 2; 259 KASSERT(freq != 0); 260 261 /* 262 * not quite divide by 1000000 but close enough 263 * (higher by 1.3% which means we wait 1.3% longer). 264 */ 265 const uint64_t incr_per_us = (freq >> 20) + (freq >> 24); 266 267 const uint64_t delta = n * incr_per_us; 268 const uint64_t base = a9tmr_gettime(sc); 269 const uint64_t finish = base + delta; 270 271 while (a9tmr_gettime(sc) < finish) { 272 /* spin */ 273 } 274 } 275 276 /* 277 * clockhandler: 278 * 279 * Handle the hardclock interrupt. 280 */ 281 static int 282 clockhandler(void *arg) 283 { 284 struct clockframe * const cf = arg; 285 struct a9tmr_softc * const sc = &a9tmr_sc; 286 struct cpu_info * const ci = curcpu(); 287 288 const uint64_t now = a9tmr_gettime(sc); 289 uint64_t delta = now - ci->ci_lastintr; 290 291 a9tmr_global_write(sc, TMR_GBL_INT, 1); // Ack the interrupt 292 293 #if 0 294 printf("%s(%p): %s: now %#"PRIx64" delta %"PRIu64"\n", 295 __func__, cf, ci->ci_data.cpu_name, now, delta); 296 #endif 297 KASSERTMSG(delta > sc->sc_autoinc / 100, 298 "%s: interrupting too quickly (delta=%"PRIu64")", 299 ci->ci_data.cpu_name, delta); 300 301 ci->ci_lastintr = now; 302 303 hardclock(cf); 304 305 #if 0 306 /* 307 * Try to make up up to a seconds amount of missed clock interrupts 308 */ 309 u_int ticks = hz; 310 for (delta -= sc->sc_autoinc; 311 ticks > 0 && delta >= sc->sc_autoinc; 312 delta -= sc->sc_autoinc, ticks--) { 313 hardclock(cf); 314 } 315 #else 316 if (delta > sc->sc_autoinc) 317 sc->sc_ev_missing_ticks.ev_count += delta / sc->sc_autoinc; 318 #endif 319 320 return 1; 321 } 322 323 void 324 setstatclockrate(int newhz) 325 { 326 } 327 328 static u_int 329 a9tmr_get_timecount(struct timecounter *tc) 330 { 331 struct a9tmr_softc * const sc = tc->tc_priv; 332 333 return (u_int) (a9tmr_gettime(sc)); 334 } 335
Indexes created Wed Sep 24 05:09:52 GMT 2025